TWI767186B - Oxide semiconductor thin films, thin film transistors and sputtering targets - Google Patents

Abstract

The present invention provides an oxide semiconductor thin film from which a thin film transistor excellent in stress tolerance can be obtained. The oxide semiconductor thin film has a first oxide semiconductor layer and a second oxide semiconductor layer, and the first oxide semiconductor layer and the second oxide semiconductor layer respectively contain In, Ga, Zn, Sn, and O as metal elements, and In the first oxide semiconductor layer, 0.05≦In/(In+Ga+Zn+Sn)≦0.25, 0.20≦Ga/(In+Ga+Zn+Sn)≦0.60, 0.20≦Zn/(In+Ga+ Zn+Sn)≦0.60, 0.05≦Sn/(In+Ga+Zn+Sn)≦0.15, in the second oxide semiconductor layer, 0.20≦In/(In+Ga+Zn+Sn)≦0.60, 0.05 ≦Ga/(In+Ga+Zn+Sn)≦0.25, 0.15≦Zn/(In+Ga+Zn+Sn)≦0.60, 0.01≦Sn/(In+Ga+Zn+Sn)≦0.20.

Description

Oxide semiconductor thin films, thin film transistors and sputtering targets

The present invention relates to an oxide semiconductor film and a thin film transistor (Thin Film Transistor, TFT) including an oxide semiconductor layer including the oxide semiconductor film. More specifically, the present invention relates to a thin film transistor suitable for use in a display device such as a liquid crystal display or an organic electroluminescence (EL) display, and an oxide semiconductor thin film contained in the thin film transistor. In addition, the present invention also relates to a sputtering target for forming an oxide semiconductor layer including the oxide semiconductor thin film.

Amorphous (amorphous) oxide semiconductors have a higher carrier concentration than general-purpose amorphous silicon (a-Si), and are expected to be used in applications requiring large-scale/high-resolution/high-speed drive generation of monitors. In addition, the amorphous oxide semiconductor has a large optical band gap and can be formed into a film at low temperature, so that it can be formed on a resin substrate with low heat resistance, and it is also expected to be applied to a light and transparent display.

As such an amorphous oxide semiconductor, for example, as shown in Patent Document 1, an In-Ga-Zn-based non-crystalline oxide containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) is known. Crystalline oxide semiconductor (hereinafter sometimes abbreviated as "IGZO").

[Prior Art Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2010-219538

However, the field effect mobility (carrier mobility) of a thin film transistor including an oxide semiconductor layer including IGZO is higher than that of general-purpose amorphous silicon, but it is about 10 cm ² /Vs. , high-definition or high-speed driving, seeking materials with higher field-effect mobility.

In addition, a thin film transistor using an oxide semiconductor layer containing IGZO is required to be excellent in resistance (stress resistance) to stresses such as light irradiation and voltage application. That is, it is required that the threshold value change amount of the thin film transistor is small with respect to stress such as light irradiation or voltage application. For example, when a voltage is continuously applied to the gate electrode, or when light in the blue range that causes absorption is continuously irradiated in the semiconductor layer, charges are trapped at the interface between the gate insulating film of the thin film transistor and the semiconductor layer, The threshold value voltage can be greatly changed (shifted) to the negative side due to the change in electric charge inside the semiconductor layer. As a result, it was pointed out that the switching characteristics of the thin film transistor changed.

Furthermore, when the liquid crystal panel is driven, or when a negative bias is applied to the gate electrode to turn on the pixel, the light leaking from the liquid crystal cell is irradiated to the TFT, but the light affects the thin film transistor. stress and cause image unevenness or characteristic deterioration. When thin-film transistors are used in practice, if the switching characteristics are changed due to the stress caused by light irradiation or voltage application, the reliability of the display device itself will be degraded. Low.

In addition, in the organic EL display, leakage light from the light-emitting layer is also irradiated to the semiconductor layer, causing problems such as variations in values of threshold voltage and the like.

Such a shift in the threshold voltage leads to a decrease in the reliability of display devices such as liquid crystal displays and organic EL displays provided with thin film transistors. Therefore, it is strongly desired to improve stress tolerance (that is, to reduce the amount of change before and after stress is applied). .

Furthermore, the structure of the thin film transistor including the oxide semiconductor layer as described above is roughly classified into a Back Channel Etch (BCE) type without an etch stop layer, and an etch stop (etch stop layer) type with an etch stop layer. (Etch Stopper Layer, ESL)) type of these two. Among them, from the viewpoint of simplification of the production steps of the thin film transistor, a BCE type structure without an etch stop layer is recommended.

In addition, as electrode materials for gate electrodes, source/drain electrodes, etc. of thin film transistors, in order to further improve the performance of display devices, materials with lower resistances have begun to be sought. In order to satisfy such a demand, Cu electrodes or Cu alloy electrodes have been used instead of the Al alloy electrodes previously used, and when these wirings are formed, etching solutions such as hydrogen peroxide are used.

However, when a Cu electrode or a Cu alloy electrode is used in the thin film transistor of the BCE type structure, the oxide semiconductor is exposed to an etchant such as hydrogen peroxide used for wet etching of the source/drain electrodes. , there is a possibility that the oxide semiconductor layer is damaged and the characteristics of the thin film transistor are degraded.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide an oxide semiconductor thin film from which a thin film transistor excellent in stress tolerance can be obtained.

Another object of the present invention is to provide a thin film transistor including an oxide semiconductor layer including the oxide semiconductor thin film and capable of maintaining high field-effect mobility, and a sputtering target for forming the oxide semiconductor layer.

The inventors of the present invention have repeatedly studied and found that by using oxide semiconductors containing In, Ga, Zn, Sn, and O as metal elements, and by appropriately controlling the compositions of these metal elements, it is possible to The above-mentioned problems have been solved, and the present invention has been completed. In addition, the inventors found that the above-mentioned problems can be solved by using the oxide semiconductor thin film in a thin film transistor, thereby completing the present invention.

That is, the said object of this invention can be achieved by the following [1] structure concerning an oxide semiconductor thin film.

[1] An oxide semiconductor thin film having a first oxide semiconductor layer and a second oxide semiconductor layer, wherein the first oxide semiconductor layer and the second oxide semiconductor layer respectively contain In as a metal element, Ga, Zn, Sn, and O, and the atomic ratio of each metal element in the first oxide semiconductor layer to the total of In, Ga, Zn, and Sn satisfies

0.05≦In/(In+Ga+Zn+Sn)≦0.25

0.20≦Ga/(In+Ga+Zn+Sn)≦0.60

0.20≦Zn/(In+Ga+Zn+Sn)≦0.60

0.05≦Sn/(In+Ga+Zn+Sn)≦0.15, each metal element in the second oxide semiconductor layer is relative to the In, The total atomic ratio of Ga, Zn, and Sn satisfies

0.20≦In/(In+Ga+Zn+Sn)≦0.60

0.05≦Ga/(In+Ga+Zn+Sn)≦0.25

0.15≦Zn/(In+Ga+Zn+Sn)≦0.60

0.01≦Sn/(In+Ga+Zn+Sn)≦0.20.

In addition, the preferred embodiment of the present invention related to the oxide semiconductor thin film is related to the following [2].

[2] The oxide semiconductor thin film according to the above [1], wherein in the first oxide semiconductor layer, the atomic ratio of In to the sum of In and Sn satisfies 0.30≦In/(In+Sn )≦0.75.

Moreover, the said objective of this invention can be achieved by the following [3] structure concerning a thin film transistor.

[3] A thin film transistor characterized by having a gate electrode, a gate insulating film, and an oxide semiconductor layer including the oxide semiconductor thin film according to [1] or [2] in this order on a substrate , source/drain electrodes and protective film.

In addition, preferred embodiments of the present invention related to thin film transistors are related to the following [4].

[4] The thin film transistor according to the above [3], wherein the source/drain electrodes contain Cu or a Cu alloy.

Moreover, the said objective of this invention can be achieved by the structure of the following [5] concerning a sputtering target.

[5] A sputtering target for forming the thin film electrode described in [3] or [4] The first oxide semiconductor layer in the crystal, and the sputtering target contains In, Ga, Zn, Sn, and O as metal elements, and each metal element is relative to the sum of the In, Ga, Zn, and Sn The atomic ratio of satisfies

0.05≦In/(In+Ga+Zn+Sn)≦0.25

0.20≦Ga/(In+Ga+Zn+Sn)≦0.60

0.20≦Zn/(In+Ga+Zn+Sn)≦0.60

0.05≦Sn/(In+Ga+Zn+Sn)≦0.15.

According to the present invention, an oxide semiconductor thin film capable of obtaining a thin film transistor excellent in stress tolerance can be provided.

Further, according to the present invention, a thin film transistor including an oxide semiconductor layer including the oxide semiconductor thin film and capable of maintaining high field-effect mobility, and a sputtering target for forming the oxide semiconductor layer can be provided.

1: Substrate

2: Gate electrode

3: Gate insulating film

4: oxide semiconductor layer

4A: First oxide semiconductor layer

4B: Second oxide semiconductor layer

5: source/drain electrodes

6: Protective film

7: Contact hole

8: Transparent conductive film

FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.

Hereinafter, an oxide semiconductor thin film and a thin film transistor according to an embodiment of the present invention (this embodiment) will be described.

The oxide semiconductor thin film of this embodiment has a first oxide semiconductor The bulk layer and the second oxide semiconductor layer, the first oxide semiconductor layer and the second oxide semiconductor layer respectively contain In, Ga, Zn, Sn, and O as metal elements, and each metal element in the first oxide semiconductor layer The atomic ratio to the total of In, Ga, Zn, and Sn satisfies

0.05≦In/(In+Ga+Zn+Sn)≦0.25

0.20≦Ga/(In+Ga+Zn+Sn)≦0.60

0.20≦Zn/(In+Ga+Zn+Sn)≦0.60

0.05≦Sn/(In+Ga+Zn+Sn)≦0.15.

In addition, the thin film transistor of this embodiment includes a gate electrode, a gate insulating film, an oxide semiconductor layer including the oxide semiconductor thin film, source/drain electrodes, and a protective film in this order on a substrate.

In addition, in this Embodiment, the oxide which consists of In, Ga, Zn, Sn, and O may be called IZGTO. In addition, the content (atomic ratio) of In, Ga, Zn, and Sn to the total of all metal elements (In, Ga, Zn, and Sn) other than O may be referred to as In atomic ratio and Ga atomic ratio, respectively. ratio, Zn atomic ratio, and Sn atomic ratio.

<First oxide semiconductor layer in oxide semiconductor thin film>

[0.05≦In/(In+Ga+Zn+Sn)≦0.25]

In is an element which contributes to the improvement of electrical conductivity. The greater the atomic ratio of In, that is, the greater the amount of In occupied in all metal elements, the higher the conductivity of the oxide semiconductor thin film. Therefore, the oxide semiconductor thin film of the present embodiment is used as the oxidation of the thin film transistor. In the case of the material semiconductor layer (channel layer), the field effect of the thin film transistor Mobility increases.

In order to effectively exhibit the above-mentioned effect, the In atomic ratio needs to be 0.05 or more. The number of In atoms is preferably 0.08 or more. However, if the In atomic ratio is too large, there are problems such as an excessive increase in the carrier density and a decrease in the threshold voltage, so the In atomic ratio is made 0.25 or less. The number of In atoms is preferably 0.20 or less, more preferably 0.15 or less, and still more preferably 0.10 or less.

[0.20≦Ga/(In+Ga+Zn+Sn)≦0.60]

Ga is an element that contributes to reducing oxygen vacancies and controlling carrier density. The greater the atomic ratio of Ga, that is, the greater the amount of Ga in all metal elements, the more the electrical stability of the oxide semiconductor thin film is improved. In the case of the oxide semiconductor layer (channel layer), the effect of suppressing excessive generation of carriers of the thin film transistor is exhibited. In addition, Ga is also an element which inhibits etching by a hydrogen peroxide-based Cu etching solution. Therefore, the larger the Ga atomic ratio, the larger the selectivity to the hydrogen peroxide-based etchant used in the etching process of the Cu electrodes serving as the source/drain electrodes, and the less likely it is damaged.

In order to effectively exhibit the above-mentioned effect, the Ga atomic ratio needs to be 0.20 or more. The number of Ga atoms is preferably 0.25 or more. However, when the Ga atomic ratio is too large, the conductivity of the oxide semiconductor thin film is lowered, and the field-effect mobility tends to be lowered. In addition, the electrical conductivity of the sputtering target for forming the oxide semiconductor layer is lowered, and it is difficult to continuously perform DC discharge stably. Therefore, the Ga atomic ratio is set to 0.60 or less. The number of Ga atoms is preferably 0.45 or less, more preferably 0.35 or less, and still more preferably 0.30 or less.

[0.20≦Zn/(In+Ga+Zn+Sn)≦0.60]

Zn is not as sensitive to the characteristics of thin film transistors as other metal elements, but the larger the atomic ratio of Zn, that is, the more Zn occupies in all metal elements, the easier it is to amorphize. In the case of the thin film transistor of the first oxide semiconductor layer of the oxide semiconductor thin film of the embodiment, it is easily etched by an etchant of an organic acid or an inorganic acid.

In order to effectively exhibit the above-mentioned effect, the Zn atomic ratio needs to be 0.20 or more. The number of Zn atoms is preferably 0.30 or more, more preferably 0.40 or more, and still more preferably 0.50 or more. However, when the atomic ratio of Zn is too large, the solubility of the oxide semiconductor thin film with respect to the etching solution for source/drain electrodes increases, and as a result, the wet etching resistance tends to deteriorate, or the In is relatively reduced. On the other hand, the field effect mobility decreases, or the electrical stability of the oxide semiconductor thin film tends to decrease due to the relative decrease in Ga. Therefore, the Zn atomic ratio is set to 0.60 or less. The number of Zn atoms is preferably 0.55 or less.

[0.05≦Sn/(In+Ga+Zn+Sn)≦0.15]

Sn is an element that inhibits etching by an acid-based chemical solution. Therefore, the larger the atomic ratio of Sn, that is, the larger the amount of Sn occupied in all the metal elements, the larger the amount of organic compounds used for patterning of the first oxide semiconductor layer including the oxide semiconductor thin film of the present embodiment. Etching with an acid or inorganic acid etchant is more difficult. However, an oxide semiconductor to which Sn is added exhibits an increase in carrier density due to hydrogen diffusion, thereby increasing field effect mobility, and when the amount of Sn added is moderate, the reliability of the thin film transistor against optical stress is improved.

In order to effectively exert the above-mentioned effect, the atomic ratio of Sn needs to be 0.05 or more. The number of Sn atoms is preferably 0.07 or more. On the other hand, if the atomic ratio of Sn is too large, the resistance of the oxide semiconductor thin film to an etching solution of an organic acid or an inorganic acid increases more than necessary, and the processing of the oxide semiconductor thin film itself becomes difficult. In addition, there is a possibility that reliability with respect to optical stress may be lowered due to the strong influence of hydrogen diffusion. Therefore, the atomic ratio of Sn is made 0.15 or less. The number of Sn atoms is preferably 0.10 or less.

Furthermore, in the oxide semiconductor thin film, it is preferable that the atomic ratio of In to the total of In and Sn is 0.30≦In/(In+Sn)≦0.75.

If In/(In+Sn) in the relationship between the addition amounts of In and Sn is less than 0.30, the carrier density decreases, the electrical conductivity decreases, and the field effect mobility of the thin film transistor tends to decrease. On the other hand, when In/(In+Sn) in the relationship between the addition amounts of In and Sn exceeds 0.75, the reliability with respect to stress decreases.

Furthermore, In/(In+Sn) in the relationship between the addition amounts of In and Sn is more preferably 0.40 or more. In addition, In/(In+Sn) is more preferably 0.67 or less, still more preferably 0.60 or less.

Furthermore, in the oxide semiconductor thin film, it is preferable that the atomic ratio of Ga to the total of Ga and Sn is 0.75≦Ga/(Ga+Sn)≦0.99.

When the oxide semiconductor thin film of the present embodiment is used as the oxide semiconductor layer of the thin film transistor, if the Ga content in the oxide semiconductor thin film is increased, the If the amount is too low, the carrier density decreases and the electrical conductivity decreases, and the field effect mobility of the thin film transistor is likely to decrease. However, on the other hand, the wet etching resistance with respect to the hydrogen peroxide-based etching solution is improved. In addition, when the addition amount of Sn is increased, the influence of hydrogen diffusion from the protective film becomes significant, and the carrier density or conductivity tends to increase due to hydrogen diffusion.

In addition, when the addition amount of In is intended to be increased in order to cope with the decrease in field-effect mobility, which is a disadvantage of increasing the addition amount of Ga, or the decrease in the conductivity of the sputtering target, there is a possibility that the thin film transistor may be subjected to optical stress. There is a risk of a reduction in reliability, or a shift in the threshold voltage to the negative voltage side.

On the other hand, when the addition amount of Sn is increased instead of In, the decrease in field-effect mobility is suppressed, and the electrical conductivity of the sputtering target is improved. In addition, when the addition amount of Sn is increased, the threshold voltage tends to be stabilized around 0V. Therefore, when increasing the addition amount of Ga, it is considered that it is effective to increase the addition amount of Sn instead of increasing the addition amount of In.

However, the addition amount of Sn has an appropriate addition range, and when the addition range exceeds this addition range, the deterioration of the light stress tolerance of the thin film transistor may become remarkable. Therefore, a highly reliable oxide semiconductor can be obtained by adding Ga in a well-balanced manner so as to satisfy the relationship between the addition amounts of Ga and Sn.

In addition, Ga/(Ga+Sn) in the relationship between the addition amounts of Ga and Sn is more preferably 0.80 or more, and still more preferably 0.85 or more. In addition, Ga/(Ga+Sn) is more preferably 0.95 or less, still more preferably 0.90 or less.

In addition, the thickness of the first oxide semiconductor layer is not particularly limited, but if Since the selectivity at the time of the etching process of a source/drain electrode is excellent in 10 nm or more, it is preferable, and it is more preferable that it is 15 nm or more. In addition, in terms of maintaining high field-effect mobility, for example, it is preferably 40 nm or less.

<Thin Film Transistor>

Next, the thin film transistor of the present embodiment will be described in further detail.

Hereinafter, embodiments of the thin film transistor of the present invention will be described in more detail with reference to the drawings. However, these are merely examples of preferred embodiments, and the present invention is not limited to these embodiments.

As shown in FIG. 1 , a gate electrode 2 and a gate insulating film 3 are formed on a substrate 1 , and a (first) oxide semiconductor layer 4 is formed thereon. A source/drain electrode 5 is formed on the (first) oxide semiconductor layer 4, a protective film (insulating film) 6 is formed thereon, and the transparent conductive film 8 is connected to the source through a contact hole 7. The pole/drain electrode 5 is electrically connected. Furthermore, since the (first) oxide semiconductor layer 4 includes the oxide semiconductor thin film, the atomic number of the metal element in the (first) oxide semiconductor layer 4 is higher than that in the oxide semiconductor thin film of the present embodiment. Descriptive.

The method of forming the gate electrode 2 and the gate insulating film 3 on the substrate 1 is not particularly limited, and a commonly used method can be used. In addition, the type of metal forming the gate electrode 2 and the gate insulating film 3 is not particularly limited, and a general-purpose metal can be used. For example, in the formation of the gate electrode 2 , metals such as Al and Cu with low resistivity, high melting point metals such as Mo, Cr, Ti and the like with high heat resistance, or alloys thereof can be preferably used.

Furthermore, the gate electrode 2 may be a build-up type including multiple layers. In addition, in the formation of the gate insulating film 3, _SiOx , _SiNx , etc. are typically used. In addition, oxides such as Al ₂ O ₃ and Y ₂ O ₃ or those formed by laminating them may also be used.

In addition, the gate insulating film 3 may be, for example, a build-up type gate insulating film in which a SiO _x film and a SiN _x film are continuously formed. Compared with the _SiOx film, the _SiNx film has a faster film formation rate and a higher dielectric constant, and therefore, the total film thickness can be made thinner if it is such a build-up type gate insulating film.

Next, the (first) oxide semiconductor layer 4 having the above-described composition is formed. The (first) oxide semiconductor layer 4 can be formed by, for example, a direct current (DC) sputtering method or a radio frequency (RF) sputtering method, in which the DC sputtering method or the RF sputtering method A sputtering target having the same composition as the (first) oxide semiconductor layer 4 to be formed was used. Alternatively, a film may be formed by a co-sputtering method using a plurality of sputtering targets.

Patterning is performed after wet etching the (first) oxide semiconductor layer 4 with an organic acid such as oxalic acid or an inorganic acid. In order to improve the film quality of the (first) oxide semiconductor layer 4, it is preferable to perform heat treatment (pre-anneal) immediately after patterning. As a result, the on-current and field-effect mobility, which are characteristics of the transistor, are increased, thereby improving the performance of the thin film transistor. As pre-annealing conditions, temperature: about 250 degreeC - 400 degreeC, time: about 10 minutes - 1 hour etc. are mentioned, for example.

The source/drain electrodes 5 are formed after pre-annealing. In the present embodiment, as shown in FIG. 1 , the source/drain electrodes 5 are directly bonded to the (first) oxide semiconductor layer 4 except for the channel region.

Furthermore, the type of the source/drain electrodes 5 is not particularly limited, and general-purpose electrodes can be used. source/drain electrodes. For example, metals or alloys such as Al, Mo, Cu, and Ti can be used similarly to the gate electrode 2 . Among these, Cu or a Cu alloy is preferably used because it is advantageous in that the resistivity is low.

As a method for forming the source/drain electrodes 5, for example, after forming a metal thin film by magnetron sputtering, patterning can be performed by photolithography, and hydrogen peroxide can be used for patterning. Electrodes are formed by wet etching with an etchant of phosphoric acid, nitric acid and acetic acid.

Next, a protective film (insulating film) 6 is formed on the (first) oxide semiconductor layer 4 by a chemical vapor deposition (Chemical Vapor Deposition, CVD) method or the like. Furthermore, the surface of the (first) oxide semiconductor layer 4 is easily turned on due to plasma damage by CVD (presumably the reason is that oxygen vacancies generated on the surface of the oxide semiconductor become electron donors) Therefore, N ₂ O plasma irradiation can also be performed before the film formation of the protective film 6 . The irradiation conditions of the N ₂ O plasma may be those described in the following documents.

J. Park et al., Appl. Phys. Lett., 93, 053505 (2008)

Here, in this embodiment, the protective film 6 contains SiO _x . The formation of SiO _x is carried out in an oxidizing environment, and therefore, the source/drain electrodes 5 including Cu or Cu alloy may be oxidized. Therefore, a Cu alloy with high oxidation resistance can also be used for the source/drain electrodes 5, or a cap layer (such as Mo or Mo) formed of a high melting point metal can be laminated on the source/drain electrodes 5. Alloy film, etc.) to prevent oxidation, or thinly form a resin layer or SiN _x before forming the SiO _x film. In addition, in order to prevent the influence of moisture absorption or the like from the outside, a resin layer or a _SiNx film may be further stacked on the protective film 6 containing _SiOx .

Next, the contact hole 7 is formed by a commonly used method, and further, an indium tin oxide film (ITO film) or the like is formed, thereby forming a transparent conductive electrically connected to the source/drain electrodes 5 through the contact hole 7 Membrane 8. The type of the transparent conductive film 8 is not particularly limited, and a commonly used transparent conductive film can be used.

Next, a preferred embodiment of the thin film transistor of the present invention will be described with reference to FIG. 2 . As shown in FIG. 2, in the thin film transistor of the present embodiment, a gate electrode 2, a gate insulating film 3, a second oxide semiconductor layer (channel forming layer) 4B, a first oxide semiconductor layer 4B, a gate electrode 2, a gate insulating film 3, a second oxide semiconductor layer (channel forming layer) 4B, a first The oxide semiconductor layer (back channel layer) 4A, the source/drain electrodes 5 , the protective film 6 , and the transparent conductive film 8 are electrically connected to the source/drain electrodes 5 through the contact holes 7 . In addition, the first oxide semiconductor layer 4A in the thin film transistor of this embodiment is the same as the oxide semiconductor layer 4 in the thin film transistor of the embodiment shown in FIG. 1, and an oxide semiconductor having the above-mentioned composition is used. Floor.

In the second oxide semiconductor layer 4B, IGZTO is used in the same manner as in the first oxide semiconductor layer 4A, but the metal element ratio may be different from the IGZTO used in the first oxide semiconductor layer 4A. More specifically, when the atomic ratios of In and Ga to the total of In, Ga, Zn, and Sn in the first oxide semiconductor layer 4A are respectively [In1] and [Ga1], the second oxide When the atomic ratio of In and Ga to the total of In, Ga, Zn, and Sn in the semiconductor layer 4B is set to [In2] and [Ga2], respectively, it is preferable to satisfy [In1]≦[In2], [Ga1]≧[Ga2].

Here, as described above, the first oxide semiconductor layer 4A directly exposed to the etching solution for source/drain electrode processing is excellent in the wet etching resistance, so that the resistance to oxide in the source/drain electrode processing is improved. Since there is little damage on the surface of the semiconductor layer, it is easy to obtain good thin film transistor characteristics. In addition, the reliability of the first oxide semiconductor layer 4A against optical stress is also high.

On the other hand, the second oxide semiconductor layer 4B satisfying the relationship can obtain high field-effect mobility, and by forming the second oxide semiconductor layer 4B under the first oxide semiconductor layer 4A, the The field effect mobility of the entire oxide semiconductor layer is maintained high, and it has excellent wet etching resistance.

Furthermore, in terms of realizing higher field-effect mobility as the entire oxide semiconductor layer, it is preferable that each metal element in the second oxide semiconductor layer 4B is relative to the above-mentioned In, Ga, Zn, and Sn. The total atomic ratio of satisfies

0.20≦In/(In+Ga+Zn+Sn)≦0.60

0.05≦Ga/(In+Ga+Zn+Sn)≦0.25

0.15≦Zn/(In+Ga+Zn+Sn)≦0.60

0.01≦Sn/(In+Ga+Zn+Sn)≦0.20.

The first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B have different ratios of the respective metal elements, but are the same in that they contain In, Ga, Zn, and Sn as the metal elements constituting the respective layers. Generally speaking, if the oxide semiconductor layer is formed into a laminated structure, the amount of side etching between the first layer and the second layer may be different when the wiring pattern is formed due to the difference in the type or content of the metal. Problems such as being unable to pattern into a desired shape. However, in this embodiment, even if the oxide semiconductor layer has a laminated structure, the etching rates of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B can be set to the same level. As a result, it is soluble with respect to the wet etching solution for oxide processing, and the said laminated structure can be etched integrally.

In addition, by setting the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B to have the same composition system, the disorder of the composition at the build-up interface is reduced, and the abrupt change in the depth distribution of each metal element is prevented. It is possible to prevent peeling or segregation of the film, abnormal grain growth, and the like when subjected to a thermal history in the production process.

<Sputtering target>

This embodiment also relates to a sputtering target for forming the first oxide semiconductor layer 4A in the thin film transistor. As a sputtering target, it is preferable to use a sputtering target containing the above-mentioned elements and having the same composition as that of the desired oxide semiconductor layer, whereby an oxide semiconductor layer having a desired composition can be formed with little difference in composition.

Specifically, the sputtering target of the present embodiment contains In, Ga, Zn, Sn, and O as metal elements, and the atomic ratio of each metal element to the sum of In, Ga, Zn, and Sn satisfies

0.05≦In/(In+Ga+Zn+Sn)≦0.25

0.20≦Ga/(In+Ga+Zn+Sn)≦0.60

0.20≦Zn/(In+Ga+Zn+Sn)≦0.60

0.05≦Sn/(In+Ga+Zn+Sn)≦0.15.

In addition, the preferable numerical range of In, Ga, Zn, and Sn in the sputtering target of this embodiment, and the reason for limitation are the same as those demonstrated for the said oxide semiconductor thin film.

[Example]

Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples, but the present invention is not limited to these Examples.

[Example 1 to Example 4]

The thin film transistor having the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B is fabricated by the following procedure.

As shown in FIG. 2 , first, a Mo thin film (film thickness 100 nm) serving as a gate electrode 2 is formed on a glass substrate 1 (Eagle XG manufactured by Corning, 100 nm in diameter×0.7 mm in thickness) , and patterned into the shape of the gate electrode 2 by photolithography. Next, an SiO _x film (film thickness: 250 nm) was formed as the gate insulating film 3 . The gate electrode 2 is formed into a film by a sputtering method using a Mo sputtering target. In addition, the gate insulating film 3 is formed by the plasma CVD method. The film-forming conditions of the gate electrode 2 and the gate insulating film 3 are shown below.

(Film-forming conditions of gate electrode)

Film forming temperature: room temperature

Film forming power: 300W

Carrier gas: Ar

Gas pressure: 2mTorr

(Film formation conditions of gate insulating film)

Carrier gas: mixed gas of SiH ₄ and N ₂ O

Film forming power: 300W

Film forming temperature: 320℃

Next, an oxide semiconductor layer having a composition of In:Ga:Zn:Sn=4:1:4:1 was formed on the gate insulating film 3 as the second oxide semiconductor layer 4B (thickness: 40 nm). Then, oxide semiconductor layers of various compositions described in the following Table 1 were formed on 4B as first oxide semiconductor layers 4A (film thickness: 40 nm). The first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are both formed by sputtering. The apparatus used in the sputtering was "CS-200" manufactured by ULVAC Co., Ltd., and the sputtering conditions for forming the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B were as follows .

(Sputtering conditions for forming the first oxide semiconductor layer and the second oxide semiconductor layer)

Substrate temperature: room temperature

Gas pressure: 1mTorr

Oxygen partial pressure: 100×O ₂ /(Ar+O ₂ )=4%

After the oxide semiconductor layer 4A and the oxide semiconductor layer 4B containing IGZTO are formed in this manner, patterning is performed by photolithography and wet etching. As the wet etching solution, "ITO-07N" manufactured by Kanto Chemical Co., Ltd., which is an etching solution containing oxalic acid, was used, and the solution temperature was set to room temperature.

As described above, after patterning the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B, in order to improve the The film quality of the second oxide semiconductor layer 4B is pre-annealed. The pre-annealing treatment was performed at 400° C. for 1 hour in an atmospheric environment.

Next, source/drain electrodes 5 are formed. Specifically, a MoNb film with a film thickness of 35 nm and a Cu film with a film thickness of 300 nm were successively formed and patterned by photolithography and wet etching with a hydrogen peroxide-based chemical solution to form a source electrode with a layered structure. /Drain electrode 5. At the time of patterning, a hydrogen peroxide aqueous (H ₂ O ₂ ) inorganic etching solution was used. By patterning the source/drain electrodes 5 , the channel length of the TFT was set to 10 μm, and the channel width was set to 200 μm.

After the source/drain electrodes 5 were formed in the above-described manner, a _SiOx film was formed with a film thickness of 200 nm by a plasma CVD method using "PD-220NL" manufactured by SAMCO, and further with a film thickness of 150 nm. The _SiNx film is formed, whereby the protective film 6 including the _SiOx film and the _SiNx film is formed. The film forming conditions of the SiO _x film and the SiN _x film are shown below.

(Film formation conditions of SiO _x film)

Carrier gas: mixed gas of SiH ₄ and N ₂ O

Film forming power: 100W

Film forming temperature: 230℃

(Film formation conditions of SiN _x film)

Carrier gas: mixed gas of NH ₃ , N ₂ and N ₂ O

Film forming power: 100W

Film forming temperature: 150℃

Furthermore, with respect to the protective film 6, an annealing treatment was performed at 300° C. for 1 hour in the air, and a photocurable resin was formed into a film with a thickness of 600 nm using a spin coater. On the protective film 6 , a through hole pattern is formed by photolithography, and a contact hole 7 is formed in the protective film 6 by a reactive ion etching (Reactive Ion Etching, RIE) plasma etching device.

Finally, a post-anneal treatment was performed at 250° C. for 30 minutes under a nitrogen atmosphere. The thin film transistor is manufactured by the above procedure.

[Comparative Example 1]

A thin film transistor of Comparative Example 1 was produced in the same manner as in the Examples except that an oxide semiconductor thin film having a composition of In:Ga:Zn=1:2:1 without Sn was used as the oxide semiconductor layer 4A (thickness: 40 nm). .

[Comparative Example 2]

A thin film transistor of Comparative Example 2 was produced in the same manner as in the Examples except that an oxide semiconductor thin film having a composition of In:Ga:Zn=1:3:3 without Sn was used as the oxide semiconductor layer 4A (film thickness 40 nm). .

[Comparative Example 3]

A thin film transistor of Comparative Example 3 was produced in the same manner as in the Example except that the oxide semiconductor layer 4A was not formed, that is, only the second oxide semiconductor layer 4B was formed.

About each thin-film transistor obtained in this way, the thin-film transistor characteristic and stress tolerance were evaluated under the following conditions.

[Measurement of transistor characteristics]

Transistor characteristics (drain current-gate voltage characteristics, I _d -V _g characteristics) were measured using a semiconductor parameter analyzer "HP4156C" manufactured by Agilent Technologies.

The detailed measurement conditions are as follows.

Source voltage: 0V

Drain voltage: 10V

Gate voltage: -30V~30V (measurement interval: 0.25V)

Substrate temperature: room temperature

<Field Effect Mobility>

The field-effect mobility (μ _FE ) is derived in the saturation region where V _g >V _d −V _th according to the TFT characteristics. In the saturation region, V _g is the gate voltage, V _d is the drain voltage, I _d is the drain current, L and W are the channel length and channel width of the TFT element, respectively, and C _i Let it be the electrostatic capacitance of the gate insulating film, and let _μFE be the field-effect mobility. μ _FE is derived from the following formula.

In this embodiment, the field-effect mobility μ _FE is derived from a slope that satisfies the drain current-gate voltage characteristic ( _Id - _Vg characteristic) in the vicinity of the gate voltage of the linear region. In the present example and the comparative example, those having a field effect mobility of 20.0 cm ² /Vs or more were determined to be high field effect mobility.

<Threshold Voltage>

The threshold voltage (V _th ) is the value of the gate voltage when the transistor transitions from an off state (a low drain current state) to an on state (a high drain current state). In this embodiment, the gate voltage when the drain current of the thin film transistor becomes 10 ⁻⁹ A is defined as the threshold voltage, and the threshold voltage (V) of each thin film transistor is measured.

<S value (sub-threshold swing)>

The S value is the minimum value of the amount of change in the gate voltage required to increase the drain current by one bit, and it is possible to evaluate the scale of the switch-off of the TFT by measuring the S value. In this example, the S value was determined to be 0.5 (V/decade) or less as a good characteristic.

[stress tolerance]

In this example, a stress application test in which a positive bias voltage was continuously applied to the gate electrode was performed for 2 hours, and the fluctuation value of the threshold voltage (V _th ) before and after the stress application test (threshold voltage shift amount: Δ V _th ) is used as an index of stress tolerance in TFT characteristics.

The conditions of the stress application test are as follows.

Gate voltage: +20V

Source/Drain Voltage: 0.1V

Substrate temperature: 60℃

Stress application time: 2 hours

In the present Examples and Comparative Examples, it was judged that the stress tolerance was excellent when the shift amount (ΔV _th ) of the threshold voltage (V _th ) before and after the stress application test was 3.0 V or less.

The compositions of the first oxide semiconductor layers of Examples 1 to 4 are shown in Table 1 below, and the evaluations of Examples 1 to 4 and Comparative Examples 1 to 3 are compared. The valence results are shown in Table 2 below.

As shown in Tables 1 and 2, the composition of each metal element in the oxide semiconductor layer used in the thin film transistors of the respective Examples was within the range specified in the present invention, and as a result, the field-effect mobility satisfies 20.0 cm ² /Vs or more, the S value is 0.5 (V/decade) or less, and the shift amount (ΔV _th ) of the threshold voltage (V _th ) before and after the stress application test is satisfied to be 3.0 V or less, thereby realizing a high field Coexistence of effect mobility, small S value, and excellent stress tolerance.

In Comparative Example 1 and Comparative Example 2, the atomic ratio of In, Ga, and Zn is this Within the scope of the invention, since Sn is not contained, the stress tolerance or the evaluation result of the S value is poor.

In Comparative Example 3, in which the oxide semiconductor layer 4A was not formed and only the second oxide semiconductor layer 4B was formed, although the field effect mobility was excellent, the second oxide semiconductor layer was exposed to the etching solution, so the second oxide semiconductor layer was exposed to the etchant. loss and the S value becomes a high value.

Various embodiments have been described above with reference to the drawings, but it goes without saying that the present invention is not limited to the examples. It is clear to those skilled in the art that various modifications and amendments can be conceived within the scope of the claims, and it should be understood that these also belong to the technical scope of the present invention. In addition, each component of the said embodiment can be combined arbitrarily in the range which does not deviate from the summary of invention.

In addition, this application is based on the Japanese patent application (Japanese Patent Application No. 2019-023463) for which it applied on February 13, 2019, and the content is used here as a reference.

Claims (6)

An oxide semiconductor thin film having a first oxide semiconductor layer and a second oxide semiconductor layer, wherein the first oxide semiconductor layer and the second oxide semiconductor layer respectively contain In, Ga, and Zn as metal elements and Sn, and O, and the atomic ratio of each metal element in the first oxide semiconductor layer to the sum of In, Ga, Zn, and Sn satisfies 0.05≦In/(In+Ga+Zn+Sn) ≦0.25 0.20≦Ga/(In+Ga+Zn+Sn)≦0.60 0.20≦Zn/(In+Ga+Zn+Sn)≦0.60 0.07≦Sn/(In+Ga+Zn+Sn)≦0.15, the The atomic ratio of each metal element in the second oxide semiconductor layer to the sum of In, Ga, Zn, and Sn satisfies 0.20≦In/(In+Ga+Zn+Sn)≦0.60 0.05≦Ga/(In +Ga+Zn+Sn)≦0.25 0.15≦Zn/(In+Ga+Zn+Sn)≦0.60 0.01≦Sn/(In+Ga+Zn+Sn)≦0.20, in the first oxide semiconductor layer , the atomic ratio of In to the total of In and Sn satisfies 0.30≦In/(In+Sn)≦(101/152). An oxide semiconductor thin film having a first oxide semiconductor layer and a second oxide semiconductor layer, The first oxide semiconductor layer and the second oxide semiconductor layer respectively contain In, Ga, Zn, Sn, and O as metal elements, and each metal element in the first oxide semiconductor layer is relative to the metal elements. The atomic ratio of the total of In, Ga, Zn and Sn satisfies 0.05≦In/(In+Ga+Zn+Sn)≦0.25 0.20≦Ga/(In+Ga+Zn+Sn)≦0.60 0.20≦Zn/( In+Ga+Zn+Sn)≦0.60 0.07≦Sn/(In+Ga+Zn+Sn)≦0.15, each metal element in the second oxide semiconductor layer is relative to the In, Ga, Zn and Sn The total atomic ratio of 0.20≦In/(In+Ga+Zn+Sn)≦0.60 0.05≦Ga/(In+Ga+Zn+Sn)≦0.25 0.15≦Zn/(In+Ga+Zn+Sn) ≦0.60 0.01≦Sn/(In+Ga+Zn+Sn)≦0.20, in the first oxide semiconductor layer, the atomic ratio of In to the total of In and Sn satisfies 0.30≦In/(In+Sn )≦0.60. A thin film transistor comprising a gate electrode, a gate insulating film, an oxide semiconductor layer comprising the oxide semiconductor thin film according to claim 1 or claim 2, source/drain electrodes and protective film. The thin film transistor of claim 3, wherein the source/drain electrodes comprise Cu or a Cu alloy. A sputtering target for forming the first oxide semiconductor layer in the thin film transistor as claimed in claim 3 or claim 4, wherein the sputtering target contains In, Ga, Zn as metal elements and Sn, and O, the atomic ratio of each metal element to the total of In, Ga, Zn and Sn satisfies 0.05≦In/(In+Ga+Zn+Sn)≦0.25 0.20≦Ga/(In+Ga +Zn+Sn)≦0.60 0.20≦Zn/(In+Ga+Zn+Sn)≦0.60 0.07≦Sn/(In+Ga+Zn+Sn)≦0.15, the atomic ratio of In to the total of In and Sn Satisfy 0.30≦In/(In+Sn)≦(101/152). A sputtering target for forming the first oxide semiconductor layer in the thin film transistor as claimed in claim 3 or claim 4, wherein the sputtering target contains In, Ga, Zn as metal elements and Sn, and O, the atomic ratio of each metal element to the total of In, Ga, Zn and Sn satisfies 0.05≦In/(In+Ga+Zn+Sn)≦0.25 0.20≦Ga/(In+Ga +Zn+Sn)≦0.60 0.20≦Zn/(In+Ga+Zn+Sn)≦0.60 0.07≦Sn/(In+Ga+Zn+Sn)≦0.15, the atomic ratio of In to the total of In and Sn Satisfy 0.30≦In/(In+Sn)≦0.60.

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