WO2014172960A1 - Gate driving apparatus and display apparatus - Google Patents

Abstract

A gate driving apparatus comprises shift register units (13). One end of each row of gate lines (14) is connected to one shift register unit (13). The other end of the gate lines (14) is connected to an auxiliary driving circuit (15). For one row of gate lines (14) connected to the auxiliary driving circuit (15), the auxiliary driving circuit (15) compensates, by using a control signal, the gate lines (14) by means of the control of other gate lines (14) connected to the auxiliary driving circuit (15). The display apparatus comprises the gate driving apparatus. The present invention can solve the problems that the existing bilateral gate driving circuit occupies relatively large space and the poor effect of a narrow side frame of a display apparatus due to the relatively large space occupancy.

Description

 Gate drive device and display device

Technical field

 The present invention belongs to the field of display technologies, and in particular, to a gate driving device and a display device including the same. Background technique

 Thin Film Transistor Liquid Crystal Display (TFT-LCD) is a common liquid crystal display product. In TFT-LCD, each pixel has a thin film transistor, and the thin film transistor of each pixel needs and corresponds. The gate drive circuit (ie, the shift register unit) is connected to control the change of the transmittance of the liquid crystal in the pixel to achieve the purpose of controlling the color change of the pixel. The gate driver on Array (GOA) circuit technology is a gate drive circuit technology commonly used in the field of TFT-LCD technology. The GOA circuit is implemented by a plurality of cascaded shift register units. The pole drive circuit is directly fabricated on the array substrate instead of the external driver chip (Driver IC).

Each shift register unit corresponds to a row of pixels of the TFT-LCD (ie, corresponding to one row of gate lines), and is used to provide a gate driving voltage to the thin film transistors of the corresponding row of pixels, and has a plurality of rows of pixels in the entire TFT-LCD, that is, There are a plurality of corresponding shift register units. During the operation of the TFT-LCD, it is necessary to sequentially supply a gate driving voltage to each row of pixels, so that the shift register unit corresponding to each row of pixels needs to start working in sequence. FIG. 1 is a schematic diagram showing the structure of a shift register unit circuit corresponding to a row of pixels. As can be seen from FIG. 1, the shift register unit includes a plurality of thin film transistors, capacitors, and shift register units and clock control lines. Connected (only one is drawn in Figure 1, usually the clock control line can also be 2 sets of 4 lines, 3 sets of 6 lines or 4 sets of 8 lines, etc.), the working process is roughly as follows: The receiving end receives the input signal INPUT (ie, the upper The gate drive signal of the first stage shift register unit and the clock control signal, under the action of each thin film transistor and capacitor, finally output the signal OUTPUT from the output terminal, that is, output the gate drive signal of the current stage, and drive the gate at the same time. The signal is used as the input signal INPUT of the shift register unit of the next stage; at the same time, the reset terminal receives the reset signal RESET, and completes the reset task for the gate drive signal of the current stage, and sequentially supplies the gate drive voltage to each row of pixels in this manner. Of course, it should be understood that FIG. 1 is only an example of a shift register unit circuit. The specific structure of the shift register unit circuit is various as long as it can implement the above functions.

 In liquid crystal displays, the gate drive circuit usually adopts a bilateral design. The bilateral drive design is the same two sets of gate drive circuits at both ends of the gate line for shifting and transmitting the gate drive signal. Especially in the large-sized panel, because of its large size, long wiring length, high resolution, it will bring a large load, resulting in signal delay (RC delay), which will have many adverse effects on pixel charging, such as insufficient charging. , poor picture uniformity, etc. For this reason, the bilateral driving method is used to increase the driving capability of the gate driving signal and to reduce the influence of the delay.

 The inventors have found that at least the following problems exist in the prior art: The design of the gate signal driving capability is increased by adopting a bilateral driving method, so that the gate driving circuit occupies a large space of the display panel, and the area of the display area is crowded, which is reduced. The design space around the display device makes it difficult to further reduce the size of the frame, which affects the actual narrow frame effect. Summary of the invention

 The technical problem to be solved by the present invention includes providing a gate drive circuit with a single gate drive circuit and a small footprint for the problem that the existing bilateral gate drive circuit occupies a large space.

 In order to solve the above technical problem, in accordance with an embodiment of the present invention, a gate driving apparatus is provided. The gate driving apparatus includes: a plurality of shift register units respectively connected to one end of each row of gate lines; and an auxiliary driving circuit, connected To the other end of the gate line, a row line is connected to the gate line of the auxiliary driving circuit, and the auxiliary driving circuit compensates the row gate line with a control signal by control of other row gate lines connected thereto.

 Optionally, the control signal is a clock control signal of the row gate line.

 Specifically, for each row of the gate lines, a control signal whose one end is connected through each shift register unit is completely coincident with a clock control signal that is connected to the other end through the auxiliary driving circuit.

 Optionally, the other row gate lines connected to the auxiliary driving circuit are gate lines whose operating level at least partially overlaps the operating level of the row gate lines.

Wherein, the working level means that the potential of the row gate line is a high level, so that the line The gate line is in a conducting state. That is, in the row-on-line conduction phase, the potential of the other row gate lines is also at least partially high level (or other row gate lines and the row gate lines are simultaneously turned on at least part of the time), The other gate lines are gate lines connected to the auxiliary drive circuit.

 Optionally, the manner in which the other row gate lines control the auxiliary driving circuit comprises: when the signal in the row gate line is a rising edge, the auxiliary driving circuit is controlled by other row gate lines at a high level ;

 When the signal in the row gate line is a falling edge, the auxiliary driving circuit is thus controlled by other row gate lines at a high level.

 Optionally, the auxiliary driving circuit connected to the row gate line includes a first switching unit and a second switching unit, wherein the first switching unit and the second switching unit are respectively connected by a previous row of gate lines and a next row Grid line control.

 Wherein, the "previous row" and "next row" gate lines are not necessarily adjacent to each other, but are directed adjacent to each other, that is, "the upper row of gate lines" means that during the gate signal driving process, The gate line that is turned on before the row gate line (or the gate line is turned on after the previous row of gate lines is turned on), and the "lower row gate line" refers to the gate signal driving process. When the row gate line is turned on, the next row of gate lines to be turned on (or the gate line is turned on after the next row of gate lines is turned on).

 Optionally, the switching unit is an N-type thin film transistor.

 Optionally, a gate of the first thin film transistor is connected to the gate line of the upper row, a drain of the first thin film transistor is connected to the gate line, and a source and a source of the first thin film transistor a clock control signal connection of the gate line;

 a gate of the second thin film transistor is connected to the gate line of the next row, a drain of the second thin film transistor is connected to the gate line, a source of the second thin film transistor and the gate line The clock control signal is connected.

 Optionally, each of the shift register units is located at the same end of each of the gate lines, and an auxiliary driving circuit is disposed at the other end of each of the gate lines.

 Further, the auxiliary driving circuit is disposed on the substrate.

Since the gate driving device of the embodiment of the present invention has an auxiliary driving circuit capable of compensating the gate driving signals for the respective gate lines, the delay of the gate driving signals is made small. At the same time, because the structure of the auxiliary driving circuit is single, the footprint of the gate driving circuit is greatly reduced. That is, the size of the gate driving circuit is reduced on the basis of ensuring that the characteristics of the existing gate signal are not changed.

 The technical problem to be solved by the present invention further includes providing a display device having a narrow frame and a large effective display area in view of the problem that the narrow side frame of the display device is poor in the prior art.

 In order to solve the above technical problem, according to an embodiment of the present invention, a display device is provided, including:

 The above gate drive device.

 Since the display device of the present invention has the above-mentioned gate driving device, the gate driving circuit has a single tube and a small space, thereby achieving the purpose of reducing the size of the frame, so that the design of the narrow frame can be realized, and the effective display of the display device is improved. area. DRAWINGS

 1 is a schematic structural view of a conventional array substrate row driving unit;

 2 is a schematic structural view of a gate driving device according to Embodiment 2 of the present invention;

 3 is a timing chart of a driving process of the gate driving device according to Embodiment 2 of the present invention; FIG. 4 is a driving waveform of the gate driving device and the single-side driving gate driving device according to Embodiment 2 of the present invention; Graph;

 The reference numerals are as follows: 1. The substrate; 2. The clock control signal line; 3. The driving waveform curve when the gate driving device of Embodiment 2 is driven; 4. The driving waveform curve when driving by one side; 12. The display area; 13. A shift register unit; 14. a gate line; 15. an auxiliary driving circuit; 151, a first thin film transistor; 152, a second thin film transistor. detailed description

 The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Example 1

The embodiment provides a gate driving device, including a shift register unit, one end of each row of gate lines is connected to one of the shift register units, and the other end of each row of gate lines is connected to an auxiliary driving circuit, and one row is connected a gate line of the auxiliary driving circuit, the auxiliary driving circuit passes The control of the other gate lines connected thereto is compensated by the control signal.

 Wherein, the control signal mainly charges the gate line of the current line at the working voltage on time, and simultaneously charges the working voltage off time of the gate line of the current line. Of course, in the middle time period, the control signal can also be applied to the line of the line. Charge maintenance is performed to reduce the signal delay across the gate lines. The control signal can directly utilize the clock control signal of the row gate line or the external control signal, which is not limited herein.

 Since the gate driving device of the embodiment includes an auxiliary driving circuit connected to the gate line, the auxiliary driving circuit controls the gate of the row gate line by a control signal through control of other gate lines connected thereto The drive signal is compensated to reduce the negative effects of the delay. At the same time, because the auxiliary driving circuit structure is simple, the occupied space is small, and the double-gate driving circuit in the prior art is improved on the basis of not changing the characteristics of the existing gate signal, and the gate driving circuit is reduced. The size of the frame is reduced, so that the design of the narrow bezel is achieved, and the effective display area of the display device is improved. Example 2:

 The embodiment provides a gate driving device. As shown in FIG. 2, the system includes: a substrate 1, a plurality of rows of gate lines 14 disposed on the substrate 1, a plurality of shift register units 13, and an auxiliary driving circuit 15, The plurality of clock control signal lines 2 of the plurality of clock control signals CK1, CK2, CK3, and CK4 are respectively transmitted (that is, the two sets of four lines are taken as an example in the present embodiment).

 Each of the shift register units 13 in this embodiment is directly fabricated on the substrate 1 by an array process.

 As shown in FIG. 2, the input terminal of each shift register unit 13 is connected to a corresponding clock control signal line 2, and its output terminal is connected to one end of the corresponding gate line 14, and the other end of the gate line 14 and the auxiliary driving circuit 15 are connected. connection.

 Optionally, the other end of each row of gate lines 14 is connected to the clock control signal 2 through two branches of the auxiliary driving circuit 15 (for example, for the Nth row gate line G_N, the shift register unit 13GOA_N input clock control connected to the left end thereof) The signal CK2 is connected to the clock control signal CK2 via the two branches at its right end.

Optionally, each shift register unit 13 is located at the same end of each gate line 14 (ie, the left side of the display area 12 in FIG. 2), and the auxiliary driving circuit 15 is disposed at the other end of each gate line 14 (ie, The right side of the area 12 is shown in Fig. 2). Such a design makes the manufacturing process single, and at the same time, since each shift register unit 13 occupies the same space, the branches of the auxiliary driving circuit 15 occupy the same space, so this design can reasonably arrange the space on the substrate.

 Further, the auxiliary driving circuit 15 of the embodiment is disposed on the substrate 1 because each of the shift register units 13 includes a plurality of thin film transistors, and the auxiliary driving circuit 15 may also include thin film transistors 151 and 152, and the film In the transistor display, a large number of thin film transistors for driving are also provided on the substrate 1 (array substrate). Such a design allows a plurality of thin film transistors to be formed simultaneously, so that the manufacturing process is simple and easy to implement.

 Alternatively, the other gate lines 14 connected to the auxiliary driving circuit 15 are gate lines 14 whose operating levels at least partially overlap the operating levels of the row gate lines 14.

 Specifically, in the present embodiment, as shown in FIG. 3, taking the Nth gate line G_N as an example, when the potential is high, that is, in the time period t2, t3, the Nth gate line G_N is On state. It is not difficult to find that, in this stage, the potentials of the N-1th gate line G_N-1 and the N+1th gate line G_N+1 are partially high level (t2 time period, the first N-1) The row gate line G_N-1 is a high level, and in the period of t3, the N+1th gate line G_N+1 is a high level), then the other gate lines 14 connected to the auxiliary driving circuit 15 are respectively N- 1 row gate line G_N-1 and N+1 row gate line G_N+1.

 Optionally, when the signal in the Nth row gate line G_N is a rising edge, the auxiliary driving circuit 15 is controlled by the gate line of the high level (ie, the N-1th gate line G_N-1). When the signal in the N row gate line G_N is a falling edge, the auxiliary driving circuit 15 is thus controlled by the gate line of the high level (i.e., the N+1th gate line G_N+1).

 Optionally, the auxiliary driving circuit 15 connected to the row gate line 14 includes a first switching unit and a second switching unit, which are a switching unit 151 and a switching unit 152, respectively. Further optionally, the switching units 151, 152 are N-type thin film transistors.

Optionally, in the embodiment, two thin film transistors in the auxiliary driving circuit 15 corresponding to one row of gate lines 14 are respectively a first thin film transistor 151 and a second thin film transistor 152 as shown in FIG. 2 . Taking the Nth row gate line G_N as an example, the auxiliary driving circuit 15 includes a first thin film transistor 151 and a second thin film transistor 152; the gate of the first thin film transistor 151 and the upper row of gate lines (ie, the N-1th gate) The line G_N-1 is connected, the drain is connected to the Nth row gate line G_N, and the source is connected to the clock control signal CK2 (ie, the shift register unit connected to the gate line G_N− terminal) The clock control signal CK2 of the GOA_N is connected; the gate of the second thin film transistor 152 is connected to the gate line of the next row (ie, the N+1th gate line G_N+1), and the drain is connected to the Nth gate line G_N, the source It is connected to the clock control signal CK2 (i.e., the clock control signal CK2 of the shift register unit GOA_N connected to the gate line G_N-).

 Specifically, the two thin film transistors 151 and 152 are respectively controlled by the upper row gate line G_N-1 of the Nth row gate line G_N and the next row gate line G_N+1, and the upper row gate line G_N of the Nth row gate line G_N 1 and the next row of gate lines G_N+1 are not necessarily adjacent in position, but are directed adjacent to each other. Because the N-1th gate line G_N-1 is a gate line that is turned on before the Nth row gate line G_N (or the Nth row gate line G_N-1 is turned on, the Nth row gate line G_N is turned on) Therefore, the N-1th gate line G_N-1 is the "previous row gate line" of the Nth gate line G_N, so the first thin film transistor 151 is controlled by the N-1th gate line G_N-1, The specific control method is to connect the gate of the first thin film transistor 151 to the N-1th gate line G_N-1; and because the N+1th gate line G_N+1 is turned on when the Nth gate line G_N is turned on, The gate line to be turned on (or the N+1th gate line G_N+1 is turned on after the Nth gate line G_N is turned on), so the N+1th gate line G_N+1 is the Nth line The gate line G_N is "the next row of gate lines", so the second thin film transistor 152 is controlled by the gate line G_N+1. The specific control method is to connect the gate of the second thin film transistor 152 to the gate line G_N+1.

Specifically, in step tl of FIG. 3, the clock control signal CK1 is at a high level, and the shift register unit GOA_N-1 connected to the clock control signal CK1 outputs a drive signal, and at this time, the N-1th gate line G_N-1 The level is high because the thin film transistor of the auxiliary driving circuit 15 is preferably an N-type thin film transistor, so that the first thin film transistor 151 of the Nth row gate line G_N is turned on because the source of the thin film transistor 151 and the clock of CK2 The control signal is connected. As shown in FIG. 3, in the t1 phase, the clock control signal CK2 is at a low level, and even if the first thin film transistor 151 is turned on, no compensation signal is transmitted to the Nth gate line G_N, but at 12 In the phase, at this time, because the N-1th gate line G_N-1 is still at a high level, the clock control signal CK2 is turned to a high level, and the signal of the clock control signal CK2 is output to the Nth gate line G_N. A signal output is formed, which is equivalent to precharging the Nth gate line G_N, reducing the delay of the rising edge of the Nth gate line G_N. In the t3 phase, the clock control signal CK3 starts to be at a high level, that is, the N+1th gate line G_N+1 is at a high level, and at this time, the second thin film transistor 152 of the Nth gate line G_N is turned on, and the clock control signal is CK2 is high, clock control at this time The signal of the signal CK2 is outputted to the Nth row gate line G_N to form a signal output, which is equivalent to charging and maintaining the Nth row gate line G_N. In the stage t4, the clock control signal CK3 is still at a high level, and the second thin film transistor 152 of the Nth gate line G_N is still turned on, but at this time, the clock control signal CK2 is turned to a low level, so equivalent to The falling edge of the Nth gate line G_N forms a signal output, reducing the delay of its falling edge.

 As shown in FIG. 4, the line 3 in the figure is a driving waveform curve when the gate driving device provided by the embodiment is driven, and the line 4 is a driving waveform curve when the gate driving device of the embodiment is not used to drive only one side. . As can be seen from FIG. 4, the gate driving device provided by the embodiment, that is, the rising edge time Tr1 of the driving waveform delayed by the gate driving signal is compensated by the auxiliary driving circuit 15 (ie, rising from the rising edge of the pulse wave by 10% to 90%). The elapsed time) and the falling edge time Tfl (i.e., the time elapsed from the falling of the pulse wave falling edge by 90% to 10%) are shorter than the driving waveform rising edge time Tr2 and the falling edge time Tf2 at the time of one-side driving. Since the rising edge time Tr affects the charging of the pixel, the shorter the time, the more sufficient the charging of the pixel; the falling edge time Tf affects the final voltage of the pixel, and the shorter the time, the more consistent the waveform characteristics of the gate. That is, the gate driving means for compensating the gate driving signal by the auxiliary driving circuit 15 allows the display device to obtain better picture uniformity.

 It should be further noted that the auxiliary driving circuit 15 in this embodiment is controlled by the "upper row gate line" and the "next row gate line" two rows of gate lines 14 of the row gate line 14 because this embodiment As shown in FIG. 3, the clock control signal line 2 for illustration is two sets of four lines, wherein the clock control signal CK1 and the clock control signal CK3 are a group, and the clock control signal CK2 and the clock control signal CK4 are a group. The two lines of the group are in opposite phase. In fact, three sets of 6 lines or 4 sets of 8 lines and other components of the clock control signal line 2 may also be understood, as long as the working level and the working level of the row line 14 at least partially overlap. Other row gate lines 14 can be used to control the auxiliary driving circuit, and the row gate lines 14 are compensated by corresponding clock control signals. No matter how many rows of gate lines 14 control the auxiliary driving circuit 15, as long as the compensation effect can be achieved, can.

It can be seen that, in the gate driving circuit 13 in this embodiment, since the auxiliary driving circuit 15 capable of providing a compensation signal to each row of gate lines 14 is enabled, the gate driving circuit 13 can also satisfy the driving requirements of the large panel, and the gate driving signal The delay is small. At the same time, because the structure of the auxiliary driving circuit 15 is simple, the space occupied by the gate driving circuit 13 is greatly reduced, and the On the basis of not changing the characteristics of the existing gate signal, the size of the gate driving circuit 13 is reduced, and the effective display area is increased, which makes it possible to further realize the narrow frame of the display device. Example 3:

 The embodiment provides a display device, including:

 The gate driving device in any of the above embodiments.

 Of course, the display device of this embodiment may further include other known components such as a color filter substrate, a power supply unit, a backlight, and the like, and will not be described in detail herein.

 Since the display device of the embodiment has the above-mentioned gate driving device, the circuit barrel and the gate driving circuit occupy a small space, so that the effective display can be improved without changing the characteristics of the existing gate signal. The area and the possibility of realizing a narrow bezel of the display device make the display device more beautiful. Exemplary embodiments, however, the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

Claims

Claim A gate driving device comprising: a plurality of shift register units respectively connected to one end of each row of gate lines; and an auxiliary driving circuit connected to the other end of each of the rows of gate lines, one of which is connected The gate line of the auxiliary driving circuit, the auxiliary driving circuit compensates the row gate line with a control signal by control of other row gate lines connected thereto.  2. The gate driving device according to claim 1, wherein the control signal is a clock control signal of the row gate line.  3. The gate driving device according to claim 1, wherein  The other row gate lines connected to the auxiliary driving circuit are gate lines whose operating level at least partially overlaps the operating level of the row gate lines.  4. The gate driving device according to claim 3, wherein the manner in which the other gate lines control the auxiliary driving circuit comprises:  When the signal in the row gate line is a rising edge, the auxiliary driving circuit is controlled by other row gate lines at an operating level;  When the signal in the row gate line is a falling edge, the auxiliary drive circuit is thus controlled by other row gate lines at an operating level.  The gate driving device according to claim 4, wherein the auxiliary driving circuit connected to the row gate line includes a first switching unit and a second switching unit, the first switching unit and the first The two switching units are respectively controlled by the upper row of gate lines of the row gate lines and the next row of gate lines of the row gate lines.  The gate driving device according to claim 5, wherein the switching unit is an N-type thin film transistor.  7. The gate driving device according to claim 6, wherein  a gate of the first thin film transistor is connected to the gate line of the upper row, a drain of the first thin film transistor is connected to the gate line, a source of the first thin film transistor and the gate line Clock control signal connection; a gate of the second thin film transistor is connected to the gate line of the next row, a drain of the second thin film transistor is connected to the gate line, a source of the second thin film transistor and the gate line The clock control signal is connected. The gate driving device according to any one of claims 1 to 7, wherein each of the shift register units is located at the same end of each of the gate lines, and the auxiliary driving circuit is provided at the other of the gate lines One end.  The gate driving device according to any one of claims 1 to 7, further comprising a substrate, the auxiliary driving circuit being provided on the substrate.  A display device comprising the gate driving device according to any one of claims 1 to 7.