Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
  • H03F3/45183—Long tailed pairs
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0264—Arrangements for coupling to transmission lines
  • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
  • H04L25/0276—Arrangements for coupling common mode signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0264—Arrangements for coupling to transmission lines
  • H04L25/0292—Arrangements specific to the receiver end
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/513—Indexing scheme relating to amplifiers the amplifier being made for low supply voltages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45008—Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45078—Indexing scheme relating to differential amplifiers the common mode signal being taken or deducted from the one or more inputs of the differential amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45454—Indexing scheme relating to differential amplifiers the CSC comprising biasing means controlled by the input signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45466—Indexing scheme relating to differential amplifiers the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors

Definitions

• the present invention relates to circuit technologies, and more specifically, to a low-voltage differential signal receiver.
• LVDS Low-voltage Differential Signaling
• LVDS Low-voltage Differential Signaling
• LVDS has a very low demand on transmission medium, and inexpensive transmission medium such that twisted-pair copper cables can be used.
• FIG. 1 is a schematic diagram of typical LVDS receiver, wherein LVDS signals at an input stage are a pair of differential signals Ina and Inb. If the Ina has a voltage higher than Inb, the signal indicates one logic value; if the Inb has a voltage lower than Ina, the signal indicates another logical value.
• the voltage average value of the Ina and Inb is called a common mode voltage.
• the voltage of the Ina and Inb respectively result from adding a swing voltage to and subtracting the swing voltage from the common mode voltage. Assume the common mode voltage is IV and the swing voltage is 0.1V, at a certain stable time the Ina signal is 1. IV whereas the Inb signal is 0.9V, or the Ina signal is 0.9V whereas the Inb signal is 1. IV.
• the LVDS signal in Fig. 1 is connected to the input stage of the LVDS receiver via a temiination resistor.
• the termination resistor is used to match a characteristic impedance of the transmission media.
• the input stage converts the LVDS differential signal into internal differential signals Outa and Outb corresponding to a power supply voltage.
• An output stage converts internal differential signals Outa and Outb into a single-ended signal Out. On some occasions using chips, the output stage can be omitted.
• a common mode voltage range of the LVDS is 0V-2.4V. That is to say, the common mode voltage of the LVDS signal received by the LVDS receiver can be any value of 0V-2.4V.
• the LVDS receiver needs to convert the LVDS signal having any value of 0V-2.4V as the common mode voltage into a signal identifiable by a subsequent circuit.
• NMOS or PMOS differential pair can be chosen as the input stage of Fig. 1. However, if the power supply voltage falls to a certain extent, the receiver cannot convert the LVDS signal whose common mode voltage is in a certain range.
• the receiver using NMOS differential pair as the input stage might not convert the LVDS signal whose common mode voltage is in the range of 0V-1.2V, and can only convert the LVDS signal whose common mode voltage is in the range of 1.2V-2.4V; similarly, the receiver using PMOS differential pair as the input stage might not convert the LVDS signal whose common mode voltage is in the range of 0.8V-2.4V, and can only convert the LVDS signal whose common mode voltage is in the range of 0V-0.8V.
• the power supply voltage of the chip will become lower and lower.
• the LVDS receiver integrated on the chip has to convert the LVDS signal at a lower power supply voltage.
• Embodiments of the present invention provide an LVDS receiver, a chip comprising the LVDS receiver and a method of receiving an LVDS signal.
• An LVDS receiver comprises: a first type of input stage and a second type of input stage respectively configured to convert an input LVDS signal into an internal differential signal; a common mode voltage determination circuit configured to detemiine a common mode voltage of the input LVDS signal; an input stage selection circuit configured to compare the common mode voltage with a reference voltage, and output an enabling signal according to comparison results, wherein when the common mode voltage is lower than the reference voltage, the enabling signal is a first logic voltage, and the first logic voltage enables the first type of input stage to be in a working state and the second type of input stage in an idle state, and wherein when the common mode voltage is lower than the reference voltage, the enabling signal is a second logic voltage, and the second logic voltage enables the second type of input stage to be in a working state and the first type of input stage in an idle state, wherein the first type of input stage is one of an NMOS input stage and a PMOS input stage, and the second type of input stage is the other
• the chip according to one embodiment of the present invention comprises the above LVDS receiver.
• a method of receiving an LVDS signal comprises: obtaining the common mode voltage of a received LVDS signal; comparing the common mode voltage with the reference voltage; and enabling the first type of input stage to be in the working state and the second type of input stage in the idle state in response to the common mode voltage being higher than the reference voltage, and enabling the second type of input stage to be in the working state and the first type of input stage in the idle state in response to the common mode voltage being lower than the reference voltage, wherein the first type of input stage is one of an NMOS input stage and a PMOS input stage, and the second type of input stage is the other of the NMOS input stage and the PMOS input stage.
• the LVDS signal can be processed at a lower power supply voltage in an entire range of the common mode voltage.
• Fig. 1 is a schematic diagram of a typical LVDS receiver.
• FIG. 2 is a schematic diagram of an LVDS receiver according to one embodiment of the present invention.
• FIG. 3(a) and Fig. 3(b) illustrate implementation modes of a PMOS input stage and an NMOS input stage according to one embodiment of the present invention.
• Fig. 4 illustrates an implementation mode of a common mode voltage determination circuit and an input stage selection circuit according to one embodiment of the present invention.
• FIG. 5 illustrates a flowchart of a method of receiving LVDS according to one embodiment of the present invention.
• FIG. 6 illustrates comparison of power consumption of the LVDS receiver according to one embodiment of the present invention and an LVDS receiver comprising a rail-to-rail input stage.
• a switch-on voltage of an N-type transistor is a high voltage
• a switch-on voltage of a P-type transistor is a low voltage.
• the conditions for high and low voltages as involved in the following description may all vary with the change of the type of a corresponding device. Besides, the conditions may also be varied by adding an extra device. For example, for a high-voltage switch-on N-type transistor, if a NOT Gate device is added between a grid of the N-type transistor and an input signal, then the transistor may be broken over when the input signal is a low voltage. All of these variations are equivalent to the embodiments of the present invention described below.
• a current mirror can be externally connected to an input stage of the receiver so as to pull up or pull down the common mode voltage of the LVDS signal.
• the external current mirror needs to consume more power.
• the input stage can be set as a rail-to-rail input stage comprised of a PMOS differential pair or an NMOS differential pair.
• this method requires the NMOS differential pair and the PMOS differential pair to operate at the same time and has to use folded cascode as a load.
• FIG. 2 is a schematic diagram of an LVDS receiver according to one embodiment of the present invention.
• the LVDS receiver comprises a common mode voltage determination circuit, an input stage selection circuit, an NMOS input stage and a PMOS input stage.
• the common mode voltage determination circuit is configured to receive an LVDS signal to determine the common mode voltage of the inputted LVDS signal.
• the input stage selection circuit is configured to compare the common mode voltage of the LVDS signal with a reference voltage, and select one of the NMOS input stage and the PMOS input stage via an enabling signal according to comparison results.
• the selected one of the NMOS input stage and PMOS input stage is in a working state, and receives the LVDS signal and processes it into an internal differential signal.
• the unselected one of the NMOS input stage and PMOS input stage is in an idle state so that it does not generate any power consumption.
• the LVDS receiver shown in Fig. 2 only one of the NMOS input stage and PMOS input stage is in a working state. Thus, it is unnecessary to use folded cascode as a load or an extra current mirror. Hence, the LVDS receiver shown in Fig. 2 can avoid generation of extra power consumption.
• the LVDS signal with a common mode voltage of 0V-2.4V can be processed at a lower power supply voltage.
• neither of the NMOS input stage and PMOS input stage can process the LVDS signal in an entire voltage range
• the NMOS input stage and PMOS input stage are complementary to each other in their operating range.
• the operating range of the PMOS input stage is 0V-1.6V
• the operating range of the NMOS input stage is 0.8V-2.4V.
• the LVDS signal in the entire voltage range can be processed so long as the PMOS input stage is enabled in a working state when the common mode voltage of the LVDS is in the range of 0V-1.6V, and the NMOS input stage is enabled in the working state when the common mode voltage of the LVDS is in the range of 0.8V-2.4V.
• the PMOS input stage can comprise a PMOS differential pair plus a PMOS input stage switch circuit
• the NMOS input stage can comprise an NMOS differential pair plus an NMOS input stage switch circuit.
• Fig. 3(a) and Fig. 3(b) respectively illustrate a specific implementation mode of the PMOS input stage and the NMOS input stage according to one embodiment of the present invention.
• input LVDS signals Ina and Inb are respectively connected to a gate of a first PMOS transistor and a second PMOS transistor.
• the first PMOS transistor and the second PMOS transistor are two transistors having the same properties.
• Sources of the first PMOS transistor and the second PMOS transistor are connected at a first node.
• the first node is further connected to a power supply voltage.
• Drains of the first PMOS transistor and the second PMOS transistor are respectively connected to one end of a first resistor and a second resistor.
• the other end of the first resistor is connected to the other end of the second resistor at a second node.
• the second node is further connected to a ground voltage.
• the drains of the first PMOS transistor and the second PMOS transistor respectively generate an Outa signal and an Outb signal.
• the Outa signal and Outb signal are, as a pair of differential signals, connected to an optional output stage.
• input LVDS signals Ina and Inb are respectively connected to the gate of the first NMOS transistor and the second NMOS transistor.
• the first NMOS transistor and the second NMOS transistor are two transistors having the same properties.
• the drain of the first NMOS transistor and the second NMOS transistor are respectively connected to an end of a third resistor and a fourth resistor.
• the other end of the third resistor is connected to the other end of the fourth resistor at a third node.
• the third node is further connected to the power supply voltage.
• the source of the first NMOS transistor and the second NMOS transistor are connected to each other at a fourth node.
• the fourth node is further connected to the ground voltage.
• the drain of the first NMOS transistor and the second NMOS transistor respectively generate an Outa signal and an Outb signal.
• the Outa signal and Outb signal are, as a pair of differential signals, connected to an optional output stage.
• a PMOS input stage switch circuit and an NMOS input stage switch circuit are respectively provided for the PMOS input stage and the NMOS input stage.
• the PMOS input stage switch circuit can be implemented by a third PMOS transistor disposed between the first node and the power supply voltage. Specifically, the gate of the third PMOS transistor is connected to an enabling signal, the source is connected to the power supply voltage, and the drain is connected to the first node.
• the NMOS input stage switch circuit can be implemented by a third NMOS transistor disposed between the fourth node and the ground voltage. Specifically, the gate of the third NMOS transistor is connected to the enabling signal, the drain is connected to the fourth node, and the source is connected to the ground voltage.
• the PMOS input stage switch circuit can be implemented by a transistor disposed between the second node and the ground voltage, and again for example, the PMOS input stage switch circuit can also be implemented by a NMOS transistor.
• the PMOS input stage and the NMOS input stage both have the Ina signal and the Inb signal as input, their switch circuits both have Vbias as the enabling signal, and their output is the differential signal pair Outa and Outb.
• Vbias is a second logic voltage
• the third PMOS transistor is turned on and the third NMOS transistor is turned off, then the NMOS input stage is in an idle state, i.e., does not generate power consumption, whereas the PMOS input stage is in a working state and processes the LVDS signal
• Vbias is a first logic voltage
• the third PMOS transistor is turned off and the third NMOS transistor is turned on, and then the PMOS input stage is in a working state and processes the LVDS signal whereas the NMOS input stage is in an idle state, i.e., does not generate power consumption.
• Fig. 4 illustrates an implementation mode of a common mode voltage determination circuit and an input stage selection circuit according to one embodiment of the present invention.
• the common mode voltage determination circuit in Fig. 4 can be implemented by making simple modification to a termination resistor in the prior art. In other words, the common mode voltage determination circuit does not add too many devices to the LDVS receiver in the prior art.
• the termination resistor in the prior art is changed into two serially connected resistors with the same resistance value, namely, a first resistor divider and a second resistor divider.
• the signal voltage at a fifth node where the first resistor divider is connected to the second resistor divider is the common mode voltage of the LDVS signal.
• the reference voltage Vref in Fig. 4 can be implemented by a voltage division circuit between the power supply and the ground.
• the power supply voltage is 3 V and the reference voltage Vref needs to be set as 1.0V
• a third resistor divider and a fourth resistor divider are provided in series between the power supply and the ground, and a ratio of the resistance value of the third resistor divider to that of the fourth resistor divider is 2:1.
• the signal at the sixth node where the third resistor divider is connected to the fourth resistor divider is the reference voltage Vref of 1.0V.
• the input stage selection circuit in Fig. 4 is a comparator which compares the LVDS common mode voltage and the reference voltage to output the enabling signal.
• the common mode voltage range that can be processed by the NMOS input stage is close to the end of 2.4V
• the common mode voltage range that can be processed by the PMOS input stage is close to the end of 0V.
• the enabling signal output by the input stage selection circuit should enable the NMOS input stage to be in a working state and the PMOS input stage in an idle state; when the common mode voltage is lower than the reference voltage, the enabling signal output by the input stage selection circuit should enable the NMOS input stage to be in an idle state and the PMOS input stage in a working state.
• the comparator is a low frequency comparator.
• the LVDS signal has a very high data transmission rate, i.e., a signal switching frequency on the Ina and Inb is very high, the common mode voltage of a period of LVDS signal is relatively stable and is a low frequency signal.
• the low-frequency comparator is simpler than the high-frequency comparator, so it occupies a smaller area on the chip and has a lower processing requirement. Besides, the power consumption of the low-frequency comparator is lower than the high-frequency comparator.
• the comparator is a comparator having hysteresis switching properties.
• the output enable voltage initiates a switching.
• assumption is made as below: when the common mode voltage is higher than the reference voltage, the enabling signal indicates the first logic voltage; when the common mode voltage is lower than the reference voltage, the enabling signal indicates the second logic voltage.
• a comparator with a Schmitt trigger is used.
• the enabling signal When the common mode voltage changes from a voltage higher than the reference signal to a voltage lower than the reference signal, the enabling signal does not certainly switch from the first logic voltage to the second logic voltage; only when an absolute value of the difference between the common mode voltage and the reference voltage is higher than a first threshold value, the enabling signal switches from the first logic voltage to the second logic voltage.
• the enabling signal when the common mode voltage changes from a voltage lower than the reference signal to a voltage higher than the reference signal, the enabling signal does not certainly switch from the second logic voltage to the first logic voltage; only when the absolute value of the difference between the common mode voltage and the reference voltage is higher than a second threshold value, the enabling signal switches from the second logic voltage to the first logic voltage.
• the enabling signal when the theoretical common mode voltage is higher than the reference voltage, even if a practical common mode voltage is made lower than the reference voltage due to influence of the noise, the enabling signal will not switch so long as the noise is not so large that the absolute value of the difference between the practical common mode voltage and the reference voltage is higher than the first threshold value.
• the enabling signal when the theoretical common mode voltage is lower than the reference voltage, even if a practical common mode voltage is made higher than the reference voltage due to influence of the noise, the enabling signal will not switch so long as the noise is not so large that the absolute value of the difference between the practical common mode voltage and the reference voltage is larger than the second threshold value.
• a low-pass Filter is provided between the Fifth node and the comparator.
• the common mode voltage signal is a low-frequency signal, so the low-pass Filter can be used to retain the common mode voltage signal and eliminate noise.
• the implementation of the low-pass filter is of common knowledge in the art, and will not be discussed in detail here.
• the common mode voltage range that can be processed by the NMOS input stage is close to the end of 2.4V
• the common mode voltage range that can be processed by the PMOS input stage is close to the end of 0V.
• Vdd - Vdsatpl + Vdsatp2 + Vthp
• Vdd an upper limit thereof
• Vdd is the power supply voltage
• Vdsatpl denotes a saturation voltage of the third NMOS transistor
• Vdsapt2 denotes a saturation voltage of the First or second NMOS transistor
• Vthp is a threshold voltage of the first or second NMOS transistor.
• a lower limit of the common mode voltage that can be processed by the PMOS input stage is a ground voltage, and an upper limit thereof is (Vdsatnl + Vdsatn2 + Vthn), wherein the Vdsatnl denotes a saturation voltage of third PMOS transistor, Vdsatn2 denotes a saturation voltage of the first or second PMOS transistor, and Vthn is a threshold voltage of the first or second PMOS transistor.
• the lower limit of the common mode voltage that can be processed by the NMOS input stage is lower than the upper limit of the common mode voltage that can be processed by the PMOS input stage.
• the reference voltage Vref can be set as any voltage value between the lower limit of the common mode voltage that can be processed by the NMOS input stage and the upper limit of the common mode voltage that can be processed by the PMOS input stage.
• the enabling signal switches from the first logic voltage to the second logic voltage. Therefore, the voltage value obtained by subtracting the first threshold value from the Vref should be higher than the lower limit of the common mode voltage that can be processed by the NMOS input stage.
• the common mode voltage changes from a voltage lower than the reference voltage to a voltage higher than the reference voltage and the absolute value of the difference between the common mode voltage and reference voltage is larger than the second threshold value
• the enabling signal switches from the second logic voltage to the first logic voltage. Therefore, the voltage value obtained by adding the second threshold value to the Vref should be lower than the upper limit of the common mode voltage that can be processed by the PMOS input stage.
• FIG. 5 illustrates a flowchart of a method of receiving LVDS signal according to one embodiment of the present invention.
• a common mode voltage of a received LVDS signal is obtained.
• the common mode voltage is compared with a reference voltage.
• the NMOS input stage is allowed to be in a working state and the PMOS input stage in an idle state in response to the common mode voltage being higher than the reference voltage, and the PMOS input stage is allowed to be in a working state and the NMOS input stage in an idle state in response to the common mode voltage being lower than the reference voltage.
• the LVDS signal is transmitted in a long distance, and its common mode voltage might jitter due to influence of noise. Hence, the magnitude relationship between the common mode voltage and the reference voltage needs to be avoided from frequently switching due to influence of the noise.
• the switching of the input stage is triggered, but that the switching is triggered after the difference between the common mode voltage and the reference voltage reaches a certain degree.
• the NMOS input stage is switched from the idle state to the working state and the PMOS input stage is switched from the working state to the idle state only when the common mode voltage changes from a voltage lower than the reference voltage to a voltage higher than the reference voltage, and the absolute value of the difference between the common mode voltage and the reference voltage is higher than the second threshold value.
• the NMOS input stage is switched from the working state to the idle state and the PMOS input stage is switched from the idle state to the working state only when the common mode voltage changes from a voltage higher than the reference voltage to a voltage lower than the reference voltage, and the absolute value of the difference between the common mode voltage and the reference voltage is higher than the first threshold value.
• a signal indicative of the common mode voltage after passing through the low-pass filter, can be compared with the reference voltage.
• the common mode voltage itself is a low-frequency signal and can pass through the low-pass filter; on the other hand, noise is a wideband signal, and the low-frequency filter can filter away a high-frequency portion, thereby reducing the strength of the noise. As such, the influence of noise on the comparison results can be weakened.
• the LVDS receiver according to one embodiment of the present invention at a transmission rate of lGbps, can be adapted for various standard common mode voltages, and can operate normally at the worst process conditions.
• a maximum of a delay error of the output signal and input signal of the LVDS receiver according to the embodiment of the present invention is 38ps (picosecond), by far less than a data cycle of 1 nanosecond (ns).
• the LVDS receiver according to the embodiment of the present invention at most consumes a current of 1.2 mA at various LVDS common mode electrical levels, i.e., a point Ml in the figure.
• the LVDS receiver having the rail-to-rail input stage at most consumes a current of 6.68 mA, i.e., a point M0 in the figure.
• the power consumption of the LVDS receiver according to the embodiment of the present invention is substantially reduced.
• a horizontal ordinate denotes a common mode electrical level of the LVDS signal and a longitudinal ordinate denotes electrical current consumed by the LVDS receiver.

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