WO2013127335A1

WO2013127335A1 - Low-voltage differential signal receiver

Info

Publication number: WO2013127335A1
Application number: PCT/CN2013/071924
Authority: WO
Inventors: Guangyu PENG; Wanxin SHAO; Si SHI
Original assignee: IBM China Co Ltd; International Business Machines Corp
Current assignee: IBM China Co Ltd; International Business Machines Corp
Priority date: 2012-02-28
Filing date: 2013-02-27
Publication date: 2013-09-06
Anticipated expiration: 2014-08-28
Also published as: CN103296984A

Description

LOW- VOLTAGE DIFFERENTIAL SIGNAL RECEIVER

FIELD OF THE INVENTION

[0001 ] The present invention relates to circuit technologies, and more specifically, to a low-voltage differential signal receiver.

BACKGROUND OF THE INVENTION

[0002] LVDS (Low-voltage Differential Signaling) is a voltage standard. It can provide a high data transmission rate with lower power consumption and has a strong noise suppressing capability. Besides, LVDS has a very low demand on transmission medium, and inexpensive transmission medium such that twisted-pair copper cables can be used.

[0003] An LVDS receiver functions to convert the LVDS into a signal identifiable by a subsequent circuit. Fig. 1 is a schematic diagram of typical LVDS receiver, wherein LVDS signals at an input stage are a pair of differential signals Ina and Inb. If the Ina has a voltage higher than Inb, the signal indicates one logic value; if the Inb has a voltage lower than Ina, the signal indicates another logical value. The voltage average value of the Ina and Inb is called a common mode voltage. The voltage of the Ina and Inb respectively result from adding a swing voltage to and subtracting the swing voltage from the common mode voltage. Assume the common mode voltage is IV and the swing voltage is 0.1V, at a certain stable time the Ina signal is 1. IV whereas the Inb signal is 0.9V, or the Ina signal is 0.9V whereas the Inb signal is 1. IV.

[0004] The LVDS signal in Fig. 1 is connected to the input stage of the LVDS receiver via a temiination resistor. The termination resistor is used to match a characteristic impedance of the transmission media. The input stage converts the LVDS differential signal into internal differential signals Outa and Outb corresponding to a power supply voltage. An output stage converts internal differential signals Outa and Outb into a single-ended signal Out. On some occasions using chips, the output stage can be omitted.

[0005] According to IEEE 1596.3 Standard, a common mode voltage range of the LVDS is 0V-2.4V. That is to say, the common mode voltage of the LVDS signal received by the LVDS receiver can be any value of 0V-2.4V. The LVDS receiver needs to convert the LVDS signal having any value of 0V-2.4V as the common mode voltage into a signal identifiable by a subsequent circuit.

[0006] If the power supply voltage of the LVDS is large enough, either NMOS or PMOS differential pair can be chosen as the input stage of Fig. 1. However, if the power supply voltage falls to a certain extent, the receiver cannot convert the LVDS signal whose common mode voltage is in a certain range. For example, when the power supply voltage falls to a certain degree, the receiver using NMOS differential pair as the input stage might not convert the LVDS signal whose common mode voltage is in the range of 0V-1.2V, and can only convert the LVDS signal whose common mode voltage is in the range of 1.2V-2.4V; similarly, the receiver using PMOS differential pair as the input stage might not convert the LVDS signal whose common mode voltage is in the range of 0.8V-2.4V, and can only convert the LVDS signal whose common mode voltage is in the range of 0V-0.8V.

[0007] As the chip technology develops, the power supply voltage of the chip will become lower and lower. Hence, the LVDS receiver integrated on the chip has to convert the LVDS signal at a lower power supply voltage.

SUMMARY OF THE INVENTION

[0008] Embodiments of the present invention provide an LVDS receiver, a chip comprising the LVDS receiver and a method of receiving an LVDS signal.

[0009] An LVDS receiver according to one embodiment of the present invention comprises: a first type of input stage and a second type of input stage respectively configured to convert an input LVDS signal into an internal differential signal; a common mode voltage determination circuit configured to detemiine a common mode voltage of the input LVDS signal; an input stage selection circuit configured to compare the common mode voltage with a reference voltage, and output an enabling signal according to comparison results, wherein when the common mode voltage is lower than the reference voltage, the enabling signal is a first logic voltage, and the first logic voltage enables the first type of input stage to be in a working state and the second type of input stage in an idle state, and wherein when the common mode voltage is lower than the reference voltage, the enabling signal is a second logic voltage, and the second logic voltage enables the second type of input stage to be in a working state and the first type of input stage in an idle state, wherein the first type of input stage is one of an NMOS input stage and a PMOS input stage, and the second type of input stage is the other of the NMOS input stage and the PMOS input stage.

[0010] The chip according to one embodiment of the present invention comprises the above LVDS receiver.

[001 1] A method of receiving an LVDS signal according to another embodiment of the present invention comprises: obtaining the common mode voltage of a received LVDS signal; comparing the common mode voltage with the reference voltage; and enabling the first type of input stage to be in the working state and the second type of input stage in the idle state in response to the common mode voltage being higher than the reference voltage, and enabling the second type of input stage to be in the working state and the first type of input stage in the idle state in response to the common mode voltage being lower than the reference voltage, wherein the first type of input stage is one of an NMOS input stage and a PMOS input stage, and the second type of input stage is the other of the NMOS input stage and the PMOS input stage.

[0012] According to the technical solutions provided by the embodiments of the present invention, the LVDS signal can be processed at a lower power supply voltage in an entire range of the common mode voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Through the more detailed description of some embodiments of the present disclosure in the accompanying drawings, the above and other objects, features and advantages of the present disclosure will become more apparent, wherein the same reference generally refers to the same components in the exemplary embodiments of the present disclosure.

[0014] Fig. 1 is a schematic diagram of a typical LVDS receiver.

[0015] Fig. 2 is a schematic diagram of an LVDS receiver according to one embodiment of the present invention.

[0016] Fig. 3(a) and Fig. 3(b) illustrate implementation modes of a PMOS input stage and an NMOS input stage according to one embodiment of the present invention.

[0017] Fig. 4 illustrates an implementation mode of a common mode voltage determination circuit and an input stage selection circuit according to one embodiment of the present invention.

[0018] Fig. 5 illustrates a flowchart of a method of receiving LVDS according to one embodiment of the present invention.

[0019] Fig. 6 illustrates comparison of power consumption of the LVDS receiver according to one embodiment of the present invention and an LVDS receiver comprising a rail-to-rail input stage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Some preferable embodiments will be described in more detail with reference to the accompanying drawings, in which the preferable embodiments of the present disclosure have been illustrated. However, the present disclosure can be implemented in various manners, and thus should not be construed to be limited to the embodiments disclosed herein. On the contrary, those embodiments are provided for the thorough and complete understanding of the present disclosure, and completely conveying the scope of the present disclosure to those skilled in the art. The drawings are provided for exemplary purposes and thus not drawn in scale. Besides, when a first element is described as being connected to a second element, the first element may not only be directly connected to the second element, but also be indirectly connected to the second element via a third element. Further, for the sake of clarity, some elements unnecessary for thoroughly understanding the present invention are omitted. In the drawings, like or corresponding elements are represented b like reference signs.

[0021 ] Those skilled in the art would appreciate that in the digital circuit, voltage has a symmetrical relation with a device type. For example, a switch-on voltage of an N-type transistor is a high voltage, and a switch-on voltage of a P-type transistor is a low voltage. Thus, the conditions for high and low voltages as involved in the following description may all vary with the change of the type of a corresponding device. Besides, the conditions may also be varied by adding an extra device. For example, for a high-voltage switch-on N-type transistor, if a NOT Gate device is added between a grid of the N-type transistor and an input signal, then the transistor may be broken over when the input signal is a low voltage. All of these variations are equivalent to the embodiments of the present invention described below.

[0022] In order to ensure conversion of the LVDS signal having a common mode voltage in the range of 0V-2.4V at a low power supply voltage, a current mirror can be externally connected to an input stage of the receiver so as to pull up or pull down the common mode voltage of the LVDS signal. The external current mirror needs to consume more power. Besides, the input stage can be set as a rail-to-rail input stage comprised of a PMOS differential pair or an NMOS differential pair. However, this method requires the NMOS differential pair and the PMOS differential pair to operate at the same time and has to use folded cascode as a load. These limitations also increase the power consumption.

[0023j Fig. 2 is a schematic diagram of an LVDS receiver according to one embodiment of the present invention.

[0024] As shown in Fig. 2, the LVDS receiver according to one embodiment of the present invention comprises a common mode voltage determination circuit, an input stage selection circuit, an NMOS input stage and a PMOS input stage.

[0025] The common mode voltage determination circuit is configured to receive an LVDS signal to determine the common mode voltage of the inputted LVDS signal. The input stage selection circuit is configured to compare the common mode voltage of the LVDS signal with a reference voltage, and select one of the NMOS input stage and the PMOS input stage via an enabling signal according to comparison results. The selected one of the NMOS input stage and PMOS input stage is in a working state, and receives the LVDS signal and processes it into an internal differential signal. The unselected one of the NMOS input stage and PMOS input stage is in an idle state so that it does not generate any power consumption.

[0026] In the LVDS receiver shown in Fig. 2, only one of the NMOS input stage and PMOS input stage is in a working state. Thus, it is unnecessary to use folded cascode as a load or an extra current mirror. Hence, the LVDS receiver shown in Fig. 2 can avoid generation of extra power consumption.

[0027] In another aspect, by selecting one of the NMOS input stage and PMOS input stage and enabling it to enter a working state according to the common mode voltage of the LVDS signal, the LVDS signal with a common mode voltage of 0V-2.4V can be processed at a lower power supply voltage. Although at the lower power supply voltage, neither of the NMOS input stage and PMOS input stage can process the LVDS signal in an entire voltage range, meanwhile, the NMOS input stage and PMOS input stage are complementary to each other in their operating range. For example, the operating range of the PMOS input stage is 0V-1.6V, and the operating range of the NMOS input stage is 0.8V-2.4V. Hence, the LVDS signal in the entire voltage range can be processed so long as the PMOS input stage is enabled in a working state when the common mode voltage of the LVDS is in the range of 0V-1.6V, and the NMOS input stage is enabled in the working state when the common mode voltage of the LVDS is in the range of 0.8V-2.4V.

[0028] The above integral parts of the LVDS receiver are described in detail with reference to the figures.

[0029] The PMOS input stage can comprise a PMOS differential pair plus a PMOS input stage switch circuit, and the NMOS input stage can comprise an NMOS differential pair plus an NMOS input stage switch circuit. Fig. 3(a) and Fig. 3(b) respectively illustrate a specific implementation mode of the PMOS input stage and the NMOS input stage according to one embodiment of the present invention.

[0030] In Fig. 3(a), input LVDS signals Ina and Inb are respectively connected to a gate of a first PMOS transistor and a second PMOS transistor. The first PMOS transistor and the second PMOS transistor are two transistors having the same properties. Sources of the first PMOS transistor and the second PMOS transistor are connected at a first node. The first node is further connected to a power supply voltage. Drains of the first PMOS transistor and the second PMOS transistor are respectively connected to one end of a first resistor and a second resistor. The other end of the first resistor is connected to the other end of the second resistor at a second node. The second node is further connected to a ground voltage. The drains of the first PMOS transistor and the second PMOS transistor respectively generate an Outa signal and an Outb signal. The Outa signal and Outb signal are, as a pair of differential signals, connected to an optional output stage.

[0031 ] In Fig. 3(b), input LVDS signals Ina and Inb are respectively connected to the gate of the first NMOS transistor and the second NMOS transistor. The first NMOS transistor and the second NMOS transistor are two transistors having the same properties. The drain of the first NMOS transistor and the second NMOS transistor are respectively connected to an end of a third resistor and a fourth resistor. The other end of the third resistor is connected to the other end of the fourth resistor at a third node. The third node is further connected to the power supply voltage. The source of the first NMOS transistor and the second NMOS transistor are connected to each other at a fourth node. The fourth node is further connected to the ground voltage. The drain of the first NMOS transistor and the second NMOS transistor respectively generate an Outa signal and an Outb signal. The Outa signal and Outb signal are, as a pair of differential signals, connected to an optional output stage.

[0032] As stated above, only one of the PMOS input stage and the NMOS input stage is in the working state, and the other is in the idle state. Therefore, according to the embodiment of the present invention, a PMOS input stage switch circuit and an NMOS input stage switch circuit are respectively provided for the PMOS input stage and the NMOS input stage. The PMOS input stage switch circuit can be implemented by a third PMOS transistor disposed between the first node and the power supply voltage. Specifically, the gate of the third PMOS transistor is connected to an enabling signal, the source is connected to the power supply voltage, and the drain is connected to the first node. The NMOS input stage switch circuit can be implemented by a third NMOS transistor disposed between the fourth node and the ground voltage. Specifically, the gate of the third NMOS transistor is connected to the enabling signal, the drain is connected to the fourth node, and the source is connected to the ground voltage.

[0033] Those skilled in the art can appreciate that there are further many modes of providing the PMOS input stage switch circuit and NMOS input stage switch circuit so long as it is ensured that one of the PMOS input stage switch circuit and the NMOS input stage switch circuit is closed and the other opened in the event of the same enabling signal. For example, the PMOS input stage switch circuit can be implemented by a transistor disposed between the second node and the ground voltage, and again for example, the PMOS input stage switch circuit can also be implemented by a NMOS transistor.

[0034] Referring to Fig. 3(a) and Fig. 3(b), the PMOS input stage and the NMOS input stage both have the Ina signal and the Inb signal as input, their switch circuits both have Vbias as the enabling signal, and their output is the differential signal pair Outa and Outb. When Vbias is a second logic voltage, the third PMOS transistor is turned on and the third NMOS transistor is turned off, then the NMOS input stage is in an idle state, i.e., does not generate power consumption, whereas the PMOS input stage is in a working state and processes the LVDS signal; when Vbias is a first logic voltage, the third PMOS transistor is turned off and the third NMOS transistor is turned on, and then the PMOS input stage is in a working state and processes the LVDS signal whereas the NMOS input stage is in an idle state, i.e., does not generate power consumption.

[0035] Fig. 4 illustrates an implementation mode of a common mode voltage determination circuit and an input stage selection circuit according to one embodiment of the present invention. [0036] The common mode voltage determination circuit in Fig. 4 can be implemented by making simple modification to a termination resistor in the prior art. In other words, the common mode voltage determination circuit does not add too many devices to the LDVS receiver in the prior art. As shown in Fig. 4, the termination resistor in the prior art is changed into two serially connected resistors with the same resistance value, namely, a first resistor divider and a second resistor divider. The signal voltage at a fifth node where the first resistor divider is connected to the second resistor divider is the common mode voltage of the LDVS signal.

[0037] The reference voltage Vref in Fig. 4 can be implemented by a voltage division circuit between the power supply and the ground. For example, assume the power supply voltage is 3 V and the reference voltage Vref needs to be set as 1.0V, a third resistor divider and a fourth resistor divider are provided in series between the power supply and the ground, and a ratio of the resistance value of the third resistor divider to that of the fourth resistor divider is 2:1. The signal at the sixth node where the third resistor divider is connected to the fourth resistor divider is the reference voltage Vref of 1.0V.

[0038] The skilled in the art can appreciate that in order to allow the signal at the fifth node or sixth node to satisfy some properties, e.g., driving capability, signal stability or the like, an extra circuit such as a follower or an amplifier can be added upon outputting the signal at the fifth node or sixth node. Fig. 4 only illustrates the most fundamental implementation method.

[0039] The input stage selection circuit in Fig. 4 is a comparator which compares the LVDS common mode voltage and the reference voltage to output the enabling signal. As stated above, the common mode voltage range that can be processed by the NMOS input stage is close to the end of 2.4V, whereas the common mode voltage range that can be processed by the PMOS input stage is close to the end of 0V. Therefore, when the common mode voltage is higher than the reference voltage, the enabling signal output by the input stage selection circuit should enable the NMOS input stage to be in a working state and the PMOS input stage in an idle state; when the common mode voltage is lower than the reference voltage, the enabling signal output by the input stage selection circuit should enable the NMOS input stage to be in an idle state and the PMOS input stage in a working state.

[0040] According to one embodiment of the present invention, the comparator is a low frequency comparator. Although the LVDS signal has a very high data transmission rate, i.e., a signal switching frequency on the Ina and Inb is very high, the common mode voltage of a period of LVDS signal is relatively stable and is a low frequency signal. In general, the low-frequency comparator is simpler than the high-frequency comparator, so it occupies a smaller area on the chip and has a lower processing requirement. Besides, the power consumption of the low-frequency comparator is lower than the high-frequency comparator.

[0041 ] Although theoretically the common mode voltage of one section of LVDS signal should remain stable, existence of noise makes the common mode voltage change. This is likely to cause frequent switching of the enabling signal.

[0042] According to one embodiment of the present invention, the comparator is a comparator having hysteresis switching properties. In use of such comparator, only when a difference between the input common mode voltage and the reference voltage reaches a certain degree, the output enable voltage initiates a switching. In order to give a detailed depiction, assumption is made as below: when the common mode voltage is higher than the reference voltage, the enabling signal indicates the first logic voltage; when the common mode voltage is lower than the reference voltage, the enabling signal indicates the second logic voltage. A comparator with a Schmitt trigger is used. When the common mode voltage changes from a voltage higher than the reference signal to a voltage lower than the reference signal, the enabling signal does not certainly switch from the first logic voltage to the second logic voltage; only when an absolute value of the difference between the common mode voltage and the reference voltage is higher than a first threshold value, the enabling signal switches from the first logic voltage to the second logic voltage. Similarly, when the common mode voltage changes from a voltage lower than the reference signal to a voltage higher than the reference signal, the enabling signal does not certainly switch from the second logic voltage to the first logic voltage; only when the absolute value of the difference between the common mode voltage and the reference voltage is higher than a second threshold value, the enabling signal switches from the second logic voltage to the first logic voltage. As such, when the theoretical common mode voltage is higher than the reference voltage, even if a practical common mode voltage is made lower than the reference voltage due to influence of the noise, the enabling signal will not switch so long as the noise is not so large that the absolute value of the difference between the practical common mode voltage and the reference voltage is higher than the first threshold value. Likewise, when the theoretical common mode voltage is lower than the reference voltage, even if a practical common mode voltage is made higher than the reference voltage due to influence of the noise, the enabling signal will not switch so long as the noise is not so large that the absolute value of the difference between the practical common mode voltage and the reference voltage is larger than the second threshold value.

[0043] Usually the comparator with the hysteresis switching properties is implemented by adding a Schmitt trigger to an ordinary comparator. Those skilled in the art can readily envisage other modes to implement the comparator with the delay switch properties.

[0044] According to a further embodiment of the present invention, a low-pass Filter is provided between the Fifth node and the comparator. As stated above, the common mode voltage signal is a low-frequency signal, so the low-pass Filter can be used to retain the common mode voltage signal and eliminate noise. The implementation of the low-pass filter is of common knowledge in the art, and will not be discussed in detail here.

[0045] The arrangement of the reference voltage Vref, the First threshold value VthL and the second threshold VthH is discussed hereunder.

[0046] As stated above, the common mode voltage range that can be processed by the NMOS input stage is close to the end of 2.4V, whereas the common mode voltage range that can be processed by the PMOS input stage is close to the end of 0V. Specifically speaking, in the NMOS input stage and the PMOS input stage shown in Fig. 3(a) and Fig. 3(b), a lower limit of the common mode voltage that can be processed by the NMOS input stage is Vdd - (Vdsatpl + Vdsatp2 + Vthp), and an upper limit thereof is Vdd, wherein Vdd is the power supply voltage, Vdsatpl denotes a saturation voltage of the third NMOS transistor, Vdsapt2 denotes a saturation voltage of the First or second NMOS transistor, and Vthp is a threshold voltage of the first or second NMOS transistor. A lower limit of the common mode voltage that can be processed by the PMOS input stage is a ground voltage, and an upper limit thereof is (Vdsatnl + Vdsatn2 + Vthn), wherein the Vdsatnl denotes a saturation voltage of third PMOS transistor, Vdsatn2 denotes a saturation voltage of the first or second PMOS transistor, and Vthn is a threshold voltage of the first or second PMOS transistor.

[0047] Generally, the lower limit of the common mode voltage that can be processed by the NMOS input stage is lower than the upper limit of the common mode voltage that can be processed by the PMOS input stage. In other words, between the lower limit of the common mode voltage that can be processed by the NMOS input stage and the upper limit of the common mode voltage that can be processed by the PMOS input stage, anyone of the input stage can be allowed to be in a working state and the other input stage is in an idle state. Therefore, the reference voltage Vref can be set as any voltage value between the lower limit of the common mode voltage that can be processed by the NMOS input stage and the upper limit of the common mode voltage that can be processed by the PMOS input stage.

[0048] Further, as can be seen from the above analysis, when the common mode voltage changes from a voltage higher than the reference voltage to a voltage lower than the reference voltage and the absolute value of the difference between the common mode voltage and reference voltage is larger than the first threshold value, the enabling signal switches from the first logic voltage to the second logic voltage. Therefore, the voltage value obtained by subtracting the first threshold value from the Vref should be higher than the lower limit of the common mode voltage that can be processed by the NMOS input stage. Similarly, when the common mode voltage changes from a voltage lower than the reference voltage to a voltage higher than the reference voltage and the absolute value of the difference between the common mode voltage and reference voltage is larger than the second threshold value, the enabling signal switches from the second logic voltage to the first logic voltage. Therefore, the voltage value obtained by adding the second threshold value to the Vref should be lower than the upper limit of the common mode voltage that can be processed by the PMOS input stage.

[0049] Fig. 5 illustrates a flowchart of a method of receiving LVDS signal according to one embodiment of the present invention.

[0050] At step 501, a common mode voltage of a received LVDS signal is obtained.

[0051 ] At step 502, the common mode voltage is compared with a reference voltage.

[0052] At step 503, the NMOS input stage is allowed to be in a working state and the PMOS input stage in an idle state in response to the common mode voltage being higher than the reference voltage, and the PMOS input stage is allowed to be in a working state and the NMOS input stage in an idle state in response to the common mode voltage being lower than the reference voltage.

[0053] The LVDS signal is transmitted in a long distance, and its common mode voltage might jitter due to influence of noise. Hence, the magnitude relationship between the common mode voltage and the reference voltage needs to be avoided from frequently switching due to influence of the noise.

[0054] According to one embodiment of the present invention, it is not the case that once the magnitude relationship between the common mode voltage and the reference voltage changes, the switching of the input stage is triggered, but that the switching is triggered after the difference between the common mode voltage and the reference voltage reaches a certain degree. For example, the NMOS input stage is switched from the idle state to the working state and the PMOS input stage is switched from the working state to the idle state only when the common mode voltage changes from a voltage lower than the reference voltage to a voltage higher than the reference voltage, and the absolute value of the difference between the common mode voltage and the reference voltage is higher than the second threshold value. Similarly, the NMOS input stage is switched from the working state to the idle state and the PMOS input stage is switched from the idle state to the working state only when the common mode voltage changes from a voltage higher than the reference voltage to a voltage lower than the reference voltage, and the absolute value of the difference between the common mode voltage and the reference voltage is higher than the first threshold value.

[0055] According to an another embodiment of the present invention, after the common mode voltage is obtained, a signal indicative of the common mode voltage, after passing through the low-pass filter, can be compared with the reference voltage. On one hand, the common mode voltage itself is a low-frequency signal and can pass through the low-pass filter; on the other hand, noise is a wideband signal, and the low-frequency filter can filter away a high-frequency portion, thereby reducing the strength of the noise. As such, the influence of noise on the comparison results can be weakened.

[0056] It is found through experiments that the LVDS receiver according to one embodiment of the present invention, at a transmission rate of lGbps, can be adapted for various standard common mode voltages, and can operate normally at the worst process conditions. At different common mode voltages and under different process conditions, a maximum of a delay error of the output signal and input signal of the LVDS receiver according to the embodiment of the present invention is 38ps (picosecond), by far less than a data cycle of 1 nanosecond (ns). Besides, according to Fig. 6, at a transmission rate of lGbps, the LVDS receiver according to the embodiment of the present invention at most consumes a current of 1.2 mA at various LVDS common mode electrical levels, i.e., a point Ml in the figure. In contrast, at the same power supply voltage, the LVDS receiver having the rail-to-rail input stage at most consumes a current of 6.68 mA, i.e., a point M0 in the figure. As seen from the above, the power consumption of the LVDS receiver according to the embodiment of the present invention is substantially reduced. In Fig. 6, a horizontal ordinate denotes a common mode electrical level of the LVDS signal and a longitudinal ordinate denotes electrical current consumed by the LVDS receiver.

[0057] Although the system and method according to the present invention have been described in detail with reference to preferred embodiments, the present invention is not limited to this. A person of normal skill in the art can make various changes, alterations and modifications to the present invention under the teaching of the description without departing from the spirit and scope of the present invention. It should be understood that all such changes, alterations, and modifications still fall into the protection scope of the present invention. The protection scope of the present invention is defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A low- voltage differential signal LVDS receiver, comprising:

a first type of input stage and a second type of input stage respectively configured to convert an input LVDS signal into an internal differential signal;

a common mode voltage determination circuit configured to determine a common mode voltage of the input LVDS signal;

an input stage selection circuit configured to compare the common mode voltage with a reference voltage, and output an enabling signal according to comparison results, wherein when the common mode voltage is higher than the reference voltage, the enabling signal indicates a first logic voltage, and the first logic voltage puts the first type of input stage into a working state and the second type of input stage in an idle state, and wherein when the common mode voltage is lower than the reference voltage, the enabling signal indicates a second logic voltage, and the second logic voltage puts the second type of input stage into the working state and the first type of input stage in the idle state,

wherein the first type of input stage is one of an NMOS input stage and a PMOS input stage, and the second type of input stage is the other of the NMOS input stage and the PMOS input stage.

2. The LVDS receiver according to claim 1, wherein under the following conditions, the enabling signal switches from the first logic voltage to the second logic voltage:

the common mode voltage changes from a voltage higher than the reference voltage to a voltage lower than the reference voltage, and

an absolute value of a difference between the common mode voltage and the reference voltage is higher than a first threshold value.

3. The LVDS receiver according to claim 1, wherein under the following conditions, the enabling signal switches from the second logic voltage to the first logic voltage:

the common mode voltage changes from a voltage lower than the reference voltage to a voltage higher than the reference voltage, and

an absolute value of a difference between the common mode voltage and the reference voltage is higher than a second threshold value.

4. The LVDS receiver according to claim 2 or 3, wherein the input stage selection circuit is a comparator with a Schmitt trigger.

5. The LVDS receiver according to claim 1, wherein the input stage selection circuit is implemented by a low frequency comparator.

6. The LVDS receiver according to claim 1, wherein an output of the common mode voltage determination circuit is connected, via a low-pass filter, to an input of the input stage selection circuit.

7. The LVDS receiver according to claim 1, wherein a value of the reference voltage is higher than a lower limit of the common mode voltage that can be processed by the first type of input stage, and lower than an upper limit of the common mode voltage that can be processed by the second type of input stage.

8. The LVDS receiver according to claim 2, wherein a value obtained by subtracting the first threshold value from the reference voltage is higher than a lower limit of the common mode voltage that can be processed by the first type of input stage.

9. The LVDS receiver according to claim 3, wherein a value obtained by adding the second threshold value to the reference voltage is lower than an upper limit of the common mode voltage that can be processed by the second type of input stage.

10. A chip, comprising the LVDS receiver according to claims 1-9.

1 1. A method for receiving an LVDS signal, comprising:

obtaining a common mode voltage of a received LVDS signal;

comparing the common mode voltage with a reference voltage; and

putting a first type of input stage into a working state and a second type of input stage into an idle state in response to the common mode voltage being higher than the reference voltage, and putting the second type of input stage into the working state and the first type of input stage into the idle state in response to the common mode voltage being lower than the reference voltage,

12. The method according to claim 11, wherein putting a first type of input stage into a working state and a second type of input stage into an idle state in response to the common mode voltage being higher than the reference voltage, comprising:

in response to the common mode voltage changing from a voltage lower than the reference voltage to a voltage higher than the reference voltage, and an absolute value of a difference between the common mode voltage and the reference voltage being higher than a second threshold value, switching the first type of input stage from the idle state to the working state, and switching the second type of input stage from the working state to the idle state.

13. The method according to claim 1 1, wherein putting the second type of input stage into the working state and the first type of input stage into the idle state in response to the common mode voltage being lower than the reference voltage, comprising:

in response to the common mode voltage changing from a voltage higher than the reference voltage to a voltage lower than the reference voltage, and an absolute value of a difference between the common mode voltage and the reference voltage being higher than a first threshold value, switching the first type of input stage from the working state to the idle state, and switching the second type of input stage from the idle state to the working state.

14. The method according to claim 11, wherein comparing the common mode voltage with the reference voltage, comprising:

comparing a signal indicative of the common mode voltage with the reference voltage after passing the signal indicative of the common mode voltage through a low-pass filter.