Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/30—Coatings
  • H10F77/306—Coatings for devices having potential barriers
  • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
  • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F10/00—Individual photovoltaic cells, e.g. solar cells
  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
  • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
  • H10F10/148—Double-emitter photovoltaic cells, e.g. bifacial photovoltaic cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/121—The active layers comprising only Group IV materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/547—Monocrystalline silicon PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the present invention relates to photovoltaic devices, and in particular, a photovoltaic device structure with improved photovoltaic properties and a simplified method of manufacture.
• the conventional methods for manufacturing photovoltaic materials also require a multi-step process, or different processes, with each step possibly taking place at a different apparatus and at different times, and requiring its own management and resources.
• different doping processes are applied to manufacture different semiconductor wafers, and the wafers of different types are sealed together in a particular way to form a photovoltaic material.
• the purpose for the doping processes and assembly of the wafers is to create p-n junctions, or p-i-n junctions, in between wafers to achieve an overall photovoltaic effect in the assembled material.
• Each of such manufacturing stages incurs a cost. It is highly desirable to have a manufacturing process for photovoltaic material that reduces the number of necessary processes or steps to reduce costs.
• Preferred embodiments of the invention provide a novel method of manufacturing a new material with photovoltaic properties.
• Embodiments include processes for manufacturing using a heating process to create one or more photovoltaic structures on a semiconductor wafer, and provide the advantage of low manufacturing cost.
• Embodiments further include processes for reducing the resistivity of a surface opposite a high-resistivity surface on the semiconductor wafer.
• FIG. 1 is diagram illustrating a view of a cross section during a heating stage of the manufacturing process according to some embodiments of the invention.
• FIG. 2 is a diagram illustrating a view of a cross section of the photovoltaic material during one stage of the manufacturing process after the photovoltaic structures are formed, according to some embodiments of the invention.
• FIG. 3 is a diagram illustrating a view of a cross section during one stage of the manufacturing process after one of the photovoltaic structures is removed, according to some embodiments of the invention.
• FIG. 4 is a diagram illustrating a view of a cross section during one stage of the manufacturing process after formation of a silicide layer, according to some embodiments of the invention.
• FIG. 5 is a diagram illustrating a view of a cross section during one stage of the manufacturing process after ion-implantation and activation process, according to some embodiments of the invention.
• FIG. 6 is a diagram illustrating a view of a cross section during a heating stage of the manufacturing process of an n-on-n++-type semiconductor wafer, according to some embodiments of the invention.
• FIG. 7 is a diagram illustrating a view of a cross section during one stage of the manufacturing process after formation of a photovoltaic structure above an n++-type layer, according to some embodiments of the invention.
• FIG. 8 is a diagram illustrating two views of a cross section with an isolation layer before and after a heating stage of the manufacturing process according to some embodiments of the invention.
• FIG. 9 is a diagram illustrating a view of a cross section during a heating stage of the manufacturing process performed with a large wafer holding structure to prevent formation of a photovoltaic layer at the bottom surface, according to some embodiments of the invention.
• FIG. 10 is a diagram illustrating a view of a cross section during one stage of the manufacturing process after a heating stage, according to some embodiments of the invention.
• FIG. 11 is a diagram illustrating a view of a cross section of a photovoltaic material as assembled into a photovoltaic device according to some embodiments of the invention.
• FIG. 12 is a flow diagram illustrating an example of a process by which a photovoltaic material is manufactured from a semiconductor wafer and assembled into a photovoltaic device, according to some embodiments of the invention.
• FIG. 13 is a graph illustrating the relationship between the measured open circuit voltage and the heating temperature used to create the material shown in FIG. 3 according to some embodiments of the invention.
• a semiconductor wafer having a dopant element in the wafer is treated in a heating process to manufacture a material with photovoltaic properties.
• the heating process induces diffusion of the dopant element in the wafer, causing a change in the semiconductor resistivity.
• a photovoltaic structure forms at the surface of the semiconductor wafer.
• FIG. 1 is a diagrammatic view of a cross section of semiconductor wafer 10 on wafer holding member 12 during an initial heating stage of the manufacturing process according to embodiments of the invention.
• heat 14 is applied to the top and bottom of the wafer.
• threshold conditions including heating, photovoltaic high-resistivity layers are formed in each side of the wafer exposed to the heat source.
• semiconductor wafer 10 comprises a doped single-crystal silicon wafer, such as an n-type silicon wafer.
• the silicon wafer has a thickness of above 10 ⁇ . In a preferred embodiment, the silicon wafer has a thickness of 200 ⁇ .
• semiconductor wafer 10 comprises any one of Silicon (Si), Germanium (Ge), or any other group IV semiconductor. In some embodiments, semiconductor wafer 10 has a resistivity of 1 to 5 ⁇ -cm in the (100) face of crystal orientation.
• the dopant element comprises any one of Phosphorus (P), Nitrogen (N), Antimony (Sb), Arsenic (As) or any other element of group V.
• the phosphorus content in the silicon wafer is above 0.01 ppb.
• the phosphorus content is the minimum amount of dopant present in n-type silicon wafers as a result of standard n-type silicon wafer fabrication.
• phosphorus is added by methods such as ion implantation and chemical diffusion.
• wafer heating is performed in diverse methods, including but not limited to infrared heating, laser heating, and hot- wall furnace heating.
• heating methods for treating semiconductor wafer 10 affect photovoltaic performance of the photovoltaic cell constructed from treated semiconductor wafer 10.
• the cooling rate after the heating stage is a crucial factor to photovoltaic cell fabrication, whereas the heating rate is a less crucial factor to photovoltaic cell fabrication.
• maximum photovoltaic cell performance is obtained at heating temperatures above 1500 K, at heating times above 5 minutes, at approximately 1x10 " Pa.
• Table 1 provides a summary of parameters used in heating semiconductor wafer 10 according to embodiments of the invention.
• semiconductor wafer 10 transforms into a photovoltaic semiconductor material 11 that includes the layered structures as illustrated in the diagram in FIG. 2.
• the heating process results in the formation of photovoltaic structure 16, semiconductor bulk 18, and photovoltaic structure 20 within semiconductor 10 to form photovoltaic semiconductor material 11.
• Photovoltaic structures 16 and 20 both include at least a high-resistivity layer therein.
• the bottom surface of photovoltaic semiconductor wafer 11 is treated to reduce its resistivity before fabricating the material into a photovoltaic cell.
• Treatments include but are not limited to one or more of physical removal of the bottom surface layer, formation of silicide at the bottom surface, and ion implantation into the bottom surface layer. Such lowering of resistivity at a bottom surface produces a greater output from a photovoltaic cell fabricated from the photovoltaic semiconductor wafer 11.
• FIG. 3 is a diagram that illustrates photovoltaic semiconductor wafer 11 after heat treatment and removal according to preferred embodiments of the invention.
• the elimination of the photovoltaic structure is achieved by physical polishing of the wafer surface, by chemical etching, or by other polishing approaches.
• the resulting wafer structure 22 includes photovoltaic structure 16 and semiconductor bulk 18 as shown in FIG. 3.
• physical polishing is achieved by polishing with an abrasive grain that can polish a silicon substrate, such as a diamond paste, alumina, or silicon carbide.
• a silicon substrate such as a diamond paste, alumina, or silicon carbide.
• the heat processing conditions may affect the depth of the bottom high resistivity layer, the thickness of the removed layer varies.
• the bottom surface is polished to a depth of ⁇ .
• photovoltaic semiconductor wafer 11 is polished using chemical mechanical planarization (CMP) techniques.
• CMP chemical mechanical planarization
• a combination of physical polishing and CMP is used to remove material from the bottom surface of photovoltaic semiconductor wafer 11.
• the high -resistivity bottom surface of semiconductor 10 is removed by laser ablation using high-output beams including but not limited to YAG laser, excimer laser, argon ion laser, solid green laser, or electron beam laser, or by performing line scanning on the rear surface.
• the ablation is provided only for the center of the substrate to prevent failure or surface leakage of the semiconductor substrate caused by fragments created during the laser ablation that have scattered onto the photovoltaic power generation layer or onto the transparent conductive film on the top surface.
• a protective film such as polymide film is formed on the bottom surface before laser ablation, and removed by peeling and cleaning after laser ablation, to minimize scattered fragments.
• chemical etching is used to remove the bottom high- resistivity surface layer from photovoltaic semiconductor wafer 11.
• a protective film for silicon such as a SiN film, is formed at the top surface to mask the top surface from contact with an etching chemical.
• the bottom side of photovoltaic semiconductor wafer 11 is dipped into the etching chemical for etching the bottom surface to a depth of approximately 10 ⁇ .
• etching chemicals used include but are not limited to KOH, NaOH, mixed solution of nitric acid and hydrofluoric acid, or an etching solution in which these materials are diluted with acetic acid and water. Alternatively, dry etching may be used.
• the protective film is removed to expose the top surface of photovoltaic semiconductor wafer 11. For example, phosphoric acid is used to remove the SiN film.
• treatments of the bottom surface for lowering the resistivity of the bottom surface includes formation of silicide on the rear surface of photovoltaic semiconductor wafer 11 after the heating process.
• FIG. 4 illustrates one example of such wafer structure 24, comprising photovoltaic structure 16, semiconductor bulk 18, photovoltaic structure 20 and silicide layer 26.
• a preliminary metal material is formed first on the bottom surface.
• metals include but are not limited to nickel, cobalt, magnesium, lead, platinum, iron, hafnium, rhodium, manganese, titan, zirconium, titanium, chromium, molybdenum, and vanadium.
• Formation of the metal material onto the bottom surface may use sputtering methods including metalorganic chemical vapour deposition (MOCVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or other coating method.
• MOCVD metalorganic chemical vapour deposition
• MBE molecular beam epitaxy
• PLD pulsed laser deposition
• heat is applied to the surface to form silicide. Heating temperatures vary depending on the material used. For example, the formation of Co onto a surface of silicon requires heat processing of 620K or higher to form silicide.
• the thickness of silicide necessary to lower the resistivity of the high- resistivity layer at bottom surface depends on the thickness of the high-resistivity layer.
• An example range of silicide formation for layer 26 is between approximately 20 nm to 10 ⁇ .
• treatments of the bottom surface for lowering the resistivity of the bottom surface includes ion implantation at the bottom surface to convert a portion of the material into an n++-type semiconductor.
• FIG. 5 illustrates the resultant ion-implanted photovoltaic material 28 transformed from photovoltaic semiconductor material 11, according to some embodiments of the invention.
• ion implantation is performed at the bottom surface to increase the concentration of the dopant in the material.
• photovoltaic semiconductor material 11 is an n-type substrate doped with phosphorus
• ion implantation of phosphorus is preferred.
• an arsenic dopant is preferred. Any range of dose amount and implantation energy may be used to achieve a desired concentration. In some embodiments, the desired concentration
• phosphorus doping is completed by a diffusion process in a diffusion furnace instead of by ion implantation.
• ion implantation is performed at a high energy level of 100 keV to 300 keV, followed by additional implantation at a low energy level of approximately 5 keV to 50 keV.
• dopant activation processing for activation is performed at room temperature, and activation annealing is performed, for example, in a diffusion furnace.
• the resultant photovoltaic material 28 includes photovoltaic structure 18, semiconductor bulk 16, and at least photovoltaic material 20 transformed into ion- implanted layer 30.
• a preventative process may be performed on semiconductor 10 before the heating process reduces the resistivity of the bottom surface by preventing the formation of at least one high-resistivity layer, for example, in photovoltaic structure 20.
• Preventative processes performed before heating include but are not limited to using a particular type of semiconductor wafer, such as an n-on-n+ - silicon substrate, that prevents formation a bottom high-resistivity layer upon heating; forming a protective film to prevent a bottom surface from forming into a high-resistivity layer upon heating; and preventing one surface from being heated to a sufficient temperature by concentrating heating to one surface or by placing semiconductor 10 on a heat reservoir to shield against the heat source.
• a particular type of semiconductor wafer such as an n-on-n+ - silicon substrate
• FIG. 6 illustrates the heating stage of an n-on-n++ silicon wafer 32 as the semiconductor substrate being transformed into a photovoltaic material.
• an n-on-n++ silicon substrate may be created by first forming an n++-type silicon substrate, and then forming an n-type silicon over the n++-type silicon.
• the n++-type silicon substrate is created by a Czochralski (CZ) process, and has a resistivity of approximately 0.001 ⁇ -cm.
• the n-type silicon formed by epitaxial growth over the n++-type silicon has a resistivity of approximately 5 ⁇ -cm and has a thickness of approximately 5 ⁇ .
• n++-type silicon is used in this description, an n+-type semiconductor wafer or a substrate having further lower resistivity may be used at the bottom layer without departing from the spirit of the invention.
• the heat process is applied to such n-on-n++-type silicon substrate, as shown in FIG. 6, under the conditions specified in Table 1, to create a photovoltaic generation layer 16 at the top surface without creating a photovoltaic layer at the bottom surface.
• the resultant photovoltaic material 34 comprising a photovoltaic structure 16 and a n++-type bulk 33 is shown in FIG. 7.
• an isolation layer or protective film 36 is formed on the bottom surface of semiconductor 10 before the heating process to prevent the high-resistivity layer from forming there during the heating process.
• the protective film 36 may comprise a SiN film formed at a thickness of approximately 20 nm by sputtering. After the heating step, high-resistivity photovoltaic structure 16 is formed only at the top portion of semiconductor wafer 10, as shown in the bottom view 802 of FIG. 8. The isolation layer or protective film 36 is removed before performing the next steps for completing the solar cell.
• the protective film is SiN film
• other materials may be used without departing from the spirit of the invention, including but not limited to: silicon- series non-organic films such as SiC, SiC"2, SiON, and SiOC, metal, metal alloy, organic material, and any material having a heat resistance equal to or higher than a temperature at which the photovoltaic layer is formed by the heating process described with reference to FIG. 1 and Table 1.
• the layer is not removed before forming the photovoltaic material into a photovoltaic cell because it does not negatively affect photovoltaic performance.
• isolation layer 36 forms a buffer to create ohmic contact between semiconductor bulk 18 and a bottom electrode. Details of the method for using SiC to create ohmic contact between semiconductor bulk 18 and a bottom electrode is further described in copending U.S. Patent Application No. 13/—, filed— , which claims priority to U.S. Provisional Application No. 61/655,449, filed June 4, 2012 (Attorney Docket No. 44671-035 (P4)).
• a preventative process includes placing semiconductor wafer 10 on a wafer holding structure or furnace base 39 comprising a cooling material, a heat dissipating material, or a heat reservoir for the heating process to prevent the bottom surface from being heated to the threshold temperature for generating a photovoltaic layer, such as the process and conditions described with reference to FIG. 1 and Table 1 above.
• the wafer holding structure 39 maintains the bottom surface at a temperature of approximately HOOK, the top surface reaches a desired temperature of approximately 1500K.
• semiconductor wafer 10 is placed in direct contact with a wafer holding structure 39 configured with tungsten alloy.
• the inside of the wafer holding structure is further cooled by water.
• the wafer holding structure 39 is configured with a material or a shape providing a large heat capacity able to reduce the temperature of the bottom surface of semiconductor 10 without water cooling.
• Other materials having a relatively large mass to function as a heat reservoir and as a shield for the bottom portion and surface against the heat source may be used without departing from the spirit of the invention.
• other high-melting-point metals may be used including molybdenum, tantalum, and niobium, and non-metal material such as quartz, may be used.
• the assembly of a large mass wafer holder 39 in contact with semiconductor wafer 10 is introduced into a pre -heated furnace.
• photovoltaic structure 40 comprising a top layer affected by the heat treatment and a bottom layer unaffected by the heat treatment as shown in FIG. 10 is formed.
• a reduction in top surface resistivity in wafer structure 22 is desirable to optimize photovoltaic performance.
• cell efficiency is high when the junction between the photovoltaic structure 16 and semiconductor bulk 18 is positioned relatively close to the wafer surface, or within 0.5 and 1.5 microns. When the junction is too deep into the bulk, or above 2 microns, cell efficiency starts to degrade due to the decreased penetration of light into the wafer.
• Treatment temperature, time, and treatment pressure are adjustable for achieving a desired position of the junction.
• FIG. 11 illustrates an example of using a photovoltaic material 42 produced as described in any of the examples above into a photovoltaic cell.
• a completed cell 44 includes a top electrode 46 placed over the top surface of photovoltaic material 42.
• any transparent conductive oxides (TCO), such as indium- tin- oxide (ITO), ZnO, NiO, or any other type of transparent electrodes can be used as a top electrode.
• Semi transparent or translucent electrodes can also be used depending on the efficiency goals and desired cost of the photovoltaic cell.
• An optional anti-reflecting coating may be placed on the top surface (on top of TCO layer) in order to improve light absorption and therefore cell performance.
• the completed cell 44 includes bottom electrode 48.
• an aluminum layer is preferred for bottom electrode 48. Thickness of the bottom electrode may vary between 1 and 800 microns, typically about 400 microns.
• a bottom aluminum electrode may be fabricated by physical vapor deposition (sputtering), screen printing, ink- jet printing or other standard printing or metal deposition techniques. Bottom electrode 48 may be placed directly over the bottom surface of photovoltaic material 42 or over a buffer in between, as previously described above with reference to related U.S. patent application 13/—.
• a photovoltaic material formed using the heating process described above with reference to FIGS. 1, 6, 8, and 9. may produce crystal defects that negatively impact the photovoltaic performance of a photovoltaic cell made from the photovoltaic material.
• a lower-temperature heating process, applied after the formation of the respective photovoltaic materials described above, may be used to reduce crystalline defects to increase photoelectric output.
• Temperature ranges for the second heat process includes temperatures higher than 650 K and lower than 1000 K, according to some embodiments of the invention. In a particular example, a heat having temperature of 870 K is applied to the photovoltaic materials for one hour in inert gas atmosphere.
• This lower- temperature heat process may be performed before or after the assembly of the photovoltaic material into a photovoltaic cell. Performing the lower-temperature heating after the assembly of the photovoltaic cell provides the advantage of removing any binder from the aluminum bottom electrode by the second heating.
• step 1202 wafer cleaning is performed.
• silicon wafers are cleaned by dipping the wafers into a solution of hydrofluoric acid, followed by water cleaning and air drying. This process mainly targets the removal of the natural oxide film formed on the wafer surface.
• step 1204 wafer heating is performed. Heat sources are applied to the top and the bottom of the wafer under the conditions described in Table 1 above.
• step 1206 process for lowering the resistivity of the bottom layer is performed. Processes for lowering resistivity of the bottom layer include but are not limited to physical removal of the bottom surface layer, formation of silicide at the bottom surface, and ion implantation into the bottom surface layer to convert a portion of the material into an n++-type semiconductor. In some embodiments, step 1206 is performed prior to step 1204.
• Processes for lowering resistivity of the bottom layer prior to a heating step include but are not limited to using a particular type of semiconductor wafer, such as an n-on-n++ silicon substrate, that prevents formation a bottom high-resistivity layer upon heating; forming a protective film to prevent a bottom surface from forming into a high-resistivity layer upon heating; and preventing one surface from being heated to a sufficient temperature by concentrating heating to one surface or by placing semiconductor on a heat reservoir to shield against the heat source.
• a particular type of semiconductor wafer such as an n-on-n++ silicon substrate
• a top electrode is placed over the photovoltaic structure 16 of the wafer.
• any transparent conductive oxides such as indium- tin- oxide (ITO), ZnO, NiO, or any other type of transparent electrodes can be used as a top electrode.
• Semi transparent or translucent electrodes can also be used depending on the efficiency goals and desired cost of the photovoltaic cell.
• an optional anti-reflecting coating may be placed on the top surface (on top of TCO layer) in order to improve light absorption and therefore cell performance.
• bottom electrode placement of bottom electrode occurs.
• an aluminum layer is preferred for the bottom electrode. Thickness of the bottom electrode may vary between 1 and 800 microns, typically about 400 microns.
• a bottom aluminum electrode may be fabricated by physical vapor deposition (sputtering), screen printing, ink- jet printing or other standard printing or metal deposition techniques.
• cell testing is optionally performed to verify the photovoltaic device and to test performance.
• FIG. 13 is a graph that shows the measured Voc for a particular heating temperature used to create a photovoltaic wafer structure according to the techniques discussed above. Improved photovoltaic cell performance is shown for heating temperatures above 1350K. In particular, the Voc nearly doubles between 1350K and the highest temperature shown on the graph.

Landscapes

• Photovoltaic Devices (AREA)

Priority Applications (2)

Applications Claiming Priority (26)

Publications (1)

Family

ID=49301004

Family Applications (1)

Country Status (1)

Citations (12)

• 2013
  • 2013-04-02 WO PCT/US2013/035043 patent/WO2013152054A1/fr not_active Ceased

Patent Citations (12)

Similar Documents

Legal Events