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WO2013048619A1 - Power line communications transmitter/receiver - Google Patents

Power line communications transmitter/receiver Download PDF

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Publication number
WO2013048619A1
WO2013048619A1 PCT/US2012/049222 US2012049222W WO2013048619A1 WO 2013048619 A1 WO2013048619 A1 WO 2013048619A1 US 2012049222 W US2012049222 W US 2012049222W WO 2013048619 A1 WO2013048619 A1 WO 2013048619A1
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WO
WIPO (PCT)
Prior art keywords
data
basedata
transmitter
ifft
repetition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2012/049222
Other languages
French (fr)
Inventor
Handa Chen
Eiji Baba
Rui Zhang
Hung Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MegaChips Corp
Greenvity Communications Inc
Original Assignee
MegaChips Corp
Greenvity Communications Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MegaChips Corp, Greenvity Communications Inc filed Critical MegaChips Corp
Publication of WO2013048619A1 publication Critical patent/WO2013048619A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0071Use of interleaving
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041Arrangements at the transmitter end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/08Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0061Error detection codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/02Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/04Arrangements for detecting or preventing errors in the information received by diversity reception using frequency diversity

Definitions

  • At least one embodiment of the present invention pertains to power line communication, and more particularly, to a power line communications transmitter and receiver.
  • a smart grid is a complex electricity network that covers electricity delivery and information exchange from energy suppliers to sub-stations, homes/buildings, and vice versa.
  • a local area network e.g., a home area network (HAN) connects or couples smart devices with a utility gateway (e.g., smart meter) or a service provider gateway (e.g., a router or a set-top box) and is quite important for the smart grid.
  • a utility gateway e.g., smart meter
  • a service provider gateway e.g., a router or a set-top box
  • ICT communication technology
  • wireless communications suffer intolerable attenuation of signal intensity caused by distances or impenetrable obstacles such as concrete walls. Relays have been attempted in the smart grid but are not really satisfactory because the relays themselves are also subject to the same attenuation. In addition, as the relays have to be awake most of the time and are usually powered by batteries, their battery life will be short.
  • a new transmitter and receiver may be required with increased robustness with decreased power consumption.
  • a transmitter comprises an interface configured to receive data; a scrambler configured to whiten the payload portion of received data; a CRC encoder configured to protect the PHR portion of received data, a convolutional encoder configured to provide error correction encoding to the whitened payload and CRC protected PHR data; a repetition interleaver logic configured to create diversity in the data; a mapping logic to map the diversified binary data to complex subcarriers to be IFFT; adding Gl logic configured to add a guard interval to the IFFTed symbol; preamble data logic configured to add preambles to the symbol sequence which consists of several IFFT symbols to form a frame or packet to be transmitted; and a DAC configured to convert the digital packet to an analog signal.
  • a method comprises: receiving data; whitening the payload portion; CRC protecting the PHR portion of the received data; convolutional error correction encoding the whitened payload data and the CRC protected PHR; creating diversity in the data; mapping the diversified data to subcarriers; adding a guard interval to the IFFT symbol; adding preambles to the symbol sequence to form a frame or packet; and converting the digital packet to an analog signal.
  • Figure 1 is a block diagram illustrating a transmitter.
  • Figure 2 is a block diagram illustrating a receiver.
  • Figure 3 is a diagram illustrating a frame format.
  • Figure 4 is the simulated narrow band PLC noise waveform.
  • Figure 5 is a chart illustrating simulation results.
  • Figure 6 is a flowchart illustrating a transmission technique according to an embodiment.
  • Figure 1 is a block diagram illustrating a transmitter 100.
  • Quadrature Phase Shift Keying (QPSK) Modulation QPSK Modulation
  • FEC Forward Error Correction
  • Convolutional code of rate 1 ⁇ 2, repetition interleaver: x2 / x4 (normal/robust); data rate: 136 / 68/ kbps (normal/robust); and a 10bit Analog-to-Digital Converter (ADC) and a 10bit Digital-to-Analog Converter (DAC).
  • ADC Analog-to-Digital Converter
  • DAC Digital-to-Analog Converter
  • a MUX 120 a convolutional encoder 125, a bit interleaver logic 130, a repetition circular interleaver logic 135, a mapping (QPSK) logic 140, an Inverse Fast Fourier Transform (IFFT) 145, an Adding Guard Interval logic (Gl) 150, preamble data logic 150, a MUX 160 and a digital to analog converter 165 each coupled to the next in the order recited except for the logic 155 which is only coupled to the MUX 160.
  • QPSK mapping
  • IFFT Inverse Fast Fourier Transform
  • Gl Guard Interval logic
  • the interface 1 10 receives a digital signal to be transmitted and can be communicatively coupled to a LED Controller/Driver through an AFE in one embodiment.
  • the scrambler 1 15 whitens payload data of the digital signal, the CRC encoder adds error check bits to the PHY header (PHR), and the MUX 120 combines the PHR with the whitened payload.
  • the convolutional encoder 125 provides for error correction encoding with code rate of 1/2 followed by a repetition interleaver.
  • the repetition and interleaving is more effective and less cost for short packet data than Reed-Solomon encoder, thus a Reed-Solomon encoder is not needed and can reduce cost.
  • the bit interleaver 130 and repetition interleaver logic 135, described further below, create diversity by sending multiple copies of data for robustness.
  • the mapping logic 140 maps data to subcarriers as will be described further below.
  • the IFFT 145 is 128p for reducing packet length. Shorter packet size enables sending data during the zero-cross period in one cycle of AC current to avoid large peak noise.
  • the Adding Gl logic 150 adds guard interval while the preamble data logic 155 adds known data for detection, synchronization and channel equalization.
  • the preamble 155 has low Peak-to-Average Power Ratio (PAPR) suitable for automatic gain control (AGC) and is symmetrical and periodic for easier synchronization and will discussed in further detail below.
  • PAPR Peak-to-Average Power Ratio
  • AGC automatic gain control
  • the MUX 160 combines data from the Adding Gl logic 150 and the preamble data 150, which is then converted to analog for transmission by the DAC 165 to an AFE 170.
  • the mapping logic 140 maps data to subcarriers as shown in Table 1 below. Because the subcarrier spacing is 9.375kHz, the subcarrier interval of
  • tone#1 1 ⁇ tone#42 are just mapped to 103.125 ⁇ 393.75kHz.
  • repetition_x2 [basedata; circshift(basedata, 8)];
  • the output from repetition interleaver for x4 is
  • repetition_x4 [basedata; circshift(basedata,8); circshift(basedata, 8 * 2-2);
  • 'circshift' means circular shift, which shifts the basedata circularly left or right.
  • FIG. 2 is a block diagram illustrating a receiver 200, which is the inverse of the transmitter. Accordingly, the components of the receiver 200 will not be described in detail to avoid repetition.
  • a Viterbi decoder 275 is the inverse of the convolutional encoder 125.
  • FIG. 3 is a diagram illustrating a frame format 300.
  • a data frame comprises a preamble (7 symbols in one embodiment), a PHR(4 symbols) (PHY header)and several payload symbols (fixed 8 symbols for normal mode and 16 symbols for robust mode.).
  • the command frame comprises a preamble (7 symbols) and a PHR.
  • the preamble comprises short training fields (SFT) and long training fields (LTF) without guard intervals.
  • the PHR and data include guard intervals.
  • the lengths of a frame or a packet are fixed to 3776, 2624 and 1472 samples for data frame of repetition 4, repetition 2 and command frame respectively.
  • the preamble is composed of 4 STF and 3 LTF.
  • STF is periodic in time domain suitable for synchronization.
  • LTF is the real part of the IFFT of a Pseudo-Random Binary Sequence (PRBS) used for channel estimation and FFT window location adjustment.
  • PRBS Pseudo-Random Binary Sequence
  • the time domain STF and LTF are obtained as follows:
  • Figure 4 is the narrow band PLC channel noise modeled by Masaaki Katayama et al.
  • the mean power of the narrow band PLC noise is calculated over 24000 samples corresponding to 20ms, and is set to -8dB. Setting the narrow band PLC noise as a floor noise, the PER performance is confirmed by placing the packet (robust mode, 3.1 ms) at the zero-crossing position and peak position respectively.
  • Figure 5 shows the PER comparison for packets transmission at a different timing.
  • the local mean power at the zero-crossing position is less than that at the peak position, and thus the PER performance of the packets at the zero-crossing position is better than those at the peak position. If the data packet is short enough to be transmitted within the silent interval; it will be less damaged by the peak noise.
  • Figure 6 is a flowchart illustrating a transmission technique 600 according to an embodiment.
  • data to transmit is received (610) by the MAC/PHY interface 100.
  • the received data is then whitened (620) by the scrambler 1 15.
  • the whitened data is then convolutionally encoded (630).
  • the bit interleaver 130 and repetition logic 135 then create (640) diversity by sending multiple copies of the data for robustness as described above.
  • the mapping logic 140 maps (650) the data to subcarriers per Table I.
  • IFFT logic 145 then performs (660) an inverse fast Fourier transform.
  • the Adding Gl logic 150 and Preamble Data logic 155 then add (670) a Gl and preamble data (Tables II and III) respectively.
  • the DAC 165 then converts (680) the data to analog for transmission and the technique 600 ends.
  • ASICs application-specific integrated circuits
  • PLDs programmable logic devices
  • FPGAs field-programmable gate arrays
  • Software or firmware to implement the techniques introduced here may be stored on a machine-readable storage medium and may be executed by one or more general-purpose or special-purpose programmable microprocessors.
  • machine-readable medium includes any mechanism that can store information in a form accessible by a machine (a machine may be, for example, a computer, network device, cellular phone, personal digital assistant (PDA), manufacturing tool, any device with one or more processors, etc.).
  • a machine-accessible medium includes recordable/non-recordable media (e.g., read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; etc.), etc.
  • logic means: a) special-purpose hardwired circuitry, such as one or more application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), or other similar device(s); b) programmable circuitry programmed with software and/or firmware, such as one or more programmed general-purpose microprocessors, digital signal processors (DSPs) and/or microcontrollers, or other similar device(s); or c) a combination of the forms mentioned in a) and b).
  • ASICs application-specific integrated circuits
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • firmware such as one or more programmed general-purpose microprocessors, digital signal processors (DSPs) and/or microcontrollers, or other similar device(s); or c) a combination of the forms mentioned in a) and b).

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

A transmitter comprises an interface configured to receive data; a scrambler configured to whiten the received data; a convolutional encoder configured to provide error correction for the whitened data; a repetition interleaver logic configured to create diversity in the data; a mapping logic to map the diversified data to subcarriers; adding GI logic configured to add a guard interval to the IFFT symbol; preamble data logic configured to add preambles to the IFFT symbols to construct a transmitted frame; and a DAC configured to convert the frames to an analog signal.

Description

POWER LINE COMMUNICATIONS TRANSMITTER/RECEIVER
PRIORITY CLAIM
This application claims priority to and incorporates by reference U.S. Patent Application No. 61/541 ,073 filed September 29, 201 1 .
FIELD OF THE INVENTION
At least one embodiment of the present invention pertains to power line communication, and more particularly, to a power line communications transmitter and receiver.
BACKGROUND
A smart grid is a complex electricity network that covers electricity delivery and information exchange from energy suppliers to sub-stations, homes/buildings, and vice versa. A local area network (LAN), e.g., a home area network (HAN) connects or couples smart devices with a utility gateway (e.g., smart meter) or a service provider gateway (e.g., a router or a set-top box) and is quite important for the smart grid. In a conventional local area network, electric vehicles, air conditioners, experimental facilities or any other smart devices can be built with either wireless or wired information communication technologies (also referred to as communication technology or ICT).
In some situations, wireless communications suffer intolerable attenuation of signal intensity caused by distances or impenetrable obstacles such as concrete walls. Relays have been attempted in the smart grid but are not really satisfactory because the relays themselves are also subject to the same attenuation. In addition, as the relays have to be awake most of the time and are usually powered by batteries, their battery life will be short.
Accordingly, a new transmitter and receiver may be required with increased robustness with decreased power consumption.
SUMMARY
This summary is provided to introduce in a simplified form certain concepts that are further described in the Detailed Description below and the drawings. This summary is not intended to identify essential features of the claimed subject matter or to limit the scope of the claimed subject matter. In an embodiment, a transmitter comprises an interface configured to receive data; a scrambler configured to whiten the payload portion of received data; a CRC encoder configured to protect the PHR portion of received data, a convolutional encoder configured to provide error correction encoding to the whitened payload and CRC protected PHR data; a repetition interleaver logic configured to create diversity in the data; a mapping logic to map the diversified binary data to complex subcarriers to be IFFT; adding Gl logic configured to add a guard interval to the IFFTed symbol; preamble data logic configured to add preambles to the symbol sequence which consists of several IFFT symbols to form a frame or packet to be transmitted; and a DAC configured to convert the digital packet to an analog signal.
In an embodiment, a method, comprises: receiving data; whitening the payload portion; CRC protecting the PHR portion of the received data; convolutional error correction encoding the whitened payload data and the CRC protected PHR; creating diversity in the data; mapping the diversified data to subcarriers; adding a guard interval to the IFFT symbol; adding preambles to the symbol sequence to form a frame or packet; and converting the digital packet to an analog signal.
Other aspects of the technique will be apparent from the accompanying figures and detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
One or more embodiments of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.
Figure 1 is a block diagram illustrating a transmitter.
Figure 2 is a block diagram illustrating a receiver.
Figure 3 is a diagram illustrating a frame format.
Figure 4 is the simulated narrow band PLC noise waveform.
Figure 5 is a chart illustrating simulation results.
Figure 6 is a flowchart illustrating a transmission technique according to an embodiment.
DETAILED DESCRIPTION
References in this description to "an embodiment", "one embodiment", or the like, mean that the particular feature, function, structure or characteristic being described is included in at least one embodiment of the present invention.
Occurrences of such phrases in this specification do not necessarily all refer to the same embodiment. On the other hand, such references are not necessarily mutually exclusive either.
Figure 1 is a block diagram illustrating a transmitter 100. The transmitter and receiver 200 (Figure 2) has a signal bandwidth of 300KHz (100kHz~400kHz); an ADC sampling rate of 1 .2 MHz; a FFT size of 128pt FFT of complex input; 32 active subcarriers; subcarrier spacing of 9.375 KHz; FFT symbol duration of 106.66667 s; Guard Interval (Gl) of 16 samples; preamble of 4 STF + 3 LTF = 7 symbols;
Quadrature Phase Shift Keying (QPSK) Modulation; Forward Error Correction (FEC) using a Convolutional code of rate ½, repetition interleaver: x2 / x4 (normal/robust); data rate: 136 / 68/ kbps (normal/robust); and a 10bit Analog-to-Digital Converter (ADC) and a 10bit Digital-to-Analog Converter (DAC).
The transmitter 100 includes a MAC/PHY interface 1 10, a scrambler using PN9 sequence 1 14, a CRC encoder 1 17 using the polynomial G8(x) = χΛ8 + χΛ2 + x + 1 . a MUX 120, a convolutional encoder 125, a bit interleaver logic 130, a repetition circular interleaver logic 135, a mapping (QPSK) logic 140, an Inverse Fast Fourier Transform (IFFT) 145, an Adding Guard Interval logic (Gl) 150, preamble data logic 150, a MUX 160 and a digital to analog converter 165 each coupled to the next in the order recited except for the logic 155 which is only coupled to the MUX 160.
The interface 1 10 receives a digital signal to be transmitted and can be communicatively coupled to a LED Controller/Driver through an AFE in one embodiment. The scrambler 1 15 whitens payload data of the digital signal, the CRC encoder adds error check bits to the PHY header (PHR), and the MUX 120 combines the PHR with the whitened payload. The convolutional encoder 125 provides for error correction encoding with code rate of 1/2 followed by a repetition interleaver.
According to our simulations, the repetition and interleaving is more effective and less cost for short packet data than Reed-Solomon encoder, thus a Reed-Solomon encoder is not needed and can reduce cost. The bit interleaver 130 and repetition interleaver logic 135, described further below, create diversity by sending multiple copies of data for robustness. The mapping logic 140 maps data to subcarriers as will be described further below. The IFFT 145 is 128p for reducing packet length. Shorter packet size enables sending data during the zero-cross period in one cycle of AC current to avoid large peak noise.
The Adding Gl logic 150 adds guard interval while the preamble data logic 155 adds known data for detection, synchronization and channel equalization. The preamble 155 has low Peak-to-Average Power Ratio (PAPR) suitable for automatic gain control (AGC) and is symmetrical and periodic for easier synchronization and will discussed in further detail below. The MUX 160 combines data from the Adding Gl logic 150 and the preamble data 150, which is then converted to analog for transmission by the DAC 165 to an AFE 170.
The mapping logic 140 maps data to subcarriers as shown in Table 1 below. Because the subcarrier spacing is 9.375kHz, the subcarrier interval of
tone#1 1 ~tone#42 are just mapped to 103.125~393.75kHz.
syb¾arn¾r ats&ig for data
Figure imgf000007_0001
Table 1
Supposing the output data from the bit interleaver 130 is 'basedata',
Then the output from repetition interleaver logic 135 for x2 is
repetition_x2=[basedata; circshift(basedata, 8)];
The output from repetition interleaver for x4 is
repetition_x4=[basedata; circshift(basedata,8); circshift(basedata, 8*2-2);
circshift(basedata, 8*3+2)].
'circshift' means circular shift, which shifts the basedata circularly left or right.
Figure 2 is a block diagram illustrating a receiver 200, which is the inverse of the transmitter. Accordingly, the components of the receiver 200 will not be described in detail to avoid repetition. A Viterbi decoder 275 is the inverse of the convolutional encoder 125.
Figure 3 is a diagram illustrating a frame format 300. In an embodiment of the invention, there are two types of frame in embodiments of the invention, one is for data and another is for commands including beacon and acknowledgement. A data frame comprises a preamble (7 symbols in one embodiment), a PHR(4 symbols) (PHY header)and several payload symbols (fixed 8 symbols for normal mode and 16 symbols for robust mode.). The command frame comprises a preamble (7 symbols) and a PHR. As can be seen in Figure 3, the preamble comprises short training fields (SFT) and long training fields (LTF) without guard intervals. Further, the PHR and data include guard intervals. The lengths of a frame or a packet are fixed to 3776, 2624 and 1472 samples for data frame of repetition 4, repetition 2 and command frame respectively.
In an embodiment, the preamble is composed of 4 STF and 3 LTF. STF is periodic in time domain suitable for synchronization. LTF is the real part of the IFFT of a Pseudo-Random Binary Sequence (PRBS) used for channel estimation and FFT window location adjustment.
The time domain STF and LTF are obtained as follows:
STFJime = Real(IFFT(STF_freq))
LTFJime = Real(IFFT(LTF_freq))
The frequency domain representation of STF and LTF are shown in following tables 2 and 3.
Figure imgf000009_0001
Table 2
IFrg€Kigft¾¥ domain r«pr«sgntatfor¾ of LTF
Figure imgf000010_0001
Table 3
Figure 4 is the narrow band PLC channel noise modeled by Masaaki Katayama et al. The mean power of the narrow band PLC noise is calculated over 24000 samples corresponding to 20ms, and is set to -8dB. Setting the narrow band PLC noise as a floor noise, the PER performance is confirmed by placing the packet (robust mode, 3.1 ms) at the zero-crossing position and peak position respectively.
Figure 5 shows the PER comparison for packets transmission at a different timing. For PLC noise with a mean power of -8dB over 20ms, the local mean power at the zero-crossing position is less than that at the peak position, and thus the PER performance of the packets at the zero-crossing position is better than those at the peak position. If the data packet is short enough to be transmitted within the silent interval; it will be less damaged by the peak noise.
Figure 6 is a flowchart illustrating a transmission technique 600 according to an embodiment. First, data to transmit is received (610) by the MAC/PHY interface 100. The received data is then whitened (620) by the scrambler 1 15. The whitened data is then convolutionally encoded (630). The bit interleaver 130 and repetition logic 135 then create (640) diversity by sending multiple copies of the data for robustness as described above. The mapping logic 140 then maps (650) the data to subcarriers per Table I. IFFT logic 145 then performs (660) an inverse fast Fourier transform. The Adding Gl logic 150 and Preamble Data logic 155 then add (670) a Gl and preamble data (Tables II and III) respectively. The DAC 165 then converts (680) the data to analog for transmission and the technique 600 ends.
The techniques introduced above can be implemented by programmable circuitry programmed/configured by software and/or firmware, or entirely by special-purpose circuitry, or by a combination of such forms. Such special-purpose circuitry (if any) can be in the form of, for example, one or more application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), etc.
Software or firmware to implement the techniques introduced here may be stored on a machine-readable storage medium and may be executed by one or more general-purpose or special-purpose programmable microprocessors. A
"machine-readable medium", as the term is used herein, includes any mechanism that can store information in a form accessible by a machine (a machine may be, for example, a computer, network device, cellular phone, personal digital assistant (PDA), manufacturing tool, any device with one or more processors, etc.). For example, a machine-accessible medium includes recordable/non-recordable media (e.g., read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; etc.), etc.
The term "logic", as used herein, means: a) special-purpose hardwired circuitry, such as one or more application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), or other similar device(s); b) programmable circuitry programmed with software and/or firmware, such as one or more programmed general-purpose microprocessors, digital signal processors (DSPs) and/or microcontrollers, or other similar device(s); or c) a combination of the forms mentioned in a) and b).
Note that any and all of the embodiments described above can be combined with each other, except to the extent that it may be stated otherwise above or to the extent that any such embodiments might be mutually exclusive in function and/or structure.
Although the present invention has been described with reference to specific exemplary embodiments, it will be recognized that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.

Claims

CLAIMS What is claimed is:
1 . A transmitter, comprising:
an interface configured to receive data;
a scrambler configured to whiten the payload of the received data;
a CRC encoder configured to add error check bits to the PHR of received data, a convolutional encoder configured to provide error correction coding to whitened payload data and CRC protected PHR data;
a bit interleaver and a repetition interleaver logic configured to create diversity in the data;
a mapping logic to map the diversified data to subcarriers;
adding Gl logic configured to add a guard interval to the IFFT symbol;
preamble data logic configured to add preambles to the IFFT symbols to construct a transmitted frame or packet; and
a DAC configured to convert the frame or packet to an analog signal.
2. The transmitter of claim 1 , wherein the scrambler uses a PN9 sequence to whiten payload data.
3. The transmitter of claim 1 , wherein the convolutional encoder has a coding rate of ½.
4. The transmitter of claim 1 , wherein the repetition interleaverlogic is configured to output repetition_x2=[basedata; circshift(basedata, 8)].
5. The transmitter of claim 1 , wherein the repetition interleaver logic is configured to output repetition_x4=[basedata; circshift(basedata,8); circshift(basedata, 8*2-2); circshift(basedata, 8*3+2)].
6. The transmitter of claim 1 , wherein subcarrier spacing is 9.375 kHz.
7. The transmitter of claim 1 , wherein the preambles includes STFs and LTFs, and the STFs are symmetrical and periodic and LTFs include the IFFT of a
Pseudo-Random Binary Sequences (PRBS) for channel estimation and FFT window location adjustment.
8. The transmitter of claim 7, wherein the adding Gl logic adds guard intervals external to the IFFT symbol
9. The transmitter of claim 1 , further comprising an IFFT of 128p to decrease packet length.
10 The transmitter of claim 1 , the lengths of frames are fixed to 3776, 2624 and 1472 samples for data frame of repetition 4, repetition 2 and command frame respectively.
1 1 . A method, comprising:
receiving data;
whitening the payload data;
CRC protecting the PHR data;
providing error correction encoding the whitened payload data and CRC protected PHR data;
creating diversity in the data;
mapping the diversified data to subcarriers;
adding a guard interval to the IFFT symbol;
adding preambles to the IFFT symbols to constructing a transmitted frame; and converting the frames to an analog signal.
12. The method of claim 1 1 , wherein the scrambler uses PN9 sequence to whiten payload data
13. The method of claim 1 1 , wherein the convolutional encoder has a code rate of ½.
14. The method of claim 1 1 , wherein the creating diversity outputs
repetition_x2=[basedata; circshift(basedata, 8)].
15. The method of claim 1 1 , wherein the creating diversity outputs
repetition_x4=[basedata; circshift(basedata,8); circshift(basedata, 8*2-2);
circshift(basedata, 8*3+2)].
16. The method of claim 1 1 , wherein subcarrier spacing is 9.375 kHz.
17. The method of claim 1 1 , wherein the preambles includes STFs and LTFs, and the STFs are symmetrical and periodic and LTFs include the IFFT of a
Pseudo-Random Binary Sequences (PRBS) for channel estimation and FFT window location adjustment.
18. The method of claim 17, wherein the adding guard intervals adds guard intervals to the IFFT symbol
19. The method of claim 1 1 , further comprising performing an inverse fast Fourier transform at 128p on the mapped data to decrease packet length.
20. A transmitter, comprising:
means for receiving data;
means for whitening the payload data;
means for CRC protecting the PHR data
means for providing error correction encoding the whitened payload data and CRC protected PHR data;
means for creating diversity in the data;
means for mapping the diversified data to subcarriers;
means for adding a guard interval to the IFFT symbol;
means for adding preambles to the IFFT symbols to constructing a transmitted frame; and
means for converting the frames to an analog signal.
PCT/US2012/049222 2011-09-29 2012-08-01 Power line communications transmitter/receiver Ceased WO2013048619A1 (en)

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US201161541073P 2011-09-29 2011-09-29
US61/541,073 2011-09-29

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