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WO2012101467A1 - Amplificateur différentiel efficace à faible bruit, et réutilisation du courant de polarisation - Google Patents

Amplificateur différentiel efficace à faible bruit, et réutilisation du courant de polarisation Download PDF

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Publication number
WO2012101467A1
WO2012101467A1 PCT/IB2011/000231 IB2011000231W WO2012101467A1 WO 2012101467 A1 WO2012101467 A1 WO 2012101467A1 IB 2011000231 W IB2011000231 W IB 2011000231W WO 2012101467 A1 WO2012101467 A1 WO 2012101467A1
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Prior art keywords
current
differential
voltage
amplifier
input
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PCT/IB2011/000231
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Inventor
Alfredo ARNAUD MACEIRA
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TREDEFIN SA
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TREDEFIN SA
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Definitions

  • This invention in general is related, to devices and methods for amplifying electric signals.
  • the present invention is related to analog integrated circuits, particularly low noise, and high gain amplifiers with minimum power consumption.
  • Micropower, ultra low noise amplifiers for implantable medical devices are examined in detail, but the amplifiers and the group of circuit techniques of the invention, may be employed also in efficient sensor amplifiers for portable devices and battery powered data loggers, minimum power low noise radio frequency amplifiers for wireless communications equipment and radio frequency identification devices, and in general for those applications involving high performance analog amplifiers and filters requiring a minimum power consumption.
  • Circuit techniques for reducing the effects of op-amp imperfections autozeroing, correlated double sampling, and chopper stabilization
  • C.C.Enz and G.C.Temes Proceedings of the IEEE, vol. 84, n°l 1, pp.1584-1614, November 1996.
  • a well known differential pair is shown. It is composed by two input transistors M la and that realize the current-to-voltage conversion, a current mirror M 2a , M 2 b that copies the current through M la to the output, and a current source transistor M3 to bias the input transistors (M 3 in the picture copies a reference current ias)-
  • Iout S m i in+ > ⁇ in- ⁇ me output current, the gate transconductance of the M la and Mi , transistors, the positive voltage input of the differential amplifier, and the negative voltage input of the differential amplifier respectively.
  • the topology in Figure 1 is preferred because of its differential characteristic, because the input is isolated from the output, and because of the input transistors are current biased which results in a precise operating point, a large CMRR (common mode rejection ratio) and a large PSRR (rejection ratio to power supply variations).
  • VDD is defined (as in Figure 1) as the supply voltage of the circuit.
  • V D D which can power the circuit of Figure 1 is given by Vosa t i + Vosati +TMax V S at2,VGsi)- From now on for any circuit in this document, V SO will denote the saturation voltage of a given transistor M x , VQS X will denote the Gate to Source voltage for a given transistor M x , and max ⁇ x,y) will denote the maximum of two magnitudes x and y. Low power consumption is a major concern in battery powered electronic devices to extend battery life.
  • Flicker noise eventually can be reduced to a negligible value by means of circuit techniques like those described in "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", C.C.Enz and G.C.Temes, Proceedings of the IEEE, vol.84, n°l l, pp.1584— 1614, November 1996.
  • thermal noise depends on the bias current of the transistors and it is necessary to increase power consumption to reduce it.
  • Consistent noise models for analysis and design of CMOS circuits A. Arnaud, C.
  • DC-DC converters are not very efficient themselves if the current consumption is low.
  • charge pump type DC-DC converters are normally employed if the current consumption is in the micro-Amperes order.
  • a PAD is a connection node from the IC to the outside of the circuit.
  • VDD- 5 capacitors and 9 PADs are required.
  • V D D may be as low as IV (leaving a reasonable margin for the signal at the output) which would reduce power consumption by a factor of 3.6 comparing to 7/3 ⁇ 4DF3.6V.
  • V DD voltage division multiplexing
  • the objective of the invention here presented is to implement efficient amplifiers. In these most of the energy is dissipated in the input transistors that carry out the voltage to current conversion, not in those transistors that are just used to bias the circuit or in current mirrors. These amplifiers should be current biased to preserve a precise operating point, a large CMRR (common mode rejection ratio), and a large PSR (power supply rejection ratio).
  • the objective of the invention is to develop amplifiers where most of the consumed battery power, is dissipated by those current biased input transistors that effectively carry-out the amplification task, and not in biasing transistors.
  • the present invention proposes to stack successive differential pairs to reutilize the same bias current from the battery, either combined with efficient current sources able to operate with few tens of mV voltage drop.
  • the present invention combines a capacitor on each gate of the input transistors of a current biased complementary differential pair to decouple the input, making it possible the operation of the complementary pair with a very low supply voltage.
  • a complementary differential pair (a PMOS pair plus an NMOS pair connected by their drains) with independent inputs (NMOS and PMOS gates are not connected) results in fact in a so-called differential difference amplifier where its output is a certain gain multiplied by the difference of the differential inputs of each pair.
  • independent differential pairs are regularly used to implement differential difference amplifiers thus the bias current is not reutilized.
  • Two differential pairs (each one biased by its own current source) are used for example in U.S. patent 6,996,435 to implement a state of the art low noise amplifier for electroneurograph signal recording (ENG) in implantable medical devices.
  • the current source biasing the differential pair is a single MOS transistor M 3 , but in the U.S. patent 6,996,435 differential pairs are biased by means of high output impedance cascode current sources.
  • Current sources with a high output impedance are required to achieve a large CMRR as needed in ENG recording, but cascode current sources require a much larger minimum voltage drop to operate (and thus much more power).
  • a current source with a very high output impedance but also a very low operating voltage for a minimum power consumption while preserving the overall CMRR and PSRR characteristics should be employed.
  • the present invention proposes to use different active current sources including a pass transistor operating either in saturation or in the linear region to bias the differential pairs in a differential amplifier.
  • Fig.l Is the schematic of a classic differential CMOS pair input stage, representing prior state of the art for several applications.
  • Fig.2 Is an amplifier stage according to the present invention, with a differential voltage input, and a differential output current, composed by an NMOS differential pair biased with a current source, and a PMOS differential pair also biased with a current source. Both pairs are stacked and connected by their drains to make the best use of the current through the circuit branch.
  • Fig.3 Is an amplifier where the current sources of Figure 2 have been substituted by transistors, and a current to voltage conversion is carried out by a resistor at the output. An operational amplifier fixes the common mode voltage at the output.
  • Fig.4(a) Is a preferred embodiment of the invention, where capacitors are connected to decouple the gate voltage of each input transistor.
  • Fig.4(b) Is a circuit diagram showing a possible method to establish the DC voltage of the gate of the input transistors, using diodes that are connected to a reference voltage. Note that since the voltage drop across the diodes tends to zero, the diodes represent a extremely large impedance for small signal calculations.
  • Fig.5 (a) Is a circuit containing several differential stages like the one in Figure 4(a), stacked to reuse the bias current in a very efficient way.
  • a common mode feedback loop (CMFB) is included on each stage to guarantee the common mode voltage at the output.
  • CMFB loop plays the role of the operational amplifier in Figure 3, but in a more efficient manner.
  • Fig.5(b) Is a second stage of the amplifier, to sum the output of the stacked differential stages of Figure 5(a).
  • Fig.5(c) Is a picture illustrating the advance of the present invention when compared to current state of the art: on the left two amplifiers require each 600 ⁇ current from the battery to achieve a given performance, in the center both are combined like in Figure 2 and only 300 ⁇ current is needed to achieve the same performance, finally on the right three stages like the one in the center of the picture are stacked to make efficient use of the supply current and only ⁇ current is now required.
  • the technique of the invention can be extended for K stacked differential pairs of any type.
  • Fig.6 Is a representation of two possible applications for the amplifier of the invention: first an electrode is connected at the input to amplify biopotentials in an implantable medical device, secondly an antenna is connected at the input of the first stage in a wireless receiver.
  • Fig.7 Is a circuit diagram for the CMFB block and the current source in a complementary differential pair like those stacked in Figure 5(a), both implemented with a single pass transistor and a feedback transconductor.
  • Fig.8 Is a possible realization of a dual output (sink/source) current source as needed to reutilize the current in the circuit in Figure 5(a).
  • Fig.9(a) Is a current source connected to ground, composed by a sense resistor, a feedback OTA, and a MOSFET pass transistor.
  • the current source has a voltage input Vc t ri to control the output current, and is able to operate at a very low voltage but showing at the same time an extremely large output equivalent resistance.
  • Fig.9(b) Is the current source of Figure 9(a) but adapted to provide a dual current output. This current source can be employed to interconnect stages as in Figure 5(a).
  • Fig.10 Is a differential amplifier stage like the one in Figure4(a) able to be stacked like in Figure 5(a), but several switches have been incorporated to periodically fix the DC gate voltage of the transistors (and eventually to adjust the amplifier's offset).
  • CMFB loop is also shown.
  • Fig.11 Is the result of a computer simulation, of an amplifier according to the present invention with electroneurograph (ENG) specifications.
  • the inputs are decupled by means of an RBC;,, circuit to obtain a high-pass characteristic (RB is the dynamic resistance of the diodes connected as in Figure 4(b)).
  • the total current consumption is 20 ⁇ from a 3.6V battery, the simulated input referred noise is just 4nV/VHz at lkHz frequency.
  • Figure 2 shows a basic differential amplification block according to the present invention.
  • the amplifier has two inputs J1 ⁇ 2 + y Vm- ⁇ It is composed by two opposite, stacked, MOS differential pairs. One is a NMOS pair constituted by M la y M ⁇ b , and the other is a PMOS pair constituted by M2 a y ⁇ 3 ⁇ 4 .
  • the output of the amplifier is a differential current, given by the difference between the currents I a and h in the picture.
  • the small-signal output current lou t is defined: ) 0)
  • Equation (3) assumes that both NMOS and PMOS transistors are biased in the same inversion level, ideally both in Weak Inversion to minimize the input referred noise.
  • g ml « g m2 g m .
  • the circuit is very efficient because the four transistors amplify the input signal in a cooperative way, but the four transistors introduce no-correlated noise to the circuit. So the input referred noise is reduced because it is divided by the gain.
  • thermal noise it can be calculated:
  • S Vjn (f) is the equivalent amplifier's input referred noise voltage PSD
  • S lx (f) is the noise current PSD introduced in the circuit by each transistor M x (in a first approach all S lx (f) are supposed to be equal).
  • the last term in equation (4) applies only for thermal noise. But the term in the middle of equation (4) does not assume a specific noise type, thus the circuit in Figure 2 results very efficient not only to minimize thermal noise but also to reduce flicker noise.
  • An equation analogous to (4) can be written for the input referred offset due to random mismatch between transistors.
  • the advantages of the circuit in Figure 2 come from the elevated total transconductance over supply current ratio of the amplifier. It should be pointed that regardless of the bias current and transistor size, the maximum tranconductance over drain current ratio that
  • the input referred noise is divided by a factor of 2 or 4, when comparing equations (4) and (2) depending on whether the mirrors M 2 in Figure 1 are biased in strong or weak inversion respectively.
  • all the transistors in Figure 2 including those implementing the current sources can be biased in Weak Inversion showing a reduced saturation voltage, allowing the operation of the circuit at a very low supply voltage.
  • Figure 3 shows the amplifier block of Figure 2, but the current sources have been substituted by a current mirror M 3 to bias the NMOS differential pair, and a current mirror M4 to bias the PMOS differential pair. Also a current to voltage conversion is carried at the output by two resistors R 1, connected as in the paper "Low noise amplifier for recording ENG signals in implantable systems", J.Sacristan and M.T.Oses, Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS'04, vol.IV, pp.33-36, May 2004. This amplifier has an output voltage V out as shown in Figure 3.
  • An operational amplifier 2 is connected to the middle node of the output resistors to set the common mode voltage at the output, compensating in this way any mismatch between the current sources M 3 and M4.
  • the operational amplifier (Oparnp) guarantees that the common mode voltage at the output (apart of a residual random mismatch offset) will be equal to VcM_Ref, a reference voltage in the positive input of the Opamp.
  • M 3 current, and M4 current are both derived by means of current mirrors from a single current reference 3, 20 times lower than ⁇ . This value was arbitrarily selected to make negligible the power consumption by any circuit branch different than that of the differential pairs.
  • the common mode voltage at the output must be controlled in some way. If it is not controlled, the drain voltage of M la , M 2a transistors 4, and the drain voltage of Mi b , M 2b transistors 5, either will drop until the NMOS pair is no longer saturated or will rise until the PMOS pair is no longer saturated. The amplifier will not properly work on this condition. Although it is not very power efficient, the circuit in Figure 3 is a possible realization to control the common mode voltage at the output. An efficient common mode control loop will be proposed later in the description of the invention.
  • Figure 4(a) shows an amplifier block like the one in Figure 2, but the input transistors gates have been decoupled by means identical capacitors Cj retail. It is necessary to initially fix the gate voltages V G i a (6), V G ib (7), VG2O (8), Vo2b (9), of each input transistor M la , M ⁇ , M 2a , M 2b , respectively to an appropriated value. The voltage fluctuations at the input of the amplifier will appear also in the gate of each transistor but with smaller amplitude given by the capacitive divider:
  • FIG 4(b) a preferred embodiment of the invention is shown, with opposite diodes connected to a reference voltage (in this case obtained from a resistive voltage divider) to fix the DC gate voltage of the input transistors.
  • a reference voltage in this case obtained from a resistive voltage divider
  • This so-called clamping diodes in figure 4(b) have an extremely large equivalent resistor (small signal analysis) enabling the amplification of even very low frequency signals.
  • the diodes in Figure 4(b) can be substituted just by resistors if the frequency of the signal to amplify is large, or the nodes 6, 7, 8, 9, can be connected by means of switches to periodically adjust their voltage.
  • This periodic adjust can be either combined with the process known as Autozero mentioned in "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", C.C.Enz and G.C.Temes, Proceedings of the IEEE, vol.84, n°l l, pp.1584-1614, November 1996.
  • the Autozero process consists in disconnecting the input signal of the amplifier at regular time intervals, where the amplifier's inputs are short-circuited and a voltage is adjusted and subtracted at the input to null the output, effectively canceling the amplifier's input referred offset. This process will be further discussed when describing Figure 10.
  • the input voltage ( Vm+ - VIM- ) is the same for all the stacked stages, their gates being decoupled through identical capacitors. Because the successive differential stages are stacked, there is no need to reduce the supply voltage to achieve the maximum possible power efficiency. Note the invention is not limited to the specific stack of complementary differential stages, and different types of differential amplifier pairs/stages can be stacked (for example differential pairs using bipolar transistors, or all-NMOS or all-PMOS differential pairs) to reutilize the current from the battery if the adequate bias scheme is provided.
  • circuit in Figure 5(a) is only a particular embodiment of the invention, and the scheme where several differential amplifier stages are stacked to power them with the same supply voltage can be applied for a wider range of unitary differential amplifiers, with either a current or a voltage output.
  • the method can be extended also to save power in circuits different than amplifiers, for example filters with a given transfer function but a gain no necessarily > 1. Successive stages of a filter can be stacked to reutilize the bias current, the output of one of the stacked stages becoming the input of the next.
  • FIG 5(a) is a preferred embodiment of the invention, where all the staked amplifying stages are as the one in Figure 4(a).
  • each differential output voltage will be referred to as V 0u ti, Vo u t2, Vo ts, for the output of stages 10, 11, 12 respectively. Therefore Voutx denotes the differential voltage between the drains of M la and Mib transistors both of which are connected to the drains of M 2a and ⁇ 3 ⁇ 4 according to Figure 4(a).
  • the output voltages V 0u ti, Vo 2, Vout3 are summed in a second stage as shown in Figure 5(b).
  • this second stage Because the signal at the input of this second stage has been previously amplified by the first stage, it has much relaxed input referred noise requirements than in the case of the first stage of Figure 5(a). So the power consumption of this second stage can be, with an adequate design, several times lower than the power consumption of the first stage.
  • the amplifier block in Figure 5(a) has K stacked differential amplifiers, and a single differential input ( V IN+ - V ® . ). Assuming that all the transistors of the complementary differential amplifiers are biased in the same inversion level (ideally in Weak Inversion to minimize thermal noise), all the gate transcoductances will be equal.
  • the circuit is very efficient because the 4-K transistors amplify the input signal in a cooperative way, but the 4-K transistors introduce non-correlated noise to the circuit. So the input referred noise is reduced because it is divided by the gain.
  • thermal noise it can be calculated:
  • S Vin (f) is the equivalent noise voltage PSD at the amplifier's input
  • S lx (f) is the noise current PSD introduced in the circuit by each transistor M x ( in a first approach all S lx (f) are supposed to be equal).
  • the last term in equation (6) applies only for thermal noise, but the term in the middle does not assume a specific noise source, thus the circuit in Figure 5(a) results very efficient not only to minimize thermal noise, but also to reduce flicker noise, and an equation analogous to (6) can be written also for the input referred offset due to random mismatch between transistors.
  • CMOS complementary metal-oxide-semiconductor
  • a 'dual current source' denotes a circuit block connected between two nodes A, B such that the current entering through node A and the current through node B have the same absolute value and opposite sign, independently of the voltage of each node within a certain operating range.
  • a dual current source has also an input voltage to control the absolute value of the output current.
  • the current sources necessary to implement the circuit in Figure 5(a) ideally should not consume any additional power, however in a real case some additional power consumption will be necessary.
  • a minimum VAB is preferred because the number K of stages to stack in principle is limited only by the stacked saturation voltage of the transistors of the differential pairs, the stacked minimum operating voltages ( VAB ) of the current sources in Figure 5(a), and a certain voltage excursion at the output; the sum must be less than VDD-
  • FIG. 5(c) A scheme is shown in Figure 5(c) to further illustrate the benefits of the present invention in comparison to prior state of the art amplifiers.
  • three amplifiers are stacked in series to be powered by a single supply voltage like in Figure 5(a), and only a IDD ⁇ ⁇ supply current is necessary to achieve the initial input referred noise performance.
  • the proposed method can be applied to an arbitrary number K of stacked stages provided all the differential pairs are saturated for the selected VDD-
  • FIG. 6 Two possible applications for the invention are shown in Figure 6.
  • An electrode is connected at the amplifier's input; the amplifier's output is connected to an AD converter or detection circuitry of the medical device.
  • the proposed topology is an advance in comparison with, for example, the state of the art amplifiers described in U.S. patent application 0155966 Al, or the amplifier described in the U.S. patent 6,996,435 that do not employ stacked amplifiers or complementary differential pairs to amplify signals thus resulting in a much higher power consumption.
  • a second application is shown: the amplifier of the invention as part of a wireless communications receiver.
  • an antenna is connected a the input, or in the case of radio-frequency identification at low frequency (LF-RFID) a simple inductive coil can substitute the antenna.
  • LF-RFID radio-frequency identification at low frequency
  • a resonant network can substitute the resistors R of Figure 3, but the working principle is the same.
  • the circuit composed by G M FB and MFB in Figure 7, implements both the CMFB block and the lower current source of a single stage of the amplifier of Figure 5(a). Because the MFB transistor may operate even in the linear region the voltage drop in MFB can be extremely low, for example as low as 50mV. So the circuit is particularly adequate for the invention in Figure 5(a).
  • the scheme in Figure 7 resembles the topology of the circuits presented in the U.S. patent 4,769,564, U.S. patent 5,936,466, U.S. patent 6,118,318 or U.S. patent U.S. 6,642,790 all of them using a single complementary MOS differential pair, but these circuits are not biased from a reference current them are self biased instead.
  • Figure 8 shows another possible realization for a current source to connect stacked differential amplifiers, like the sources 14, 15 in Figure 5(a), independently of the CMFB block.
  • the current reference 7 ⁇ / enters trough the NMOS on the left and is copied to the output transistor.
  • I Re f is several times lower than the output current to minimize the power consumption as the reference current is connected directly to the supply voltage VDD-
  • the main current branch between nodes A and B in Figure 8, may connect the stacked differential stages of Figure 5(a).
  • a CMOS technology including an isolated P-Well is necessary in this realization of this current source using NMOS transistors, to avoid the so-called 'body effect' since both source and drain of the transistors are connected to an arbitrary voltage. Because a control voltage V n is necessary to adjust the output current, an extra transistor Mctri is included.
  • the gate voltage of Mc t ri is used to control a current that is summed to
  • the outputs I A , I B in Figure 8 are related to Va r i as follows: I A - N- ⁇ l Ref + I Ctrl ) ;
  • I B (N + l)- (l Ref +I ClrI ).
  • the current source in Figure 8 results adequate for the circuit of Figure 5(a) but is necessary, during the amplifier design, to consider the differences between the sink and source currents I A and as each differential stage in Figure 5(a) will be biased by a slightly different current.
  • the main problem with the current source in Figure 8 are its poor output impedance, and that it requires a relatively large voltage drop VAB to operate (around 200mV or larger) because the output transistor must be saturated.
  • the reduction of the output impedance results in a poor common mode rejection ratio (CMRR) that is an important characteristic of amplifiers.
  • An improved current source should operate with a voltage drop VAB lower than the saturation voltage of a single transistor, guarantee that the current I A and IB for both nodes A and B have the same absolute value, and present the largest possible output impedance.
  • the circuit in Figure 9(a) shows a preferred current source for the amplifier of the invention.
  • the current source is composed by a sense resistor Rs, a MOS pass transistor MR in series, and a feedback transconductor G Reason,FB that controls the impedance of MR SO that the voltage drop in R s results equal to a control voltage Van- Because the transistor MR can operate in its linear region, the voltage of A can be very low.
  • Vctri can be selected as 30mV so that results much larger man the input offset voltage of GmFB- Since precision OTAs can be realized consuming as little as few tens nA or less, GmFB can be powered directly from the supply voltage VDD without a significant increase of the overall circuit power consumption.
  • the output impedance of the current source in Figure 9(a) is very high particularly at low frequency, because it does not depend on the output impedance of MR.
  • G m FB transconductance, MR size, and Vc t ri can be selected according to output impedance, power consumption, and other specifications.
  • the current source of Figure 9(a) can be utilized instead of the grounded current source 13 in Figure 5(a).
  • Figure 9(b) a floating dual current source, using the same principle of Figure 9(a) is shown.
  • the current source of Figure 9(b) can be utilized instead of the current sources 14, 15, in Figure 5(a). In this case the feedback OTA G m pB has been substituted by a dual differential input OTA.
  • FIG. 10 a more complex version of a single differential amplifier stage of Figure 5(a) is shown in Figure 10.
  • the stage includes appropriate switches to periodically adjust the voltage of the input transistors' gates, and to implement the so-called 'Autozero' technique to guarantee minimum offset and minimum low frequency noise.
  • Autozero technique consists in periodically sampling offset and noise that is later subtracted at the input.
  • switches 17, 18, 19, 20, in Figure 10 are open and the signal to amplify is connected to the inputs VIM- and VIN + through the switches 21 that are closed.
  • the signal to amplify is periodically disconnected from the amplifier's input (switches 21 are opened), both inputs are short-circuited to a reference voltage VCM through the switches 20, and then the gates of the four input MOS transistors are connected to a proper voltage NRef A and VR e f_B by closing the corresponding switches 17, 18.
  • switches 17 and 18 are opened and switches 19 are closed, so the transconductor Gm2 delivers the necessary current to charge gates of the transistors on the left to null the output voltage.
  • switches 19 are opened and the signal to amplify is reconnected again to the input.
  • the OTA G ml in Figure 10 controls a current source, preferably one like in Figure 8, Figure 9(a) or Figure 9(b). It should be pointed that Figure 10 is a possible realization of the invention but not the only. In a different realization it is only necessary to guarantee in some way an appropriate operating voltage of the nodes equivalent to 6 7 8 y 9 of Figure 4(a), without introducing a significant excess noise at the input nodes.
  • a computer simulation of a complete differential amplifier like the one in Figure 5(a) is shown in Figure 11.
  • the purpose of the circuit is to amplify electroneurograph signals (ENG), in the frequency span of 100 to 10kHz.
  • ENG signals have very low amplitude, as low as ⁇ RMS, which require the use of very low noise amplifiers.
  • This application fits the scheme of Figure 6; ENG signals are registered by using proper differential electrodes.
  • the amplifier of the invention can help develop more efficient medical devices as ENG signal recording is being incorporated in novel active medical implants.
  • the current sources in Figure 11 are like the one in Figure 9(a) and Figure 9(b), where each transconductor consumes only 300nA current from the battery to make the total current consumption of the sources, negligible in comparison to the overall current consumption of the amplifier.
  • the output common mode feedback (CMFB) is implemented with a transconductor like in Figure 7, but Autozero like in Figure 10 is not applied.
  • CMFB output common mode feedback
  • the simulated gain-frequency plot of amplifier is shown, as well as a scheme of the stacked differential stages on the right.
  • the total current consumption of the circuit including the five complementary differential pairs and all the OTAs for CMFB and current sources, is less than 30 ⁇ from a VDD - 3.6V battery (the nominal voltage of a usual rechargeable battery).
  • the input referred noise voltage in the band from 100 to 10kHz is just 4nV/VHz.
  • the bandwidth of the plot in Figure 11 is several times higher than needed, thus the present invention shows to be valuable also to implement high frequency and low power amplifiers.
  • a band-pass and a summing second stage like in Figure 5(b) should be implemented.

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Abstract

Selon certains aspects, l'invention concerne un dispositif comprenant une pluralité de caméras agencées en réseau, chaque caméra de la pluralité de caméras générant un signal indicatif d'un rayonnement qui vient frapper la caméra respective, et la pluralité de caméras étant agencée de telle sorte que le champ de vision de chaque caméra de la pluralité de caméras chevauche au moins partiellement le champ de vision d'au moins une caméra adjacente de la pluralité de caméras afin de former une pluralité respective de régions de chevauchement ; un composant de conversion d'énergie destiné à convertir le premier rayonnement qui vient frapper sa surface en un second rayonnement à une énergie plus faible pouvant être détectée par la pluralité de caméras ; et au moins un ordinateur destiné à traiter les signaux provenant de chaque caméra de la pluralité de caméras afin de générer au moins une image, un processeur étant configuré pour combiner des signaux dans la pluralité de régions de chevauchement afin de former ladite image.
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US20130106513A1 (en) * 2011-11-02 2013-05-02 Marvell World Trade Ltd. Differential amplifier
EP2713171A3 (fr) * 2012-09-26 2015-02-11 Broadcom Corporation Amplificateur de fréquence radio de classe AB pour détecteur d'enveloppe
WO2015057759A1 (fr) * 2013-10-17 2015-04-23 Knowles Electronics, Llc Appareil haute impédance à différentiel
WO2016025177A1 (fr) * 2014-08-13 2016-02-18 Northrop Grumman Systems Corporation Régulation d'intensité-tension de polarisation empilée
US9287830B2 (en) 2014-08-13 2016-03-15 Northrop Grumman Systems Corporation Stacked bias I-V regulation
US9924904B2 (en) 2014-09-02 2018-03-27 Medtronic, Inc. Power-efficient chopper amplifier
US10622950B2 (en) 2015-12-04 2020-04-14 Ams Ag Amplifier arrangement and switched capacitor integrator
EP3176945A1 (fr) * 2015-12-04 2017-06-07 ams AG Agencement d'amplificateur et intégrateur à condensateur commuté
WO2017092980A1 (fr) * 2015-12-04 2017-06-08 Ams Ag Montage amplificateur et intégrateur à capacités commutées
JP2020520715A (ja) * 2017-05-25 2020-07-16 ペースセツター、インコーポレイテツドＰａｃｅｓｅｔｔｅｒ，Ｉｎｃ． 植込み型医療システムにおけるインプラント間通信のためのオフセット補正された常時オンの受信機
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