WO2012101467A1

WO2012101467A1 - Efficient low noise differential amplifier, reutilizing the bias current

Info

Publication number: WO2012101467A1
Application number: PCT/IB2011/000231
Authority: WO
Inventors: Alfredo ARNAUD MACEIRA
Original assignee: TREDEFIN SA
Current assignee: TREDEFIN SA
Priority date: 2011-01-24
Filing date: 2011-01-24
Publication date: 2012-08-02
Anticipated expiration: 2013-07-24

Abstract

According to some aspects, a device comprising a plurality of cameras arranged in an array, each of the plurality of cameras producing a signal indicative of radiation impinging on the respective camera, the plurality of cameras arranged such that the field of view of each of the plurality of cameras at least partially overlaps the field of view of at least one adjacent camera of the plurality of cameras, to form a respective plurality of overlap regions, an energy conversion component for converting first radiation impinging on a surface of the energy conversion component to second radiation at a lower energy that is detectable by the plurality of cameras, and at least one computer for processing the signals from each of the plurality cameras to generate at least one image, the at least one processor configured to combine signals in the plurality of overlap regions to form the at least one image is provided.

Description

AN EFFICIENT LOW NOISE DIFFERENTIAL AMPLIFIER, REUTILIZING THE BIAS

CURRENT

Field of the invention

This invention in general is related, to devices and methods for amplifying electric signals. The present invention is related to analog integrated circuits, particularly low noise, and high gain amplifiers with minimum power consumption. Micropower, ultra low noise amplifiers for implantable medical devices are examined in detail, but the amplifiers and the group of circuit techniques of the invention, may be employed also in efficient sensor amplifiers for portable devices and battery powered data loggers, minimum power low noise radio frequency amplifiers for wireless communications equipment and radio frequency identification devices, and in general for those applications involving high performance analog amplifiers and filters requiring a minimum power consumption.

References cited.

Patents

- "Sense Amplifier", U.S. patent 4,769,564, 09/1988, D.Gardo.

- "Differential Operational Transconductance Amplifier", U.S. Patent 5,936,466, 08/1999, H.Andoh, D.Duan Lee Tang.

- "Differential Complementar Amplifier", U.S. Patent 6,642,790, 11/2003, K.Schr5dinger, J.Stimma.

"Implantable Signal Amplifying Circuit for Electroneurographic Recording", U.S. Patent 6,996,435 02/2006, M.Baru.

- "Low Power, Low Noise CMOS Amplifier", U.S. Patent Application 2003/0155966 Al, R.Harrison.

"Ultra Fast, Low Noise Operational Amplifier with Dynamic Biasing", U.S. patent 7,135,927 10/2006, Charles Parkhurst.

- "Self Biased Differential Amplifier with Histeresis", U.S. patent 6,118,318 9/2000, J.Fifield, G.Heller.

Scientific papers

"Consistent noise models for analysis and design of CMOS circuits", A. Arnaud, C. Galup Montoro, IEEE Transactions on Circuits & Systems I, Vol.51, n°10, pp.1909-1915, October 2004

"Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", C.C.Enz and G.C.Temes, Proceedings of the IEEE, vol. 84, n°l 1, pp.1584-1614, November 1996.

"A Sub-Microwatt Low-Noise Amplifier for Neural Recording", J.Holleman and B.Otis, 29th Annual International Conference of the IEEE-EMBS, pp.3930-3933, August 2007.

"Low noise amplifier for recording ENG signals in implantable systems", J. Sacristan and M.T. Oses, Proceedings of IEEE International Symposium on Circuits and Systems ISCAS'04, vol.IV, pp.33-36, May 2004. Background of the invention.

In Figure 1, a well known differential pair is shown. It is composed by two input transistors M_la and

that realize the current-to-voltage conversion, a current mirror M_2a, M₂b that copies the current through M_la to the output, and a current source transistor M3 to bias the input transistors (M₃ in the picture copies a reference current ias)- The output of this circuit is the current lo_ut: l0ut = gml(^VIn₊ - ^VIn-) (1)

In equation (1), Iout_>S_mi in+ _> ^in- ^ ^me output current, the gate transconductance of the M_la and Mi , transistors, the positive voltage input of the differential amplifier, and the negative voltage input of the differential amplifier respectively. The topology in Figure 1 is preferred because of its differential characteristic, because the input is isolated from the output, and because of the input transistors are current biased which results in a precise operating point, a large CMRR (common mode rejection ratio) and a large PSRR (rejection ratio to power supply variations). VDD is defined (as in Figure 1) as the supply voltage of the circuit. It is a well known fact that several characteristics of the amplifier in Figure 1 like the input referred noise, the input referred mismatch offset, the gain, among others depend on the bias current ias (that in this case is approximately equal to the supply current IDD provided by the supply voltage of Figure 1) but not on the supply voltage VDD itself. The power consumption of the whole differential amplifier in Figure 1 is V_DD · I_DD . Thus if minimum power dissipation is required within the circuit, then VDD should be the minimum possible as a lower VDD does not degrade the amplifier characteristics. The minimum V_DD which can power the circuit of Figure 1 is given by Vosa_ti + Vosati +™ax V _Sat2,VGsi)- From now on for any circuit in this document, V _SO will denote the saturation voltage of a given transistor M_x, VQS_X will denote the Gate to Source voltage for a given transistor M_x, and max{x,y) will denote the maximum of two magnitudes x and y. Low power consumption is a major concern in battery powered electronic devices to extend battery life.

As pointed in "Consistent noise models for analysis and design of CMOS circuits", A. Arnaud and C. Galup Montoro, IEEE Transactions on Circuits & Systems I, Vol.51, n°10, pp.1909-1915, October 2004, there are two sources for input referred noise in a CMOS amplifier: flicker noise, and thermal noise. The former is inversely proportional the area mainly of the input transistors of the amplifier thus large transistors can be selected to reduce flicker noise. Flicker noise eventually can be reduced to a negligible value by means of circuit techniques like those described in "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", C.C.Enz and G.C.Temes, Proceedings of the IEEE, vol.84, n°l l, pp.1584— 1614, November 1996. In contrast, thermal noise depends on the bias current of the transistors and it is necessary to increase power consumption to reduce it. As pointed in "Consistent noise models for analysis and design of CMOS circuits"; A. Arnaud, C. Galup Montoro, IEEE Transactions on Circuits & Systems I, Vol.51, n°10, pp.1909-1915, October 2004, to minimize thermal noise M_\ transistors in Figure 1 should be biased in Weak Inversion to achieve the highest possible g_ml/l_m ratio (Mi denotes either of the M_la and Mu, transistors, and _¾_¾ denotes the DC(direct current) bias drain current of a given transistor M_x). For a given transistor, a larger g_ml/I_m allows to improve gate referred noise or mismatch for the same current consumption budget. From now on in the description of the invention the focus will be on thermal noise, but the invention can also be used (for a given current consumption budget) to reduce the input referred flicker noise, to reduce input referred mismatch offset, to increase the gain, of a given amplifier using the proposed architecture. In the previously cited reference, thermal noise Power Spectral Density (PSD) of an amplifier like the one in Figure 1 is calculated:

where k the Boltzmann's constant, T is the absolute Kelvin temperature, g_wl, g_m2, are the gate transconductance of the respective transistors Mi M₂, n is the slope factor (n is a number slightly larger than 1), and γ = 2 is a constant. S_Vi„(f) denotes the input referred noise voltage PSD, its units are V²/Hz . Assuming that M_la and Mu, of Figure 1 are biased in Weak Inversion, M_2a and M_¾ should be biased in Strong Inversion to minimize as much as possible the second term in equation (2). But when M2 transistors are biased in strong inversion both Vosa and VGS2 increase, thus also the minimum V D necessary to operate the circuit increases. In the circuit in Figure 1, even if it is powered with the minimum possible VDD, most of the energy is dissipated by the M₂ and M₃ transistors while only a small fraction of the energy is dissipated in the Mi transistors, those that effectively perform the voltage to current conversion (in fact M_la, Mi_b are the only transistors that act as amplifiers).

Most applications where it is of interest to minimize input referred noise or to maximize gain, preserving an extremely low power consumption, are battery powered ones. Modern implantable medical devices for example, where power consumption is critical, are either powered by 2.8V (nominal) lithium-iodine batteries like in the case of pacemakers, or by 3.7V (nominal) rechargeable lithium batteries. The batteries that are employed for example to power radio-frequency mobile communications devices where a low noise amplifier may be valuable to implement the receiver, or to power data loggers where a low noise amplifier may be valuable for a wide range of sensor devices, also have a similar voltage range. According to the previous analysis a first approach to achieve a lower power consumption in a circuit like the one in Figure 1 or a similar one, is to realize an efficient voltage reduction of the battery voltage of for example Vs_at = 3.7V by means of a DC-DC converter, to derive a much lower V D of for example 1.2V or 0.6V to efficiently power the amplifier. However, DC-DC converters are not very efficient themselves if the current consumption is low. In the case of implantable electronics, charge pump type DC-DC converters are normally employed if the current consumption is in the micro-Amperes order. But in this case several external components in addition to the integrated circuit (IC) are required, as well as the corresponding PADs (a PAD is a connection node from the IC to the outside of the circuit). For example in the case of a divide by four converter VDD-

5 capacitors and 9 PADs are required. The result is an IC with a large circuit area, and with a power efficiency far from the ideal 100%. If a DC-DC converter is not employed, the circuit in Figure 1 will operate without any problem for example with P¾D=3.6V, but it will consume several times the minimum power necessary to achieve a given noise performance. For example a typical saturation voltage for a MOS transistor in a modem technology is around 200mV, and VGS is around 400mV at Weak Inversion, thus minimum V_DD may be as low as IV (leaving a reasonable margin for the signal at the output) which would reduce power consumption by a factor of 3.6 comparing to 7/¾DF3.6V. But even if the circuit in Figure 1 is powered with a V_DD as low as IV, less than one third of the energy is dissipated by Mi transistors, and there is still available room to further reduce power consumption.

Summary of the invention

The objective of the invention here presented is to implement efficient amplifiers. In these most of the energy is dissipated in the input transistors that carry out the voltage to current conversion, not in those transistors that are just used to bias the circuit or in current mirrors. These amplifiers should be current biased to preserve a precise operating point, a large CMRR (common mode rejection ratio), and a large PSR (power supply rejection ratio). The objective of the invention is to develop amplifiers where most of the consumed battery power, is dissipated by those current biased input transistors that effectively carry-out the amplification task, and not in biasing transistors. In these amplifiers, multiple input transistors M, will operate with a drain to source voltage Vost close to their saturation voltage V _SM, even in the case the supply voltage is equal to a typical battery voltage. To achieve the objective, the present invention proposes to stack successive differential pairs to reutilize the same bias current from the battery, either combined with efficient current sources able to operate with few tens of mV voltage drop.

Current reuse is at least mentioned in "A Sub-Microwatt Low-Noise Amplifier for Neural Recording", J.Holleman, B.Otis, 29th Annual International Conference of the IEEE-EMBS, pp.3930-3933, August 2007, but the amplifier proposed there is just a single MOS inverter operated like an analog amplifier, instead of a current biased differential pair. There are also several references and patents, most of them related to memory sense amplifiers, that use a single PMOS differential pair stacked with a single NMOS differential pair like for example U.S. patent 4,769,564, U.S. patent 5,936,466, U.S. patent 6,118,318 or U.S. patent U.S. 6,642,790, all of them describe very similar circuits and the latter at least recognizes that this topology is effective to achieve a high gain with a low current consumption. This kind of NMOS-PMOS stacked topology is sometimes referred as a 'complementary differential pair', and is not recognized as a valuable circuit to reduce input referred noise or input referred offset.

The amplifiers described in the above mentioned patents, are only partially biased by a current source, and the gate of the NMOS and PMOS transistors are connected together which strongly limits the input common mode of the amplifier and the minimum power supply voltage. In effect, a large VDD is necessary to power a complementary differential pair if the gate of the NMOS and PMOS transistors are connected together because VDD must be larger than VGSN plus VGSP plus the voltage drop of any current source to bias the transistors (VGSN and VQSP are the gate to source voltage of the NMOS and PMOS input transistors respectively). The use of complementary differential pairs reutilizing the supply current is limited because of this reason, the amplifier described in U.S. patent 7,135,927 for example uses different current sources for two complementary differential bipolar pairs with the same input. The present invention combines a capacitor on each gate of the input transistors of a current biased complementary differential pair to decouple the input, making it possible the operation of the complementary pair with a very low supply voltage. Finally, in all the examined patents and scientific papers the use of a single complementary pair is proposed, while the present invention claims the use of several stacked differential pairs to take full advantage of current reutilization for a given V_DD. If for the same supply voltage V_DD, three complimentary differential pairs are stacked to reutilize the bias current instead of a single one, the amplifier will result three times more efficient. The method can be extended to K stacked stages reutilizing the bias current.

A complementary differential pair (a PMOS pair plus an NMOS pair connected by their drains) with independent inputs (NMOS and PMOS gates are not connected) results in fact in a so-called differential difference amplifier where its output is a certain gain multiplied by the difference of the differential inputs of each pair. However, independent differential pairs are regularly used to implement differential difference amplifiers thus the bias current is not reutilized. Two differential pairs (each one biased by its own current source) are used for example in U.S. patent 6,996,435 to implement a state of the art low noise amplifier for electroneurograph signal recording (ENG) in implantable medical devices. This patent reports a power consumption of several milliamperes for the complete amplifier, but a power consumption two orders of magnitude lower would be desirable in the application to avoid frequent battery recharges. In Figure 1, the current source biasing the differential pair is a single MOS transistor M₃, but in the U.S. patent 6,996,435 differential pairs are biased by means of high output impedance cascode current sources. Current sources with a high output impedance are required to achieve a large CMRR as needed in ENG recording, but cascode current sources require a much larger minimum voltage drop to operate (and thus much more power). Instead, to bias the differential pair in an optimum amplifier, a current source with a very high output impedance but also a very low operating voltage for a minimum power consumption while preserving the overall CMRR and PSRR characteristics should be employed.

To reduce the voltage drop in the current source while preserving its large output impedance, the present invention proposes to use different active current sources including a pass transistor operating either in saturation or in the linear region to bias the differential pairs in a differential amplifier.

Brief description of drawings

Fig.l : Is the schematic of a classic differential CMOS pair input stage, representing prior state of the art for several applications.

Fig.2: Is an amplifier stage according to the present invention, with a differential voltage input, and a differential output current, composed by an NMOS differential pair biased with a current source, and a PMOS differential pair also biased with a current source. Both pairs are stacked and connected by their drains to make the best use of the current through the circuit branch.

Fig.3: Is an amplifier where the current sources of Figure 2 have been substituted by transistors, and a current to voltage conversion is carried out by a resistor at the output. An operational amplifier fixes the common mode voltage at the output. Fig.4(a): Is a preferred embodiment of the invention, where capacitors are connected to decouple the gate voltage of each input transistor.

Fig.4(b): Is a circuit diagram showing a possible method to establish the DC voltage of the gate of the input transistors, using diodes that are connected to a reference voltage. Note that since the voltage drop across the diodes tends to zero, the diodes represent a extremely large impedance for small signal calculations.

Fig.5 (a): Is a circuit containing several differential stages like the one in Figure 4(a), stacked to reuse the bias current in a very efficient way. A common mode feedback loop (CMFB) is included on each stage to guarantee the common mode voltage at the output. CMFB loop plays the role of the operational amplifier in Figure 3, but in a more efficient manner.

Fig.5(b): Is a second stage of the amplifier, to sum the output of the stacked differential stages of Figure 5(a).

Fig.5(c): Is a picture illustrating the advance of the present invention when compared to current state of the art: on the left two amplifiers require each 600μΑ current from the battery to achieve a given performance, in the center both are combined like in Figure 2 and only 300μΑ current is needed to achieve the same performance, finally on the right three stages like the one in the center of the picture are stacked to make efficient use of the supply current and only ΙΟΟμΑ current is now required. The technique of the invention can be extended for K stacked differential pairs of any type.

Fig.6: Is a representation of two possible applications for the amplifier of the invention: first an electrode is connected at the input to amplify biopotentials in an implantable medical device, secondly an antenna is connected at the input of the first stage in a wireless receiver.

Fig.7: Is a circuit diagram for the CMFB block and the current source in a complementary differential pair like those stacked in Figure 5(a), both implemented with a single pass transistor and a feedback transconductor.

Fig.8: Is a possible realization of a dual output (sink/source) current source as needed to reutilize the current in the circuit in Figure 5(a).

Fig.9(a): Is a current source connected to ground, composed by a sense resistor, a feedback OTA, and a MOSFET pass transistor. The current source has a voltage input Vc_tri to control the output current, and is able to operate at a very low voltage but showing at the same time an extremely large output equivalent resistance.

Fig.9(b): Is the current source of Figure 9(a) but adapted to provide a dual current output. This current source can be employed to interconnect stages as in Figure 5(a).

Fig.10: Is a differential amplifier stage like the one in Figure4(a) able to be stacked like in Figure 5(a), but several switches have been incorporated to periodically fix the DC gate voltage of the transistors (and eventually to adjust the amplifier's offset). CMFB loop is also shown. Fig.11 : Is the result of a computer simulation, of an amplifier according to the present invention with electroneurograph (ENG) specifications. The simulated amplifier is composed of K = 5 stacked complementary differential amplifiers. Each stage is like the one in the upper left of the picture. The inputs are decupled by means of an RBC;,, circuit to obtain a high-pass characteristic (RB is the dynamic resistance of the diodes connected as in Figure 4(b)). The total current consumption is 20μΑ from a 3.6V battery, the simulated input referred noise is just 4nV/VHz at lkHz frequency.

Detailed description of the invention

Figure 2 shows a basic differential amplification block according to the present invention. The amplifier has two inputs J½₊ y Vm-■ It is composed by two opposite, stacked, MOS differential pairs. One is a NMOS pair constituted by M_la y M_\b, and the other is a PMOS pair constituted by M2_a y Μ_¾. The output of the amplifier is a differential current, given by the difference between the currents I_a and h in the picture. The small-signal output current lou_t is defined:

) 0)

Equation (3) assumes that both NMOS and PMOS transistors are biased in the same inversion level, ideally both in Weak Inversion to minimize the input referred noise. Thus g_ml « g_m2 = g_m . The circuit is very efficient because the four transistors amplify the input signal in a cooperative way, but the four transistors introduce no-correlated noise to the circuit. So the input referred noise is reduced because it is divided by the gain. In the case of thermal noise it can be calculated:

S_Vjn(f) is the equivalent amplifier's input referred noise voltage PSD, while S_lx(f) is the noise current PSD introduced in the circuit by each transistor M_x (in a first approach all S_lx(f) are supposed to be equal). The last term in equation (4) applies only for thermal noise. But the term in the middle of equation (4) does not assume a specific noise type, thus the circuit in Figure 2 results very efficient not only to minimize thermal noise but also to reduce flicker noise. An equation analogous to (4) can be written for the input referred offset due to random mismatch between transistors. The advantages of the circuit in Figure 2 come from the elevated total transconductance over supply current ratio of the amplifier. It should be pointed that regardless of the bias current and transistor size, the maximum tranconductance over drain current ratio that

σ

can be achieved for a single transistor is— * 25 when it is biased in Weak Inversion.

Thus for a given bias current, the input referred noise is divided by a factor of 2 or 4, when comparing equations (4) and (2) depending on whether the mirrors M₂ in Figure 1 are biased in strong or weak inversion respectively. Furthermore, all the transistors in Figure 2 including those implementing the current sources can be biased in Weak Inversion showing a reduced saturation voltage, allowing the operation of the circuit at a very low supply voltage.

For a better comprehension of this first element of the invention, Figure 3 shows the amplifier block of Figure 2, but the current sources have been substituted by a current mirror M₃ to bias the NMOS differential pair, and a current mirror M4 to bias the PMOS differential pair. Also a current to voltage conversion is carried at the output by two resistors R 1, connected as in the paper "Low noise amplifier for recording ENG signals in implantable systems", J.Sacristan and M.T.Oses, Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS'04, vol.IV, pp.33-36, May 2004. This amplifier has an output voltage V_out as shown in Figure 3. An operational amplifier 2 is connected to the middle node of the output resistors to set the common mode voltage at the output, compensating in this way any mismatch between the current sources M₃ and M4. The operational amplifier (Oparnp) guarantees that the common mode voltage at the output (apart of a residual random mismatch offset) will be equal to VcM_Ref, a reference voltage in the positive input of the Opamp. M₃ current, and M4 current are both derived by means of current mirrors from a single current reference 3, 20 times lower than ΙΒ^. This value was arbitrarily selected to make negligible the power consumption by any circuit branch different than that of the differential pairs. Because it is not possible to guarantee that the current through the NMOS differential pair is exactly the same than through the PMOS differential pair, the common mode voltage at the output must be controlled in some way. If it is not controlled, the drain voltage of M_la, M_2a transistors 4, and the drain voltage of Mi_b, M_2b transistors 5, either will drop until the NMOS pair is no longer saturated or will rise until the PMOS pair is no longer saturated. The amplifier will not properly work on this condition. Although it is not very power efficient, the circuit in Figure 3 is a possible realization to control the common mode voltage at the output. An efficient common mode control loop will be proposed later in the description of the invention.

Another difficulty that appears when the amplifier in Figure 2 and Figure 3 is operated at a very low supply voltage VDD, is the limited common mode range at the input because the gates of Mi and M₂ transistors are connected together. Common mode range at the input can be even non-existent for a low VDD as the gate to source voltage VGSI of the Mi transistors will be much higher than the saturation voltage Vosati of the same transistors; and the gate to source voltage VQS2 of the M₂ transistors will be much higher than the saturation voltage Vo_Sat2 of the same transistors.

Figure 4(a) shows an amplifier block like the one in Figure 2, but the input transistors gates have been decoupled by means identical capacitors Cj„. It is necessary to initially fix the gate voltages V_Gi_a (6), V_Gib (7), VG2O (8), Vo2b (9), of each input transistor M_la, M^, M_2a, M_2b, respectively to an appropriated value. The voltage fluctuations at the input of the amplifier will appear also in the gate of each transistor but with smaller amplitude given by the capacitive divider:

W_Gxb = AV_ln+ ^■ -^— AV_Gxb = AV_In_^■ (5) where CG_X is the total gate capacitance of each corresponding M_x input transistor. So C_IN should be selected as large as possible in comparison to CG_X value, to reduce the capacitive divider effect, particularly if we also take into account the Miller effect. The circuit in Figure 4(a) however, still requires some changes because in a real situation it will not be enough to adjust the voltage of the floating gate nodes 6, 7, 8, 9 only once when the amplifier is turned on. In effect the capacitors will be discharged because of leakage currents, thus it is necessary to control the DC voltage of nodes 6, 7, 8, 9 or at least to periodically adjust the voltage of nodes 6, 7, 8, 9. In Figure 4(b) a preferred embodiment of the invention is shown, with opposite diodes connected to a reference voltage (in this case obtained from a resistive voltage divider) to fix the DC gate voltage of the input transistors. This so-called clamping diodes in figure 4(b) have an extremely large equivalent resistor (small signal analysis) enabling the amplification of even very low frequency signals. The diodes in Figure 4(b) can be substituted just by resistors if the frequency of the signal to amplify is large, or the nodes 6, 7, 8, 9, can be connected by means of switches to periodically adjust their voltage. This periodic adjust can be either combined with the process known as Autozero mentioned in "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", C.C.Enz and G.C.Temes, Proceedings of the IEEE, vol.84, n°l l, pp.1584-1614, November 1996. The Autozero process consists in disconnecting the input signal of the amplifier at regular time intervals, where the amplifier's inputs are short-circuited and a voltage is adjusted and subtracted at the input to null the output, effectively canceling the amplifier's input referred offset. This process will be further discussed when describing Figure 10.

The circuits in Figure 2, Figure 3, and Figure 4 are very efficient because the current of the differential PMOS pair is reutilized to amplify again with a differential NMOS pair. To further exploit the reutilization of the supply current to the limit imposed by the supply voltage VQD, in a preferred embodiment of the invention successive complementary differential pairs are stacked. An amplifier that reutilizes the bias current in a very efficient way is shown in Figure 5(a). Three amplifiers are stacked in Figure 5(a), each one composed by complementary connected differential NMOS and PMOS pairs 10, 11, 12, but in general a larger number of stages can be stacked. In a preferred embodiment of the invention, all the differential stages are like the one in Figure 4(a), biased through the current sources 13, 14, 15, 16. The input voltage ( Vm+ - VIM- ) is the same for all the stacked stages, their gates being decoupled through identical capacitors. Because the successive differential stages are stacked, there is no need to reduce the supply voltage to achieve the maximum possible power efficiency. Note the invention is not limited to the specific stack of complementary differential stages, and different types of differential amplifier pairs/stages can be stacked (for example differential pairs using bipolar transistors, or all-NMOS or all-PMOS differential pairs) to reutilize the current from the battery if the adequate bias scheme is provided. The circuit in Figure 5(a) is only a particular embodiment of the invention, and the scheme where several differential amplifier stages are stacked to power them with the same supply voltage can be applied for a wider range of unitary differential amplifiers, with either a current or a voltage output. Finally note the method can be extended also to save power in circuits different than amplifiers, for example filters with a given transfer function but a gain no necessarily > 1. Successive stages of a filter can be stacked to reutilize the bias current, the output of one of the stacked stages becoming the input of the next.

Figure 5(a) is a preferred embodiment of the invention, where all the staked amplifying stages are as the one in Figure 4(a). For the three stacked stages, each differential output voltage will be referred to as V_0uti, Vo_ut2, Vo ts, for the output of stages 10, 11, 12 respectively. Therefore Voutx denotes the differential voltage between the drains of M_la and Mib transistors both of which are connected to the drains of M_2a and Μ_¾ according to Figure 4(a). To obtain a single output for the amplifier in Figure 5(a), the output voltages V_0uti, Vo 2, Vout3, are summed in a second stage as shown in Figure 5(b). Because the signal at the input of this second stage has been previously amplified by the first stage, it has much relaxed input referred noise requirements than in the case of the first stage of Figure 5(a). So the power consumption of this second stage can be, with an adequate design, several times lower than the power consumption of the first stage.

In a general case the amplifier block in Figure 5(a) has K stacked differential amplifiers, and a single differential input ( V_IN+ - V_®. ). Assuming that all the transistors of the complementary differential amplifiers are biased in the same inversion level (ideally in Weak Inversion to minimize thermal noise), all the gate transcoductances will be equal. The circuit is very efficient because the 4-K transistors amplify the input signal in a cooperative way, but the 4-K transistors introduce non-correlated noise to the circuit. So the input referred noise is reduced because it is divided by the gain. In the case of thermal noise it can be calculated:

{2 - K - g_ml) K - g_m

In equation (6) S_Vin (f) is the equivalent noise voltage PSD at the amplifier's input, while S_lx(f) is the noise current PSD introduced in the circuit by each transistor M_x ( in a first approach all S_lx(f) are supposed to be equal). The last term in equation (6) applies only for thermal noise, but the term in the middle does not assume a specific noise source, thus the circuit in Figure 5(a) results very efficient not only to minimize thermal noise, but also to reduce flicker noise, and an equation analogous to (6) can be written also for the input referred offset due to random mismatch between transistors.

The advantages of the circuit in Figure 5(a) come from the elevated total transconductance over supply current ratio of the amplifier. It should be pointed that regardless of the bias current and transistor size, the maximum tranconductance over drain current ratio that can be achieved for a single transistor is— « 25 when it is biased in Weak Inversion. Thus for a given supply current, the input referred noise is divided by a factor of 2-K or 4-K, when comparing equations (6) and (2) depending on whether the mirrors M₂ in Figure 1 are biased in Strong Inversion or Weak Inversion respectively. Furthermore, all the transistors including those composing the current sources in Figure 5(a), can be biased in weak inversion to obtain a reduced saturation voltage, allowing the operation of the circuit at a very low supply voltage or the addition of more stages for a given supply voltage.

Current sources connected to ground or VDD are usual circuit blocks in CMOS technology, but to build the circuit in Figure 5(a) it is necessary to implement dual current sources like 14, 15. In this document a 'dual current source' denotes a circuit block connected between two nodes A, B such that the current entering through node A and the current through node B have the same absolute value and opposite sign, independently of the voltage of each node within a certain operating range. A dual current source has also an input voltage to control the absolute value of the output current. The current sources necessary to implement the circuit in Figure 5(a) ideally should not consume any additional power, however in a real case some additional power consumption will be necessary. The current sources necessary to implement the circuit in Figure 5(a) ideally should operate at a voltage drop V B = (VA -V_B ) close to zero, but in a real case tens to hundreds mV VAB will be necessary. A minimum VAB is preferred because the number K of stages to stack in principle is limited only by the stacked saturation voltage of the transistors of the differential pairs, the stacked minimum operating voltages ( VAB ) of the current sources in Figure 5(a), and a certain voltage excursion at the output; the sum must be less than VDD-

A scheme is shown in Figure 5(c) to further illustrate the benefits of the present invention in comparison to prior state of the art amplifiers. Two conventional amplifiers using a single differential pair either NMOS or PMOS require separately I D = 600μΑ each from the supply voltage to amplify with a given input referred noise floor. If both amplifiers are combined (by connecting them in series) into a single one powered by a single supply voltage to reuse the bias current like in Figure 2, only half the supply current is needed. Finally on the right, three amplifiers are stacked in series to be powered by a single supply voltage like in Figure 5(a), and only a IDD ~ ΙΟΟμΑ supply current is necessary to achieve the initial input referred noise performance. The proposed method can be applied to an arbitrary number K of stacked stages provided all the differential pairs are saturated for the selected VDD-

Two possible applications for the invention are shown in Figure 6. First an amplifier for biopotentials that is part of an implantable medical device where ultra low power consumption is mandatory. An electrode is connected at the amplifier's input; the amplifier's output is connected to an AD converter or detection circuitry of the medical device. The proposed topology is an advance in comparison with, for example, the state of the art amplifiers described in U.S. patent application 0155966 Al, or the amplifier described in the U.S. patent 6,996,435 that do not employ stacked amplifiers or complementary differential pairs to amplify signals thus resulting in a much higher power consumption. In the same picture a second application is shown: the amplifier of the invention as part of a wireless communications receiver. In this case an antenna is connected a the input, or in the case of radio-frequency identification at low frequency (LF-RFID) a simple inductive coil can substitute the antenna. In the case of very high frequencies, a resonant network can substitute the resistors R of Figure 3, but the working principle is the same. By stacking differential pairs, the amplifier of the invention allows to implement efficient low-noise, low-power receivers or transceivers for mobile communications, active RFID tags, among other battery powered applications.

While the current source biasing a differential pair in a classic amplifier like the one in Figure 1 is a simple MOS (M₃) transistor, a more complex dual current source (able to sink/source current from both terminals) is necessary to connect the stacked complementary amplifiers shown in Figure 5(a). A possible solution to implement the dual current source is shown in Figure 7, consisting in a feedback transconductor G_MFB connected to the gate of a pass transistor MFB to fix the output common mode voltage to a voltage reference J¾ . In this way not only the common mode voltage at the output is controlled, but also the current through MFB is made equal to hias , the bias current of the upper differential pair. The circuit composed by G_MFB and MFB in Figure 7, implements both the CMFB block and the lower current source of a single stage of the amplifier of Figure 5(a). Because the MFB transistor may operate even in the linear region the voltage drop in MFB can be extremely low, for example as low as 50mV. So the circuit is particularly adequate for the invention in Figure 5(a). The scheme in Figure 7 resembles the topology of the circuits presented in the U.S. patent 4,769,564, U.S. patent 5,936,466, U.S. patent 6,118,318 or U.S. patent U.S. 6,642,790 all of them using a single complementary MOS differential pair, but these circuits are not biased from a reference current them are self biased instead. Also in these circuits a feedback transconductor is not connected to the pass transistor, thus the output common mode voltage can not be arbitrarily selected to allow the stack of successive amplifying stages. Also the amplifiers on these patents do not consider capacitors to decouple transistors' gates like in Figure 4 and Figure 5(a). Since it is a well known fact that precision OTAs (a transconductors will be denoted as OTA = operational transconductor amplifier) can be realized consuming as little as few tens nA, G_MFB can be powered directly from the supply voltage VDD without a significant increase of the overall circuit power consumption.

Even though the circuit in Figure 7 is enough to implement the invention, Figure 8 shows another possible realization for a current source to connect stacked differential amplifiers, like the sources 14, 15 in Figure 5(a), independently of the CMFB block. The circuit in Figure 8 is a l:N NMOS mirror with dual outputs, where N>>1 is assumed (N=20 for example). The current reference 7^/ enters trough the NMOS on the left and is copied to the output transistor. I_Ref is several times lower than the output current to minimize the power consumption as the reference current is connected directly to the supply voltage VDD- The main current branch between nodes A and B in Figure 8, may connect the stacked differential stages of Figure 5(a). A CMOS technology including an isolated P-Well is necessary in this realization of this current source using NMOS transistors, to avoid the so-called 'body effect' since both source and drain of the transistors are connected to an arbitrary voltage. Because a control voltage V n is necessary to adjust the output current, an extra transistor Mctri is included. The gate voltage of Mc_tri is used to control a current that is summed to The outputs I_A , I_B in Figure 8 are related to Va_ri as follows: I_A - N- {l_Ref + I_Ctrl) ;

I_B = (N + l)- (l_Ref +I_ClrI ). The current source in Figure 8 results adequate for the circuit of Figure 5(a) but is necessary, during the amplifier design, to consider the differences between the sink and source currents I A and as each differential stage in Figure 5(a) will be biased by a slightly different current. However, the main problem with the current source in Figure 8 are its poor output impedance, and that it requires a relatively large voltage drop VAB to operate (around 200mV or larger) because the output transistor must be saturated. The reduction of the output impedance results in a poor common mode rejection ratio (CMRR) that is an important characteristic of amplifiers. An improved current source should operate with a voltage drop VAB lower than the saturation voltage of a single transistor, guarantee that the current I_A and IB for both nodes A and B have the same absolute value, and present the largest possible output impedance.

The circuit in Figure 9(a) shows a preferred current source for the amplifier of the invention. The current source is composed by a sense resistor Rs, a MOS pass transistor MR in series, and a feedback transconductor G„,FB that controls the impedance of MR SO that the voltage drop in R_s results equal to a control voltage Van- Because the transistor MR can operate in its linear region, the voltage of A can be very low. In a typical example Vctri can be selected as 30mV so that results much larger man the input offset voltage of GmFB- Since precision OTAs can be realized consuming as little as few tens nA or less, GmFB can be powered directly from the supply voltage VDD without a significant increase of the overall circuit power consumption. The output impedance of the current source in Figure 9(a) is very high particularly at low frequency, because it does not depend on the output impedance of MR. G_mFB transconductance, MR size, and Vc_tri, can be selected according to output impedance, power consumption, and other specifications. The current source of Figure 9(a) can be utilized instead of the grounded current source 13 in Figure 5(a). In Figure 9(b) a floating dual current source, using the same principle of Figure 9(a) is shown. The current source of Figure 9(b) can be utilized instead of the current sources 14, 15, in Figure 5(a). In this case the feedback OTA G_mpB has been substituted by a dual differential input OTA. G_mFB in Figure 9(b) has an output current of the form: I_FB = G_mFB ^V_R+ - V_R_)+ (- V_Ctrl)] . A feedback loop is established such that I_pg -» 0 and both currents from nodes A and B are: I_0ut = V_Ctrl/R_s .

To further illustrate a possible realization of the invention, a more complex version of a single differential amplifier stage of Figure 5(a) is shown in Figure 10. The stage includes appropriate switches to periodically adjust the voltage of the input transistors' gates, and to implement the so-called 'Autozero' technique to guarantee minimum offset and minimum low frequency noise. Autozero technique consists in periodically sampling offset and noise that is later subtracted at the input. During regular signal amplification, switches 17, 18, 19, 20, in Figure 10 are open and the signal to amplify is connected to the inputs VIM- and VIN₊ through the switches 21 that are closed. To implement the Autozero, the signal to amplify is periodically disconnected from the amplifier's input (switches 21 are opened), both inputs are short-circuited to a reference voltage VCM through the switches 20, and then the gates of the four input MOS transistors are connected to a proper voltage NRef A and VR_ef_B by closing the corresponding switches 17, 18. A small time interval later, switches 17 and 18 are opened and switches 19 are closed, so the transconductor Gm2 delivers the necessary current to charge gates of the transistors on the left to null the output voltage. Finally, switches 19 are opened and the signal to amplify is reconnected again to the input. The OTA G_ml in Figure 10 controls a current source, preferably one like in Figure 8, Figure 9(a) or Figure 9(b). It should be pointed that Figure 10 is a possible realization of the invention but not the only. In a different realization it is only necessary to guarantee in some way an appropriate operating voltage of the nodes equivalent to 6 7 8 y 9 of Figure 4(a), without introducing a significant excess noise at the input nodes.

Other circuit techniques can be independently employed or combined with the Autozero to minimize noise. For example to subtract at the output a noise sample immediately after the Autozero phase (this technique is known as Correlated Double Sampling - CDS). Or in the case of a band-pass amplifier, all the Autozero circuitry can be substituted just by a resistor, or just by diodes connected to a reference voltage like in Figure 4(b). Note the diodes in Figure 4(b) in fact play the role of an extremely large resistor. But the Autozero amplifier in Figure 10 guarantees the operation up to DC. It should be remarked also that the present invention is compatible with Chopper circuit technique to reduce offset and flicker noise, which can be easily implemented if the amplifier's inputs VIN- and VIN₊ are periodically exchanged. To periodically exchange the inputs means to alternatively swap the positive and negative connection of the input signal to the amplifier. The tutorial in "Circuit techniques for reducing the effects of op- amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", C.C.Enz and G.C.Temes, Proceedings of the IEEE, vol.84, n°l l, pp.1584-1614, November 1996 examines in detail Autozero, Chopper and CDS that are known techniques that can be applied to the amplifier of the invention.

To demonstrate a realization on the invention for a specific application, a computer simulation of a complete differential amplifier like the one in Figure 5(a) is shown in Figure 11. The purpose of the circuit is to amplify electroneurograph signals (ENG), in the frequency span of 100 to 10kHz. ENG signals have very low amplitude, as low as ^ RMS, which require the use of very low noise amplifiers. This application fits the scheme of Figure 6; ENG signals are registered by using proper differential electrodes. The amplifier of the invention can help develop more efficient medical devices as ENG signal recording is being incorporated in novel active medical implants. In the case of Figure 11, five stacked complementary differential pairs K = 5) were used, all the PMOS and NMOS transistors are biased in weak inversion with a total bias current htas - 20μΑ. Decoupling capacitors of 150pF, and floating diodes like in Figure 4(b) connected to a resistive voltage divider are used to establish an adequate bias voltage in the gates of the transistors. To simplify the understanding of the circuit in Figure 11, the diodes pairs are represented like resistors R_B. RB represent the hundreds ΜΩ small signal equivalent resistor of the diodes. The current sources in Figure 11 are like the one in Figure 9(a) and Figure 9(b), where each transconductor consumes only 300nA current from the battery to make the total current consumption of the sources, negligible in comparison to the overall current consumption of the amplifier. The output common mode feedback (CMFB) is implemented with a transconductor like in Figure 7, but Autozero like in Figure 10 is not applied. On the bottom of Figure 11, the simulated gain-frequency plot of amplifier is shown, as well as a scheme of the stacked differential stages on the right. The total current consumption of the circuit including the five complementary differential pairs and all the OTAs for CMFB and current sources, is less than 30μΑ from a VDD - 3.6V battery (the nominal voltage of a usual rechargeable battery). The input referred noise voltage in the band from 100 to 10kHz is just 4nV/VHz. The bandwidth of the plot in Figure 11 is several times higher than needed, thus the present invention shows to be valuable also to implement high frequency and low power amplifiers. For the ENG application also a band-pass and a summing second stage like in Figure 5(b) should be implemented.

Having described the preferred aspects of the invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit of the scope thereof.

Claims

What is claimed is:

#1) A differential amplifier comprising:

(a) Several complementary differential pairs (each one composed by an NMOS differential pair and a PMOS differential pair connected by their drain terminals), stacked to be powered by the same supply voltage to reutilize the bias current. The current biasing the upper stacked differential pair is used to bias the second differential pair that also provides the current for a third, and so on.

(b) A second amplification stage to sum the current or voltage output of the stacked complementary differential pairs.

(c) Several current sources, and common mode feedback blocks that are necessary to properly bias the stacked differential amplifiers.

#2) A differential amplifier with the objective of reducing to the minimum possible the voltage drop in the transistors that do not effectively amplify the signal comprising:

(a) Several unitary differential amplifier stages of any type (either implemented with bipolar transistors, NMOS or PMOS only differential pairs, among other possibilities), stacked to be powered by the same supply voltage to reutilize the bias current. The current biasing the upper stacked differential pair is used to bias the second differential pair that also provides the current for a third, and so on.

#3) A differential amplifier comprising:

(a) A first NMOS differential pair biased with a current source.

(b) A second PMOS differential pair biased with a current source connected in series with the first pair by the respective drain terminals to reutilize the bias current.

(c) A differential output current from the connected drains.

#4) The differential amplifiers of claim 1 , claim 2, and claim 3 wherein the use of an electrode or electrode array connected at the input, allows for the very efficient amplification of biopotentials in implantable and other battery powered medical devices.

#5) The differential amplifiers of claim 1, claim 2, and claim 3, wherein the connection of an antenna at the input, allows for the construction of a very efficient amplifier in medium and high frequency range signals, in the first stage of a radio communications receiver or a radio frequency identification transponder.

#6) The differential amplifiers of claim 1, claim 2, wherein the stack of transistors allows for an efficiency improvement regarding input referred noise against power consumption ratio, input referred offset against power consumption ratio, amplifier's gain against power consumption ratio, in one of the following applications: implantable medical devices and other battery powered medical devices, signal processing of sensors in data loggers and mobile equipment, radio frequency (RF) amplifiers. #7) The use of multiple capacitors connected to the input signal and to the gate of each input transistor in a multiple input differential amplifier like the ones of claim 1, claim 3, to decouple the input signal to allow the adjustment of the direct current (DC) voltage of the transistors' gates at a voltage different than the input.

#8) The differential amplifiers of claim 1, claim 2, claim 3, including the decoupling capacitors of claim 6, wherein the gate voltage of the MOS transistors is connected either

(a) To a fixed voltage by means of a high impedance resistor, reverse biased diodes, MOS transistors, among others.

(b) To a certain voltage that is periodically adjusted to cancel input referred mismatch offset, constituting in fact the Autozero technique applied to the amplifiers in claim 1, claim 2, and claim 3.

(c) To an input that is modulated at a much higher frequency to be demodulated back after amplification in order to minimize input referred flicker noise and offset, constituting in fact the Chopper technique applied to the amplifiers in claim 1, claim 2, claim 3.

#9) The utilization of a very low voltage current source to bias the differential amplifiers of claim 1, claim 2, claim 3, with a large output impedance comprising: a pass transistor operating either in saturation or in the linear region to control current flow, connected in series to a resistor to sense the current, and a feedback transconductor amplifier with its inputs connected to the sense resistor and to a reference voltage and its output connected to the gate of the pass transistor, in order to fix the current to a desired value.