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WO2012006766A1 - Structure semiconductrice et procédé de fabrication de celle-ci - Google Patents

Structure semiconductrice et procédé de fabrication de celle-ci Download PDF

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Publication number
WO2012006766A1
WO2012006766A1 PCT/CN2010/001498 CN2010001498W WO2012006766A1 WO 2012006766 A1 WO2012006766 A1 WO 2012006766A1 CN 2010001498 W CN2010001498 W CN 2010001498W WO 2012006766 A1 WO2012006766 A1 WO 2012006766A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
forming
sidewall
local interconnect
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2010/001498
Other languages
English (en)
Chinese (zh)
Inventor
朱慧珑
尹海洲
骆志炯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to US12/996,721 priority Critical patent/US8610275B2/en
Publication of WO2012006766A1 publication Critical patent/WO2012006766A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • a semiconductor structure comprising: a semiconductor substrate; a local interconnect structure connected to the semiconductor substrate; a via stack structure electrically connected to the local interconnect structure; wherein the via hole
  • the laminated structure comprises: a via hole, the via hole comprises an upper via hole and a lower via hole, wherein the width of the upper via hole is larger than the width of the lower via hole; the via sidewall wall is formed adjacent to the inner wall of the lower via hole; the insulating layer covers the via hole Forming a surface of the via sidewall; the conductive plug is formed in a space surrounded by the insulating layer and electrically connected to the local interconnect structure.
  • the width of the conductive plug Down from the side wall of the via, the width of the conductive plug is aligned with the inner wall of the side wall of the via, so that the width of the conductive plug can be defined by the spacing of the inner walls of the side wall of the via.
  • the via sidewalls may be formed of any one of SiO 2 , Si 3 N 4 , SiON, SiOF, SiCOH, SiO, SiCO, SiCON.
  • the conductive plug further includes a barrier layer and a conductive material; the barrier layer covers a surface of the insulating layer, and the conductive material is formed in a space surrounded by the barrier layer.
  • the barrier layer may be formed of a combination of one or more of TiN, TaN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru.
  • the conductive material may be formed of any one of ⁇ , Al, Cu, TiAl.
  • the step of forming the lower via and the via sidewalls may include: forming a dielectric layer on the local interconnect structure; using a first mask pattern on the dielectric layer to define a width of the upper via to be formed; Second mask pattern limit Determining the width of the lower via hole to be formed; using the second mask pattern as a mask, etching the dielectric layer downward to form a portion of the lower via hole by self-alignment; forming a via hole along the bottom inner wall of a portion of the lower via hole Side wall; using the via sidewall as a mask, further etching the dielectric layer to the local interconnect structure to complete the formation of the lower via.
  • the step of forming the upper via hole comprises: removing the second mask pattern, and etching the dielectric layer downward with the first mask pattern as a mask to form an upper via hole by self-alignment, wherein the upper via hole and the lower hole Vias are connected.
  • the semiconductor structure and the method of fabricating the same according to the embodiments of the present invention can realize self-alignment formation of via laminations, and can freely adjust the via size, avoid short circuits between the via holes, and improve the good yield of the device.
  • FIG. 1 is a schematic view showing a semiconductor structure fabricated according to a conventional process
  • FIGS. 11 and 12 illustrate a method of fabricating a semiconductor structure according to a first embodiment of the present invention. Manufacturing a completed semiconductor structure
  • FIG. 11 shows a method of fabricating a semiconductor structure according to a first embodiment of the present invention.
  • the semiconductor structure fabricated according to the proposed process of the present invention mainly comprises: a semiconductor substrate 100, a first dielectric layer 110 formed on the semiconductor substrate 100, and a second dielectric formed on the first dielectric layer 110.
  • a via stack structure 220 is formed in the second dielectric layer 210 to be electrically connected to the local interconnect structure 120.
  • the via sidewall spacer 224 may have a thickness of 5-100 nm, and the via 221 may have a bottom width of 30-500 nm.
  • the width of the conductive plug 226 is aligned with the inner wall of the via sidewall 224, and thus the width of the conductive plug 226 can be defined by the spacing of the inner walls of the via sidewall 224.
  • the via sidewall spacer 224 may be formed of any one of SiO 2 , Si 3 N 4 , SiON, SiOF, SiC0H, Si0, SiC0, SiCON.
  • the conductive plug 226 further includes a barrier layer 227 and a conductive material 228; the barrier layer covers the surface of the insulating layer 225, and the conductive material 228 is formed in a space surrounded by the barrier layer 227.
  • the barrier layer 227 may be formed of a combination of one or more of TiN, TaN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru.
  • the conductive material 228 may be formed of any one of Al, Cu, and TiAl.
  • the via holes in the embodiments of the present invention are formed by self-alignment.
  • the through-hole laminate on the left side has a shape similar to that of the via-hole stack on the right side in a direction perpendicular to the plane of the paper, and the width of the upper via hole is larger than the width of the lower via hole.
  • Figure 17 and Figure 18 are similar.
  • the semiconductor structure of the hole stack. 17 and 18 are semiconductor structures obtained in accordance with another embodiment of the present invention.
  • a local interconnect structure 120 is formed on a semiconductor substrate 100 including an IC device (not shown).
  • the local interconnect structure 120 can be completed by a damascene method by first depositing an ILD layer 110 on the semiconductor substrate 100 on which the device is fabricated, which may have a thickness of 100-300 ⁇ .
  • Undoped silicon oxide (SiO 2 ), various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si 3 N 4 ) may be used as the constituent material of the ILD layer 210. .
  • a polysilicon layer 310 is deposited on the semiconductor structure shown in FIG. 2 as a hard mask (HM) for the next level of interconnection.
  • Photoresist PR320 is then applied over polysilicon layer 310 and photoresist PR320 is patterned for the next level of interconnect.
  • other materials may be used as the hard mask, and those skilled in the art may select according to actual needs.
  • the polysilicon layer 310 is etched by a dry etching method using the patterned photoresist of FIG. 3 as a mask to form a hard mask as the next-level interconnection.
  • the dry etching method may be reactive ion etching RIE.
  • the ILD layer 210 is then etched to half or other depth using an RIE etch that is selective to polysilicon.
  • the etch depth can depend on the requirements of the via metal plug process.
  • the photoresist PR330 shown in FIG. 5 is removed.
  • spacer material 228 is deposited (5-50 nm is used to form the via side) Wall.
  • the sidewall material 228 may be formed of any one of SiO 2 , Si 3 N 4 , SiON, SiOF, SiC0H, Si0, SiC0, SiCON, or other materials may also be used.
  • a via stack as shown in Fig. 11 is formed using a conventional method.
  • the insulating layer 225 is formed, and a conductive plug 226 is formed in a space surrounded by the insulating layer.
  • the conductive plug may further include a barrier layer 227 and a conductive material 228 formed in a space surrounded by the barrier layer.
  • CMP polishing is performed and stopped at the ILD layer 210.
  • the polysilicon hard mask 310 is also removed together while the CMP is being performed.
  • Photoresist PR320 is then applied over polysilicon layer 310 and photoresist PR320 is patterned for the next level of interconnect.
  • the polysilicon 310 is etched by a dry etching method using a patterned photoresist as a mask to form a hard mask as a next-level interconnection.
  • the photoresist PR 320 on the patterned polysilicon layer 310 as a hard mask is removed.
  • the photoresist 310 formed after patterning is used as a first mask pattern for defining the width of the upper via.
  • another photoresist layer PR 330 using a self-aligned via is patterned.
  • Photoresist 330 is referred to as a second pattern mask for defining the width of the lower via. Then, using the second pattern mask, the ILD layer 210 is etched to the local interconnect structure 120 to be connected by reactive ion etching RIE, exposing the upper surface of the local interconnect connection 120 to be connected, thereby forming a lower Via 223. Then, as shown in FIG. 14, the photoresist layer PR330 is removed, and then sidewall material 208 (5-50 nm), such as a nitride or low-k material, is deposited. It should be noted that the deposited sidewall material 208 does not fill the entire via, but fills a portion of the via.
  • sidewall material 208 5-50 nm

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une structure semiconductrice et un procédé de fabrication de celle-ci. Le dispositif semiconducteur comprend un substrat semiconducteur (100), une structure d'interconnexion locale (120) connectée au substrat semiconducteur (100), une structure stratifiée de trous traversants (220) connectés électriquement à la structure d'interconnexion locale (120). La structure stratifiée de trous traversants (220) comprend un trou traversant (221), une paroi latérale de trou traversant (224), une couche d'isolation (225) et un bouchon conducteur (226). Le trou traversant (221) comprend un trou traversant supérieur (222) et un trou traversant inférieur (223). La largeur du trou traversant supérieur (222) est supérieure à celle du trou traversant inférieur (223). La paroi latérale de trou traversant (224) est adjacente à la paroi intérieure du trou traversant inférieur (223). La surface du trou traversant (221) et la paroi latérale de trou traversant (224) sont recouvertes par la couche d'isolation (225). Le bouchon conducteur (226) est formé dans un espace délimité par la couche d'isolation (225) et il est connecté électriquement à la structure d'interconnexion locale (120).
PCT/CN2010/001498 2010-07-14 2010-09-27 Structure semiconductrice et procédé de fabrication de celle-ci Ceased WO2012006766A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/996,721 US8610275B2 (en) 2010-07-14 2010-09-27 Semiconductor contact structure including a spacer formed within a via and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2010102320608A CN102339813A (zh) 2010-07-14 2010-07-14 半导体结构及其制造方法
CN201010232060.8 2010-07-14

Publications (1)

Publication Number Publication Date
WO2012006766A1 true WO2012006766A1 (fr) 2012-01-19

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CN (1) CN102339813A (fr)
WO (1) WO2012006766A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9754925B2 (en) 2013-12-19 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10269768B2 (en) 2014-07-17 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US10304818B2 (en) 2013-12-26 2019-05-28 Taiwan Semiconductor Manufacturing Company Method of manufacturing semiconductor devices having conductive plugs with varying widths
US11798916B2 (en) 2013-12-19 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method

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CN103971779B (zh) * 2014-05-21 2016-08-24 电子科技大学 一种小型中子源及其制备方法
US9455158B2 (en) 2014-05-30 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect devices and methods of forming same
US9502293B2 (en) * 2014-11-18 2016-11-22 Globalfoundries Inc. Self-aligned via process flow
KR102415952B1 (ko) 2015-07-30 2022-07-05 삼성전자주식회사 반도체 소자의 레이아웃 설계 방법, 및 그를 이용한 반도체 소자의 제조 방법
US9928333B2 (en) * 2015-07-30 2018-03-27 Samsung Electronics Co., Ltd. Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semicondutor device using the same

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9754925B2 (en) 2013-12-19 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10157891B2 (en) 2013-12-19 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10510729B2 (en) 2013-12-19 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US11798916B2 (en) 2013-12-19 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US12476224B2 (en) 2013-12-19 2025-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10304818B2 (en) 2013-12-26 2019-05-28 Taiwan Semiconductor Manufacturing Company Method of manufacturing semiconductor devices having conductive plugs with varying widths
US12381195B2 (en) 2013-12-26 2025-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US10269768B2 (en) 2014-07-17 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US10629568B2 (en) 2014-07-17 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US11923338B2 (en) 2014-07-17 2024-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US12482791B2 (en) 2014-07-17 2025-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines

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