KR20020086100A - 다층 배선의 콘택 형성 방법 - Google Patents
다층 배선의 콘택 형성 방법 Download PDFInfo
- Publication number
- KR20020086100A KR20020086100A KR1020010025815A KR20010025815A KR20020086100A KR 20020086100 A KR20020086100 A KR 20020086100A KR 1020010025815 A KR1020010025815 A KR 1020010025815A KR 20010025815 A KR20010025815 A KR 20010025815A KR 20020086100 A KR20020086100 A KR 20020086100A
- Authority
- KR
- South Korea
- Prior art keywords
- plug
- contact
- film
- interlayer insulating
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (2)
- 기판의 상부에 제1 배선층을 형성하는 단계,상기 제1 배선층을 덮는 층간 절연막을 적층하는 단계,상기 층간 절연막의 상부에 질화막을 형성하는 단계,상기 질화막 및 상기 층간 절연막을 패터닝하여 상기 제1 도전층을 드러내는 콘택 홀을 형성하는 단계,상기 콘택 홀의 내부에 베리어 금속층을 형성하는 단계,플러그용 금속막을 적층하는 단계,상기 베리어 금속층 및 상기 플러그용 금속막을 에치 백하여 플러그를 형성하는 단계,상기 질화막 제거하여 상기 층간 절연막을 드러내는 단계,상기 플러그를 통하여 상기 제1 배선층과 전기적으로 연결되는 제2 배선층을 형성하는 단계를 포함하는 다층 배선의 콘택 형성 방법.
- 제1항에서,상기 플러그는 상기 질화막 밖으로 돌출되도록 형성하는 다층 배선의 콘택 형성 방법.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010025815A KR20020086100A (ko) | 2001-05-11 | 2001-05-11 | 다층 배선의 콘택 형성 방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010025815A KR20020086100A (ko) | 2001-05-11 | 2001-05-11 | 다층 배선의 콘택 형성 방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020086100A true KR20020086100A (ko) | 2002-11-18 |
Family
ID=27704584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010025815A Ceased KR20020086100A (ko) | 2001-05-11 | 2001-05-11 | 다층 배선의 콘택 형성 방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020086100A (ko) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100815186B1 (ko) * | 2006-09-11 | 2008-03-19 | 주식회사 하이닉스반도체 | 돌출형상의 텅스텐플러그를 구비한 반도체소자의 제조 방법 |
| KR100831248B1 (ko) * | 2007-05-16 | 2008-05-22 | 주식회사 동부하이텍 | 반도체 소자의 금속배선 형성방법 |
| KR100850069B1 (ko) | 2006-12-27 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 제조 방법 |
| US11367651B2 (en) | 2019-07-18 | 2022-06-21 | Samsung Electronics Co., Ltd. | Semiconductor device |
-
2001
- 2001-05-11 KR KR1020010025815A patent/KR20020086100A/ko not_active Ceased
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100815186B1 (ko) * | 2006-09-11 | 2008-03-19 | 주식회사 하이닉스반도체 | 돌출형상의 텅스텐플러그를 구비한 반도체소자의 제조 방법 |
| US7615494B2 (en) | 2006-09-11 | 2009-11-10 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device including plug |
| KR100850069B1 (ko) | 2006-12-27 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 제조 방법 |
| KR100831248B1 (ko) * | 2007-05-16 | 2008-05-22 | 주식회사 동부하이텍 | 반도체 소자의 금속배선 형성방법 |
| US11367651B2 (en) | 2019-07-18 | 2022-06-21 | Samsung Electronics Co., Ltd. | Semiconductor device |
| US12165916B2 (en) | 2019-07-18 | 2024-12-10 | Samsung Electronics Co., Ltd. | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20010511 |
|
| PA0201 | Request for examination | ||
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20030213 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20031009 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20030213 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |