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WO2012043508A1 - Cellule solaire et son procédé de fabrication - Google Patents

Cellule solaire et son procédé de fabrication Download PDF

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Publication number
WO2012043508A1
WO2012043508A1 PCT/JP2011/071953 JP2011071953W WO2012043508A1 WO 2012043508 A1 WO2012043508 A1 WO 2012043508A1 JP 2011071953 W JP2011071953 W JP 2011071953W WO 2012043508 A1 WO2012043508 A1 WO 2012043508A1
Authority
WO
WIPO (PCT)
Prior art keywords
solar cell
semiconductor substrate
electrode
edge
mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2011/071953
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English (en)
Japanese (ja)
Inventor
井手　大輔
森上　光章
仁 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of WO2012043508A1 publication Critical patent/WO2012043508A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell and a manufacturing method thereof.
  • Patent Document 1 proposes a so-called back junction type solar cell having a p-type region and an n-type region on the back side.
  • this back junction solar cell it is not always necessary to provide an electrode for collecting carriers on the light receiving surface. For this reason, in the back junction solar cell, the light receiving efficiency can be improved. Therefore, more improved conversion efficiency can be realized.
  • the p-type region and the n-type region are formed on the back surface with high definition. For this reason, when manufacturing a back junction solar cell, it is necessary to form the p-type region and the n-type region after accurately detecting the position of the semiconductor substrate.
  • a direction for detecting the position of the semiconductor substrate for example, by detecting the position of the end surface of the semiconductor substrate, by detecting the position of the semiconductor substrate, or by detecting the position of the alignment mark formed on the semiconductor substrate
  • a method for detecting the position of the semiconductor substrate may be used.
  • the method of detecting the position of the semiconductor substrate by detecting the position of the alignment mark formed on the semiconductor substrate is particularly useful because it can detect the position of the semiconductor substrate with high accuracy. .
  • alignment marks 101a to 101d are formed at the center of each of four edge portions as alignment marks used when inspecting a manufactured solar cell 100. Are listed. However, when alignment marks 101a to 101d are provided at the center of each of the four edge portions, there is a problem that the photoelectric conversion efficiency of the solar cell is lowered.
  • the solar cell according to the present invention includes a semiconductor substrate, a first electrode, and a second electrode.
  • the semiconductor substrate includes first and second edge portions facing each other.
  • the first electrode is provided on one main surface of the semiconductor substrate.
  • the first electrode includes a first portion located at the first edge portion, and a plurality of first linear portions extending from the first portion toward the second edge portion side.
  • Have The second electrode is provided on one main surface of the semiconductor substrate.
  • the second electrode includes a second portion located at the second edge, and a plurality of second linear portions extending from the second portion toward the first edge.
  • Have The semiconductor substrate has a mark on one main surface.
  • the manufacturing method of the solar cell according to the present invention includes first and second end edges facing each other, and a plurality of one end faces provided on one of the first and second end edges.
  • a semiconductor substrate having an alignment mark, a first portion provided on one main surface of the semiconductor substrate and positioned at the first edge, and a second edge from the first portion
  • a first electrode having a plurality of first linear portions extending toward the surface, and a second portion provided on one main surface of the semiconductor substrate and positioned at the second edge portion
  • a second electrode having a plurality of second linear portions extending from the second portion toward the first edge portion side.
  • the first and second electrodes are formed based on the positions of the semiconductor substrates detected by detecting the positions of the plurality of alignment marks.
  • a solar cell having improved photoelectric conversion efficiency can be provided.
  • FIG. 1 is a schematic plan view of a solar cell according to a first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1 is a schematic plan view of a semiconductor substrate according to a first embodiment. It is a schematic plan view of the solar cell according to the second embodiment. It is a schematic plan view of a solar cell according to a third embodiment. It is schematic-drawing sectional drawing of the solar cell which concerns on 4th Embodiment. 2 is a schematic plan view of a solar cell described in Patent Document 1.
  • FIG. 1 is a schematic plan view of a solar cell according to a first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1 is a schematic plan view of a semiconductor substrate according to a first embodiment. It is a schematic plan view of the solar cell according to the second embodiment. It is a schematic plan view of a solar cell according to a third embodiment. It is schematic-drawing sectional drawing of the solar
  • the solar cell 1 of this embodiment can also be used independently, when the solar cell 1 single-piece
  • the solar cell 1 includes a solar cell substrate 10.
  • the solar cell substrate 10 includes a semiconductor substrate 15, an n-type amorphous semiconductor layer 14n disposed in the first region of the back surface 15a of the semiconductor substrate 15, and a p-type amorphous semiconductor layer disposed on the second region. 14p.
  • the semiconductor substrate 15 is made of single crystal silicon.
  • the semiconductor substrate 15 has a rectangular shape with chamfered corners.
  • the semiconductor substrate 15 includes a pair of end edge portions 15A and 15B facing in the y direction (one direction) and a pair of ends facing in the x direction (other direction) orthogonal to the y direction. And an edge.
  • the semiconductor substrate 15 may have a quadrangular shape that does not have chamfered portions at corners.
  • the semiconductor substrate 15 has a back surface 15a and a light receiving surface 15b.
  • the semiconductor substrate 15 generates carriers by receiving light at the light receiving surface 15b.
  • the carriers are holes and electrons that are generated when light is absorbed by the semiconductor substrate 15.
  • the semiconductor substrate 15 is composed of a substrate made of a crystalline semiconductor having n-type or p-type conductivity.
  • Specific examples of the crystalline semiconductor include crystalline silicon such as single crystal silicon and polycrystalline silicon.
  • the semiconductor substrate 15 is formed of a substrate made of crystalline silicon having n-type conductivity.
  • the n-type amorphous semiconductor layer 14n is formed on the first region of the back surface 15a of the semiconductor substrate 15, and the p-type amorphous semiconductor layer 14p is formed on the second region of the back surface 15a of the semiconductor substrate 15. Yes.
  • each of the n-type amorphous semiconductor layer 14n and the p-type amorphous semiconductor layer 14p is formed in a comb shape.
  • the back surface 10a of the solar cell substrate 10 is constituted by the surface of the n-type amorphous semiconductor layer 14n and the p-type amorphous semiconductor layer 14p and the exposed portion of the back surface 15a.
  • the light receiving surface 10 b of the solar cell substrate 10 is constituted by the light receiving surface 15 b of the semiconductor substrate 15.
  • the light-receiving surface 10b of the solar cell substrate 10 can also be constituted by a light-receiving surface of a passivation layer or an antireflection layer formed on substantially the entire surface of the light-receiving surface 15b of the semiconductor substrate 15.
  • a semiconductor layer or a protective layer may be formed on the light receiving surface 15 b of the semiconductor substrate 15.
  • a protective layer having a function as a film may be laminated in this order.
  • the light receiving surface 10b of the solar cell substrate 10 is constituted by the surface of the protective layer.
  • the n-type amorphous semiconductor layer 14n is formed of n-type amorphous silicon containing hydrogen.
  • the p-type amorphous semiconductor layer 14p is formed of p-type amorphous silicon containing hydrogen.
  • the thicknesses of the p-type and n-type amorphous semiconductor layers 14p and 14n are not particularly limited, but can be, for example, about 20 to 500 mm.
  • an i-type amorphous semiconductor layer may be interposed between the semiconductor substrate 15 and the n-type amorphous semiconductor layer 14n and between the semiconductor substrate 15 and the p-type amorphous semiconductor layer 14p.
  • the i-type amorphous semiconductor layer is preferably composed of an i-type amorphous silicon layer containing hydrogen.
  • the thickness of the i-type amorphous silicon layer is preferably a thickness that does not substantially contribute to power generation, for example, about several to 250 inches.
  • a p-side electrode 17p is provided on the p-type amorphous semiconductor layer 14p.
  • an n-side electrode 17n is provided on the n-type amorphous semiconductor layer 14n.
  • Each of the p-side electrode 17p and the n-side electrode 17n is arranged at a predetermined interval so as not to be electrically short-circuited.
  • each of the p-side electrode 17p and the n-side electrode 17n has a comb-like shape.
  • the p-side electrode 17p has a p-side bus bar portion 17p1 and a plurality of p-side finger portions 17p2.
  • the p-side bus bar portion 17p1 is located at the edge portion 15A on the y1 side of the semiconductor substrate 15.
  • the p-side bus bar portion 17p1 is formed in a linear shape extending along the x direction.
  • the plurality of p-side finger portions 17p2 extend along the y direction from the p-side bus bar portion 17p1 toward the y2 side.
  • the n-side electrode 17n has an n-side bus bar portion 17n1 and a plurality of n-side finger portions 17n2.
  • the n-side bus bar portion 17n1 is located at the edge portion 15B on the y2 side of the semiconductor substrate 15.
  • the n-side bus bar portion 17n1 is formed in a linear shape extending along the x direction.
  • the plurality of n-side finger portions 17n2 extend along the y direction from the n-side bus bar portion 17n1 toward the y1 side.
  • the plurality of n-side finger portions 17n2 and the plurality of p-side finger portions 17p2 are alternately arranged in the x direction.
  • the n-side electrode 17n is an electrode that collects electrons that are majority carriers.
  • the p-side electrode 17p is an electrode that collects holes that are minority carriers.
  • each of the p-side electrode 17p and the n-side electrode 17n is not particularly limited.
  • Each of the p-side electrode 17p and the n-side electrode 17n can be formed of, for example, a metal such as Ag, Cu, Au, Pt, Al, Sn, or Pd or an alloy containing one or more of these metals.
  • the formation method of each of the p-side electrode 17p and the n-side electrode 17n is not particularly limited.
  • Each of the p-side electrode 17p and the n-side electrode 17n may be formed, for example, by applying a resin-type conductive paste containing a conductive filler made of metal, an alloy, or the like, or formed by plating. May be.
  • Each of the p-side electrode 17p and the n-side electrode 17n may be formed by a vapor deposition method, a sputtering method, or the like.
  • a plurality of alignment marks are provided on the back surface 15 a of the semiconductor substrate 15.
  • two alignment marks 12a and 12b are provided on the back surface 15a.
  • the alignment marks 12a and 12b are provided on one end edge of the end edges 15A and 15B.
  • the alignment marks 12a and 12b are not provided on the other edge portion.
  • the alignment marks 12a and 12b are provided on the edge portion 15B where the n-side bus bar portion 17n1 of the n-side electrode 17n that collects majority carriers is disposed. More specifically, the alignment marks 12a and 12b are formed below the n-side bus bar portion 17n1 at the end edge portion 15B.
  • each of the alignment marks 12a and 12b includes a recess formed on the back surface 15a of the semiconductor substrate 15 located in a portion hidden by the n-side bus bar portion 17n1.
  • This recess has a depth larger than the thickness of the n-type amorphous semiconductor layer 14n. That is, the alignment marks 12a and 12b provided on the back surface 15a of the semiconductor substrate 15 are formed when the n-type and p-type amorphous semiconductor layers 14n and 14p are formed, and the n-side electrode 17n and the p-side electrode 17p are formed. In addition, it is formed to a depth that can be confirmed from the outside.
  • the position of the semiconductor substrate 15 can be detected using the alignment marks 12a and 12b.
  • the alignment marks 12a and 12b may be visible after the n-side electrode 17n and the p-side electrode 17p are formed, or may not be visible.
  • the marks 12a and 12b are formed even after the electrodes are formed. Visible. In this case, the marks 12a and 12b can also be used as product information marks.
  • the alignment mark is not limited to the one composed only of the concave portion.
  • the alignment mark may include another layer formed on the back surface of the semiconductor substrate.
  • the planar shape of the alignment marks 12a and 12b is not particularly limited.
  • the alignment marks 12a and 12b may have a shape in which a plurality of line segments intersect such as a cross shape, for example, or may have a dot shape.
  • the alignment marks 12a and 12b may have a circular shape, or may have other shapes such as a triangular shape and a rectangular shape.
  • alignment marks 12 a and 12 b are formed on the back surface 15 a of the semiconductor substrate 15.
  • the method for forming the alignment marks 12a and 12b is not particularly limited.
  • the alignment marks 12a and 12b can be formed by removal processing by various methods such as laser irradiation, etching, or mechanical processing.
  • the n-type amorphous semiconductor layer 14n is formed on the first region of the back surface 15a, and the p-type amorphous semiconductor layer 14p is formed on the second region.
  • the n-type amorphous semiconductor layer 14n and the p-type amorphous semiconductor layer 14p can be formed by, for example, a CVD (Chemical Vapor Deposition) method.
  • the alignment marks 12a and 12b are detected using detection means such as an imaging device, and n is determined based on the detection position.
  • a type amorphous semiconductor layer 14n and a p type amorphous semiconductor layer 14p are formed. Therefore, the n-type amorphous semiconductor layer 14n and the p-type amorphous semiconductor layer 14p can be formed with high positional accuracy. Therefore, the interval between the n-type amorphous semiconductor layer 14n and the p-type amorphous semiconductor layer 14p can be reduced. Therefore, the solar cell 1 with higher photoelectric conversion efficiency can be manufactured.
  • n-side electrode 17n and a p-side electrode 17p are formed.
  • the n-side electrode 17n and the p-side electrode 17p can be formed by, for example, a thin film forming method such as a vacuum deposition method, a sputtering method, or a plating method, or a method using a conductive paste.
  • the step of forming the n-side electrode 17n and the p-side electrode 17p as in the step of forming the n-type amorphous semiconductor layer 14n and the p-type amorphous semiconductor layer 14p, detection means such as an imaging device is used. Then, the alignment marks 12a and 12b are detected, and the n-side electrode 17n and the p-side electrode 17p are formed based on the detected positions. For this reason, the n-side electrode 17n and the p-side electrode 17p can be formed with high positional accuracy. Therefore, the solar cell 1 with higher photoelectric conversion efficiency can be manufactured.
  • both the plurality of alignment marks 12a and 12b are formed on one of the edge portions 15A and 15B.
  • membrane formed on alignment mark 12a, 12b is the same. For this reason, detection errors of the alignment marks 12a and 12b due to the difference in the film surface are unlikely to occur, and highly accurate position detection is possible. Therefore, the n-side electrode 17n and the p-side electrode 17p can be formed with high positional accuracy. Therefore, the photoelectric conversion efficiency of the solar cell 1 can be increased.
  • both the alignment marks 12a and 12b are formed on one of the end edges 15A and 15B, so that the alignment mark of the end edge 15A and the alignment mark of the end edge 15B are different. I am letting. Specifically, the number of alignment marks is made different. And the edge part 15A and the edge part 15B can be identified by making the number of alignment marks different. For this reason, the orientation of the semiconductor substrate 15 can be easily determined. Therefore, it is possible to reduce misidentification of the orientation of the semiconductor substrate 15 in the manufacturing process of the solar cell. Such an effect can be obtained not only by the number of alignment marks but also by changing the shape, color, and the like.
  • the alignment marks 12a and 12b are provided on the edge 15B where the n-side electrode 17n is provided. Since the n-side electrode 17n is an electrode that collects electrons that are majority carriers, the edge portion 15B has a small influence on the collection of minority carriers that greatly affects the photoelectric conversion characteristics. For this reason, by forming the alignment marks 12a and 12b on the electrode side that collects majority carriers, the photoelectric conversion efficiency of the solar cell 1 is unlikely to decrease even when a structural defect occurs in the edge 15B. Accordingly, it is possible to effectively suppress a decrease in photoelectric conversion efficiency due to the formation of the alignment marks 12a and 12b on the semiconductor substrate 15.
  • the n-side bus bar portion 17n1 is formed on the region where the alignment marks 12a and 12b are formed. For this reason, the area
  • FIG. 4 is a schematic plan view of the solar cell according to the second embodiment.
  • the alignment marks 12a and 12b are provided under the n-side bus bar portion 17n1 .
  • the present invention is not limited to this configuration.
  • the alignment marks 12a and 12b may be formed in a region where the n-side electrode 17n and the p-side electrode 17p are not formed.
  • notches 18a and 18b are formed in the n-side bus bar portion 17n1
  • alignment marks 12a and 12b are formed in the notches 18a and 18b.
  • the p-type amorphous semiconductor layer 14p nor the n-type amorphous semiconductor layer 14n is formed on the alignment marks 12a and 12b. For this reason, the depth of the alignment marks 12a and 12b can be made shallow. Therefore, it is possible to effectively suppress the occurrence of structural defects in the semiconductor substrate 15.
  • FIG. 5 is a schematic plan view of a solar cell according to the third embodiment.
  • the mark is not limited to the alignment mark.
  • one product information mark 12c may be formed, or in addition to the alignment marks 12a and 12b of the first embodiment, a product information mark 12c may be formed. .
  • the product information mark 12c is a mark that can identify some information about the solar cell 1 such as the date of manufacture, the production line, the lot number, the type of semiconductor substrate used, the lot number, and the like.
  • the product information mark 12c may be, for example, an enumeration of numbers or a figure such as a barcode or a QR code (registered trademark).
  • FIG. 6 is a schematic cross-sectional view of a solar cell according to the fourth embodiment.
  • the present invention is not limited to this configuration.
  • a p-type dopant diffusion region 10 ap in which a p-type dopant is diffused and an n-type dopant diffusion region 10 an in which an n-type dopant is diffused are exposed on the surface.
  • the n-side electrode 17n and the p-side electrode 17p may be formed immediately above the semiconductor substrate 15 using the semiconductor substrate 15 that is formed.
  • the alignment marks 12a and 12b are used when forming the n-side electrode 17n and the p-side electrode 17p, and are also positioned when forming the p-type dopant diffusion region 10ap and the n-type dopant diffusion region 10an. Used as an indicator.

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  • Photovoltaic Devices (AREA)

Abstract

La présente invention concerne une cellule solaire présentant une efficacité de conversion photoélectrique élevée. Une cellule solaire (1) comporte un substrat semi-conducteur (15), une première électrode (17n), et une seconde électrode (17p). Le substrat semi-conducteur (15) a une première section de bord (15B) et une seconde section de bord (15A) qui se font face. La première électrode (17n) a une première section (17n1) qui est située dans la première section de bord (15B) et une pluralité de premières sections linéaires (17n2). La seconde électrode (17p) a une seconde section (17p1) qui est située dans la seconde section de bord (15A) et une pluralité de secondes sections linéaires (17p2). Le substrat semi-conducteur (15) a des marques (12a et 12b) sur une surface principale (15a). Lesdites marques (12a et 12b) sont formées soit dans la première section de bord (15B) soit dans la seconde section de bord (15A).
PCT/JP2011/071953 2010-09-27 2011-09-27 Cellule solaire et son procédé de fabrication Ceased WO2012043508A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-215559 2010-09-27
JP2010215559A JP2012069881A (ja) 2010-09-27 2010-09-27 太陽電池及びその製造方法

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WO2012043508A1 true WO2012043508A1 (fr) 2012-04-05

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111948558A (zh) * 2019-05-16 2020-11-17 丰田自动车株式会社 电池的检查方法、电池的检查装置以及电池

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7626615B2 (ja) * 2020-12-25 2025-02-04 株式会社カネカ 太陽電池ユニットおよび太陽電池ユニットの製造方法
CN117117011A (zh) 2023-09-19 2023-11-24 晶科能源(海宁)有限公司 一种电池片及光伏组件

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WO2006117980A1 (fr) * 2005-04-26 2006-11-09 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d’une cellule solaire, cellule solaire et procede de fabrication d’un dispositif semi-conducteur
WO2008090718A1 (fr) * 2007-01-25 2008-07-31 Sharp Kabushiki Kaisha Cellule de batterie solaire, réseau de batteries solaires, module de batterie solaire et procédé de fabrication d'un réseau de batteries solaires
WO2010068331A1 (fr) * 2008-12-10 2010-06-17 Applied Materials, Inc. Système de visualisation amélioré pour calage de motif de sérigraphie
JP2010205913A (ja) * 2009-03-03 2010-09-16 Sharp Corp 太陽電池モジュールの製造方法、および太陽電池モジュールの製造装置
WO2011090169A1 (fr) * 2010-01-22 2011-07-28 シャープ株式会社 Cellule solaire à contact arrière, feuille de câblage, cellule solaire comportant une feuille de câblage, module de cellules solaires et procédé de fabrication d'une cellule solaire comportant une feuille de câblage

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Publication number Priority date Publication date Assignee Title
WO2006117980A1 (fr) * 2005-04-26 2006-11-09 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d’une cellule solaire, cellule solaire et procede de fabrication d’un dispositif semi-conducteur
WO2008090718A1 (fr) * 2007-01-25 2008-07-31 Sharp Kabushiki Kaisha Cellule de batterie solaire, réseau de batteries solaires, module de batterie solaire et procédé de fabrication d'un réseau de batteries solaires
WO2010068331A1 (fr) * 2008-12-10 2010-06-17 Applied Materials, Inc. Système de visualisation amélioré pour calage de motif de sérigraphie
JP2010205913A (ja) * 2009-03-03 2010-09-16 Sharp Corp 太陽電池モジュールの製造方法、および太陽電池モジュールの製造装置
WO2011090169A1 (fr) * 2010-01-22 2011-07-28 シャープ株式会社 Cellule solaire à contact arrière, feuille de câblage, cellule solaire comportant une feuille de câblage, module de cellules solaires et procédé de fabrication d'une cellule solaire comportant une feuille de câblage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111948558A (zh) * 2019-05-16 2020-11-17 丰田自动车株式会社 电池的检查方法、电池的检查装置以及电池
CN111948558B (zh) * 2019-05-16 2023-12-08 丰田自动车株式会社 电池的检查方法、电池的检查装置以及电池

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