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WO2011129039A1 - Dispositif de capture d'image à semiconducteur et appareil photographique - Google Patents

Dispositif de capture d'image à semiconducteur et appareil photographique Download PDF

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Publication number
WO2011129039A1
WO2011129039A1 PCT/JP2011/000521 JP2011000521W WO2011129039A1 WO 2011129039 A1 WO2011129039 A1 WO 2011129039A1 JP 2011000521 W JP2011000521 W JP 2011000521W WO 2011129039 A1 WO2011129039 A1 WO 2011129039A1
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Prior art keywords
solid
imaging device
state imaging
binary
voltage
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Ceased
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PCT/JP2011/000521
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English (en)
Japanese (ja)
Inventor
三宅智治
徳本順士
羽原紀史
本多智宏
松本博志
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
    • H04N25/445—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by skipping some contiguous pixels within the read portion of the array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals

Definitions

  • the present invention relates to a solid-state imaging device used for a digital still camera or the like, and more particularly to reduction of the number of terminals between a solid-state imaging device and a vertical drive circuit (VDr).
  • VDr vertical drive circuit
  • HD movies High-Definition movies
  • Patent Document 1 a time division multiplexing circuit is provided in a timing signal generation circuit (TG), and a read pulse and a vertical transfer pulse are time division multiplexed.
  • TG timing signal generation circuit
  • a technique for reducing the number of terminals between the timing signal generation circuit and the vertical drive circuit has been proposed.
  • an object of the present invention is to provide a solid-state imaging device capable of reducing the number of terminals between a solid-state imaging device and a vertical drive circuit.
  • the solid-state imaging device in the solid-state imaging device according to the first aspect of the present invention, two-dimensionally arranged photodiodes and a vertical transfer unit that transfers signal charges photoelectrically converted by the photodiodes in the vertical direction. And a horizontal transfer unit for transferring the signal charge from the vertical transfer unit in the horizontal direction, and by applying a first voltage, the signal charge is read from the photodiode to the vertical transfer unit and the read
  • the solid-state imaging device that transfers the signal charge toward the horizontal transfer unit by applying a second voltage lower than the first voltage and a third voltage lower than the second voltage
  • the solid-state imaging device A binary pulse generating circuit for generating a binary pulse composed of the second and third voltages from a ternary pulse composed of the first, second and third voltages, Ternary pulse and the generated binary pulse generating circuit and a binary pulse and switches the 3 / bi switching control signal.
  • the binary pulse generation circuit includes a transistor.
  • the binary pulse generation circuit includes a transistor and a diode.
  • the ternary / binary switching control signal for controlling the binary pulse generation circuit is obtained from a binary pulse of a high level and a low level. It is characterized by becoming.
  • n 1 interlace reading is performed in which the signal charge for one screen is divided into n times (n is an integer of 2 or more) and read to the vertical transfer unit.
  • the number of drive pulses for controlling reading and vertical transfer is n / 2.
  • the solid-state imaging device in the solid-state imaging device according to the first aspect, in the thinning readout in which the signal charges accumulated in the photodiode are not read out to the vertical transfer unit for a specific row, the vertical direction connected to the same phase electrode
  • the binary pulse generation circuit is inserted into a row to be thinned out so that the first voltage is not simultaneously applied to the continuous pixels of the pixel, and the inserted binary pulse generation circuit is switched to the ternary / binary switching. Control is performed by a control signal.
  • the binary pulse generation circuit is inserted in a row not to be read so that the first voltage is not applied to a peripheral row not to be read, and the inserted binary pulse generation circuit is switched to the ternary / binary switching. Control is performed by a control signal.
  • the ternary / binary switching control signal for controlling the binary pulse generation circuit is a drive pulse for controlling horizontal transfer.
  • a camera according to a ninth aspect of the invention is characterized by including the solid-state imaging device according to any one of the first to eighth aspects.
  • a conventional ternary pulse is applied to the solid-state imaging device. Therefore, it is possible to reduce the number of terminals between the solid-state imaging device and the vertical drive circuit.
  • the number of terminals between the solid-state imaging device and the vertical drive circuit can be reduced, and smear occurring in the HD moving image mode can be achieved.
  • the step can be eliminated without increasing the number of terminals.
  • FIG. 1 is a schematic configuration diagram of a camera according to the first embodiment of the present invention.
  • FIG. 2 is a configuration diagram of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a configuration example of a binary pulse generation circuit provided in the solid-state imaging device.
  • FIG. 4 is a diagram showing another configuration example of the binary pulse generation circuit provided in the solid-state imaging device.
  • FIG. 5 is an operation timing chart of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 6 is a configuration diagram of a solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 7 is an operation timing chart of the solid-state imaging device.
  • FIG. 1 is a schematic configuration diagram of a camera according to the first embodiment of the present invention.
  • FIG. 2 is a configuration diagram of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a configuration example of a binary pulse
  • FIG. 8 is a configuration diagram of a solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 9 is an operation timing chart of the solid-state imaging device.
  • FIG. 10 is a configuration diagram of a conventional solid-state imaging device when performing a 12: 1 interlace operation.
  • FIG. 11 is a configuration diagram of a conventional solid-state imaging device in the case where thinned rows and non-thinned rows are controlled by separate drive pulses.
  • FIG. 12 is a configuration diagram of a conventional solid-state imaging device when only the effective pixel at the center of the screen is read.
  • FIG. 13 is a configuration diagram of a solid-state imaging device according to the fourth embodiment of the present invention.
  • FIG. 14 is an operation timing chart of the solid-state imaging device.
  • FIG. 1 shows a configuration of a camera using a general solid-state image sensor.
  • 101 is a solid-state image sensor (CCD)
  • 102 is a timing signal generation circuit (TG) for controlling the drive timing for the solid-state image sensor
  • 103 is a signal input from the timing signal generation circuit 102.
  • 101 is a vertical drive circuit (VDr) that performs voltage conversion as a drive signal of 101
  • 104 is a preprocessing circuit (AFE) that receives a signal from the solid-state image sensor 101 and performs CDS or A / D conversion
  • 105 is the preprocessing.
  • a digital signal processing circuit (DSP) that receives a signal from the circuit 104 and performs pixel interpolation, luminance / color signal processing, and the like.
  • FIG. 2 shows a configuration of the solid-state imaging device according to the first embodiment of the present invention, and includes a solid-state imaging device (CCD) 101 and a vertical drive circuit (VDr) 103 provided in the camera of FIG.
  • CCD solid-state imaging device
  • VDr vertical drive circuit
  • the vertical drive circuit 103 includes a first voltage VH for reading a signal charge from a photodiode (described later) in the solid-state imaging device 101 to a vertical transfer unit (described later) in the solid-state imaging device 101, and the vertical driving circuit 103.
  • the vertical drive pulse 201 ( ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, ⁇ V6) generated in the above is generated.
  • the solid-state imaging device 101 includes a photodiode 204 that forms a cell of one pixel, a vertical transfer unit 205 for vertically transferring a signal charge read from the photodiode 204, and the vertical transfer unit.
  • the binary pulse generation circuit 203 uses the ternary / binary switching control signal 202 (HC1, HC2) supplied from the outside of the solid-state imaging device 101 to convert the vertical drive pulse 201 into three values (VH, VM, VL). Switching between supply and binary (VM, VL) switching.
  • the ternary / binary switching control signal 202 is composed of binary pulses of a first voltage VH and a second voltage VM.
  • the drive electrodes 207 of the vertical transfer units 205 in each column have a vertical 6-phase configuration in which 6 types of drive electrodes are repeated as a set in the vertical direction.
  • the ternary / binary switching control signal 202 connected to the binary pulse generation circuit 203 is changed according to the value HC1 and the value HC2.
  • FIG. 3 shows an example of the internal configuration of the binary pulse generation circuit 203 shown in FIG.
  • a binary pulse generation circuit 203 is composed of a transistor 301.
  • a ternary / binary switching control signal 202 (HCx) is supplied to the gate of the transistor 301, and a vertical drive pulse 201 ( ⁇ Vx) is supplied to the drain.
  • HCx ternary / binary switching control signal
  • ⁇ Vx vertical drive pulse 201
  • FIG. 4 shows another configuration example of the binary pulse generation circuit 203 shown in FIG.
  • a binary pulse generation circuit 203 is composed of a diode 401 and a transistor 301, the vertical drive pulse 201 ( ⁇ Vx) is provided at the anode of the diode 401, the drain of the transistor 301 is provided at the cathode, and the gate of the transistor 301 is provided.
  • the ternary / binary switching control signal 202 (HCx) is connected to the transistor 301, and the ground (GND) of 0V is connected to the source of the transistor 301.
  • the ternary / binary switching control signal 202 when the ternary / binary switching control signal 202 is at the low level, the input vertical drive pulse 201 is output as it is. Next, when the ternary / binary switching control signal 202 is at a high level, a current flows from the diode 401 to the GND through the transistor 301, and the first voltage VH of the input vertical drive pulse 201 is suppressed.
  • FIG. 5 shows an operation timing chart of the solid-state imaging device of the present embodiment. This figure is a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.
  • ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, and ⁇ V6 are vertical drive pulses generated by the vertical drive circuit 103, and ⁇ V1 ′, ⁇ V2 ′, ⁇ V3 ′, ⁇ V4 ′, ⁇ V5 ′, and ⁇ V6 ′.
  • ⁇ V1 ′′, ⁇ V2 ′′, ⁇ V3 ′′, ⁇ V4 ′′, ⁇ V5 ′′, ⁇ V6 ′′ are vertical drive pulses generated by the binary pulse generation circuit 203
  • HC1 and HC2 are ternary / binary switching control signals 202.
  • the vertical drive pulses ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, ⁇ V1 ′, ⁇ V2 ′, ⁇ V3 ′, ⁇ V4 ′, ⁇ V5 ′, ⁇ V1 ′′, ⁇ V2 ′′, ⁇ V3 ′′, ⁇ V4 ′′, ⁇ V5 ′′ are
  • the third voltage VL is incapable of accumulating signals in the vertical transfer unit 205 (barrier state)
  • the vertical drive pulses ⁇ V6, ⁇ V6 ′, ⁇ V6 ′′ are the second voltage VM, and signals to the vertical transfer unit 205 It can be stored (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal 202 (HC1) is at the low level.
  • VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 is the first because the ternary / binary switching control signal 202 (HC2) is at the high level. Propagation of the voltage VH is suppressed, and the signal charge is not read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM. Charges are transferred in the direction of a horizontal transfer unit (not shown). The signal charge output from the horizontal transfer unit is converted into a signal voltage or a signal current and output by a signal charge detection unit (not shown).
  • 12: 1 interlace operation can be performed in a vertical 6-phase configuration.
  • a vertical 12-phase configuration is required in order to perform the 12: 1 interlace operation.
  • an n: 1 interlace operation can be realized with the number of vertical phases of n / 2, and the terminals related to the vertical drive between the solid-state imaging device 101 and the vertical drive circuit 103 are set to n / The effect that it can be reduced to two is obtained.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).
  • FIG. 6 shows a configuration of a solid-state imaging device according to the second embodiment of the present invention.
  • the basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 in the figure is the same as that of the first embodiment except for the number of vertical phases and the connection configuration of the binary pulse generation circuit 203.
  • the drive electrodes 207 of the vertical transfer unit 205 in each column have a vertical 6-phase configuration in which six types of drive electrodes are arranged as a set in the vertical direction.
  • the binary pulse generation circuit 203 is connected so that the first voltage VH is not simultaneously applied to the continuous pixels in the vertical direction connected to the same phase electrode in the pulses ⁇ V1 and ⁇ V2.
  • FIG. 7 shows an operation timing chart according to the second embodiment. This figure shows a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.
  • ⁇ V1 and ⁇ V2 are vertical drive pulses generated by the vertical drive circuit 103
  • ⁇ V1 ′ and ⁇ V2 ′ are vertical drive pulses generated by the binary pulse generation circuit 203
  • HC1 is a ternary / binary switching control signal. 202.
  • the vertical drive pulses ⁇ V2, ⁇ V3, ⁇ V5, ⁇ V6, ⁇ V2 ′, and ⁇ V2 ′′ are the third voltage VL, and the vertical transfer unit 205 cannot store signals (barrier state).
  • the vertical drive pulses ⁇ V 1, ⁇ V 4, ⁇ V 1 ′, ⁇ V 1 ′′ are the second voltage VM, and a signal can be accumulated in the vertical transfer unit 205 (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the low level. VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the high level. Is suppressed, and the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V 2 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V2 ′ to which the same drive pulse as the vertical drive pulse ⁇ V2 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the low level. VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V2 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the high level. And the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the high level. VH is suppressed and the signal charge is not read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the low level. Is applied as it is, and the signal charge is read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V2 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the high level. VH is suppressed and the signal charge is not read out.
  • the vertical drive pulse ⁇ V2 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V2 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the low level. Is applied as it is, and the signal charge is read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM, respectively, and the signal charges in the vertical transfer unit 205 are transferred horizontally. Transfer in the direction of the part.
  • the present embodiment it is possible to reduce the number of terminals related to vertical driving between the vertical driving circuit 103 and the solid-state imaging device 101 in the thinning-out operation.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).
  • FIG. 8 shows a configuration of a solid-state imaging device according to the third embodiment of the present invention.
  • the basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 shown in the figure is the same as that of the first embodiment except for the number of vertical phases and the connection configuration of the binary pulse generation circuit 203.
  • the drive electrodes 207 of the vertical transfer units 205 in each column have a vertical three-phase configuration in which three types of drive electrodes are arranged as a set in the vertical direction.
  • the binary pulse generation circuit 203 is connected so that the first voltage VH is not applied to the other peripheral pixels.
  • FIG. 9 is a diagram illustrating an operation timing chart of the solid-state imaging device according to the third embodiment. This figure shows a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.
  • vertical drive pulses ⁇ V 1, ⁇ V 2, and ⁇ V 3 are vertical drive pulses generated by the vertical drive circuit 103, and ⁇ V 1 ′, ⁇ V 2 ′, and ⁇ V 3 ′ are vertical drive pulses generated by the binary pulse generation circuit 203.
  • HC1 is a ternary / binary switching control signal 202.
  • the vertical drive pulses ⁇ V2 and ⁇ V2 ′ are the third voltage VL, and the signal cannot be accumulated in the vertical transfer unit 205 (barrier state).
  • the vertical drive pulses ⁇ V 1, ⁇ V 3, ⁇ V 1 ′, and ⁇ V 3 ′ are the second voltage VM, and the signal can be accumulated in the vertical transfer unit 205 (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM.
  • the voltage VH of 1 is suppressed and the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V3, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V3 ′ to which the same drive pulse as the vertical drive pulse ⁇ V3 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM.
  • the voltage VH of 1 is suppressed and the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V2, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V2 ′ to which the same drive pulse as the vertical drive pulse ⁇ V2 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM.
  • the voltage VH of 1 is suppressed and the signal charge is not read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM, respectively, and the signal charges in the vertical transfer unit 205 are transferred horizontally. Transfer in the direction of the part.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical three-phase configuration. However, the vertical transfer unit 205 does not have to be a vertical three-phase, and may be any number that is equal to or greater than the number of phases that can be vertically transferred (three or more phases).
  • FIG. 13 shows a configuration of a solid-state imaging device according to the fourth embodiment of the present invention.
  • the basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 in the figure is the same as that of the first embodiment except for the ternary / binary pulse switching control signal 202.
  • the horizontal drive pulse 209 of the horizontal transfer unit 210 that controls horizontal transfer is used as a ternary / binary pulse switching control signal.
  • FIG. 14 shows an operation timing chart of the solid-state imaging device of the present embodiment.
  • the figure is the same as the first embodiment except that the ternary / binary pulse switching control signal 202 is a horizontal drive pulse 209 composed of a value ⁇ H1 and a value ⁇ H2.
  • the vertical drive pulses ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, ⁇ V1 ′, ⁇ V2 ′, ⁇ V3 ′, ⁇ V4 ′, ⁇ V5 ′, ⁇ V1 ′′, ⁇ V2 ′′, ⁇ V3 ′′, ⁇ V4 ′′, ⁇ V5 ′′ are
  • the third voltage VL is incapable of signal accumulation (barrier state) in the vertical transfer unit 205.
  • the vertical drive pulses ⁇ V6, ⁇ V6 ′, and ⁇ V6 ′′ are the second voltage VM, and the vertical transfer unit 205 In this state, the signal can be accumulated (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal 202 (the horizontal drive pulse 209 of the value ⁇ H1) low. Since it is level, the first voltage VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has a ternary / binary switching control signal 202 (horizontal drive pulse 209 of value ⁇ H2) at a high level. Therefore, the propagation of the first voltage VH is suppressed, and the signal charge is not read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL, and from the third voltage VL to the second voltage VM.
  • the charge is transferred in the direction of the horizontal transfer unit 210.
  • the signal charge output from the horizontal transfer unit 210 is converted into a signal voltage or a signal current by the signal charge detection unit 211 and output.
  • 12: 1 interlace operation can be performed in a vertical 6-phase configuration.
  • a vertical 12-phase configuration is required in order to perform the 12: 1 interlace operation.
  • an n: 1 interlace operation can be realized with the number of vertical phases of n / 2, and the terminals related to the vertical drive between the solid-state imaging device 101 and the vertical drive circuit 103 are set to n / The effect that the number can be reduced to two is obtained.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).
  • the present invention is particularly useful in a device using a solid-state imaging device having a high pixel count.
  • a solid-state imaging device having a high pixel count.
  • a digital still camera but also a digital video camera, a camera mounted on a mobile phone, an in-vehicle camera, a surveillance It is useful when applied to cameras.
  • Solid-state image sensor (CCD) 102 Timing signal generation circuit (TG) 103 Vertical drive circuit (VDr) 104 Pre-processing circuit (AFE) 105 Digital signal processing circuit (DSP) 201 vertical drive pulse 202 ternary / binary pulse switching control signal 203 binary pulse generation circuit 204 photodiode 205 vertical transfer unit 206 metal wiring 207 vertical drive electrode 208 bus line 209 horizontal drive pulse 210 horizontal transfer unit 211 signal charge detection unit 301 Transistor 302 Binary Pulse Generation Circuit Output Signal (Vertical Drive Pulse) 401 diode

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Abstract

L'invention concerne un dispositif de capture d'image à semiconducteur. Selon l'invention, il existe des circuits générateurs d'impulsions binaires (203) qui génèrent des impulsions binaires à partir d'impulsions ternaires et des signaux de commande verticale provenant d'un circuit de commande verticale (103) sont commutés d'impulsions ternaires en impulsions binaires par des signaux de commande d'impulsions ternaires/binaires (202). Le nombre de bornes entre un élément de capture d'image à semiconducteur (101) et le circuit de commande verticale (103) est ainsi réduit, ce qui permet de réduire à son tour le nombre de bornes entre l'élément de capture d'image et le circuit de commande verticale.
PCT/JP2011/000521 2010-04-15 2011-01-31 Dispositif de capture d'image à semiconducteur et appareil photographique Ceased WO2011129039A1 (fr)

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JP2010094325 2010-04-15
JP2010-094325 2010-04-15

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064753A (ja) * 2000-08-16 2002-02-28 Fuji Film Microdevices Co Ltd Ｃｃｄ電荷転送用駆動回路
JP2005039561A (ja) * 2003-07-15 2005-02-10 Sharp Corp 固体撮像装置およびその駆動方法
JP2009130907A (ja) * 2007-11-28 2009-06-11 Panasonic Corp 固体撮像装置およびその駆動方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064753A (ja) * 2000-08-16 2002-02-28 Fuji Film Microdevices Co Ltd Ｃｃｄ電荷転送用駆動回路
JP2005039561A (ja) * 2003-07-15 2005-02-10 Sharp Corp 固体撮像装置およびその駆動方法
JP2009130907A (ja) * 2007-11-28 2009-06-11 Panasonic Corp 固体撮像装置およびその駆動方法

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