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WO2011129039A1 - Solid-state image capture device and camera - Google Patents

Solid-state image capture device and camera Download PDF

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Publication number
WO2011129039A1
WO2011129039A1 PCT/JP2011/000521 JP2011000521W WO2011129039A1 WO 2011129039 A1 WO2011129039 A1 WO 2011129039A1 JP 2011000521 W JP2011000521 W JP 2011000521W WO 2011129039 A1 WO2011129039 A1 WO 2011129039A1
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Prior art keywords
solid
imaging device
state imaging
binary
voltage
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Ceased
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PCT/JP2011/000521
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French (fr)
Japanese (ja)
Inventor
三宅智治
徳本順士
羽原紀史
本多智宏
松本博志
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
    • H04N25/445—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by skipping some contiguous pixels within the read portion of the array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals

Definitions

  • the present invention relates to a solid-state imaging device used for a digital still camera or the like, and more particularly to reduction of the number of terminals between a solid-state imaging device and a vertical drive circuit (VDr).
  • VDr vertical drive circuit
  • HD movies High-Definition movies
  • Patent Document 1 a time division multiplexing circuit is provided in a timing signal generation circuit (TG), and a read pulse and a vertical transfer pulse are time division multiplexed.
  • TG timing signal generation circuit
  • a technique for reducing the number of terminals between the timing signal generation circuit and the vertical drive circuit has been proposed.
  • an object of the present invention is to provide a solid-state imaging device capable of reducing the number of terminals between a solid-state imaging device and a vertical drive circuit.
  • the solid-state imaging device in the solid-state imaging device according to the first aspect of the present invention, two-dimensionally arranged photodiodes and a vertical transfer unit that transfers signal charges photoelectrically converted by the photodiodes in the vertical direction. And a horizontal transfer unit for transferring the signal charge from the vertical transfer unit in the horizontal direction, and by applying a first voltage, the signal charge is read from the photodiode to the vertical transfer unit and the read
  • the solid-state imaging device that transfers the signal charge toward the horizontal transfer unit by applying a second voltage lower than the first voltage and a third voltage lower than the second voltage
  • the solid-state imaging device A binary pulse generating circuit for generating a binary pulse composed of the second and third voltages from a ternary pulse composed of the first, second and third voltages, Ternary pulse and the generated binary pulse generating circuit and a binary pulse and switches the 3 / bi switching control signal.
  • the binary pulse generation circuit includes a transistor.
  • the binary pulse generation circuit includes a transistor and a diode.
  • the ternary / binary switching control signal for controlling the binary pulse generation circuit is obtained from a binary pulse of a high level and a low level. It is characterized by becoming.
  • n 1 interlace reading is performed in which the signal charge for one screen is divided into n times (n is an integer of 2 or more) and read to the vertical transfer unit.
  • the number of drive pulses for controlling reading and vertical transfer is n / 2.
  • the solid-state imaging device in the solid-state imaging device according to the first aspect, in the thinning readout in which the signal charges accumulated in the photodiode are not read out to the vertical transfer unit for a specific row, the vertical direction connected to the same phase electrode
  • the binary pulse generation circuit is inserted into a row to be thinned out so that the first voltage is not simultaneously applied to the continuous pixels of the pixel, and the inserted binary pulse generation circuit is switched to the ternary / binary switching. Control is performed by a control signal.
  • the binary pulse generation circuit is inserted in a row not to be read so that the first voltage is not applied to a peripheral row not to be read, and the inserted binary pulse generation circuit is switched to the ternary / binary switching. Control is performed by a control signal.
  • the ternary / binary switching control signal for controlling the binary pulse generation circuit is a drive pulse for controlling horizontal transfer.
  • a camera according to a ninth aspect of the invention is characterized by including the solid-state imaging device according to any one of the first to eighth aspects.
  • a conventional ternary pulse is applied to the solid-state imaging device. Therefore, it is possible to reduce the number of terminals between the solid-state imaging device and the vertical drive circuit.
  • the number of terminals between the solid-state imaging device and the vertical drive circuit can be reduced, and smear occurring in the HD moving image mode can be achieved.
  • the step can be eliminated without increasing the number of terminals.
  • FIG. 1 is a schematic configuration diagram of a camera according to the first embodiment of the present invention.
  • FIG. 2 is a configuration diagram of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a configuration example of a binary pulse generation circuit provided in the solid-state imaging device.
  • FIG. 4 is a diagram showing another configuration example of the binary pulse generation circuit provided in the solid-state imaging device.
  • FIG. 5 is an operation timing chart of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 6 is a configuration diagram of a solid-state imaging device according to the second embodiment of the present invention.
  • FIG. 7 is an operation timing chart of the solid-state imaging device.
  • FIG. 1 is a schematic configuration diagram of a camera according to the first embodiment of the present invention.
  • FIG. 2 is a configuration diagram of the solid-state imaging device according to the first embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a configuration example of a binary pulse
  • FIG. 8 is a configuration diagram of a solid-state imaging device according to the third embodiment of the present invention.
  • FIG. 9 is an operation timing chart of the solid-state imaging device.
  • FIG. 10 is a configuration diagram of a conventional solid-state imaging device when performing a 12: 1 interlace operation.
  • FIG. 11 is a configuration diagram of a conventional solid-state imaging device in the case where thinned rows and non-thinned rows are controlled by separate drive pulses.
  • FIG. 12 is a configuration diagram of a conventional solid-state imaging device when only the effective pixel at the center of the screen is read.
  • FIG. 13 is a configuration diagram of a solid-state imaging device according to the fourth embodiment of the present invention.
  • FIG. 14 is an operation timing chart of the solid-state imaging device.
  • FIG. 1 shows a configuration of a camera using a general solid-state image sensor.
  • 101 is a solid-state image sensor (CCD)
  • 102 is a timing signal generation circuit (TG) for controlling the drive timing for the solid-state image sensor
  • 103 is a signal input from the timing signal generation circuit 102.
  • 101 is a vertical drive circuit (VDr) that performs voltage conversion as a drive signal of 101
  • 104 is a preprocessing circuit (AFE) that receives a signal from the solid-state image sensor 101 and performs CDS or A / D conversion
  • 105 is the preprocessing.
  • a digital signal processing circuit (DSP) that receives a signal from the circuit 104 and performs pixel interpolation, luminance / color signal processing, and the like.
  • FIG. 2 shows a configuration of the solid-state imaging device according to the first embodiment of the present invention, and includes a solid-state imaging device (CCD) 101 and a vertical drive circuit (VDr) 103 provided in the camera of FIG.
  • CCD solid-state imaging device
  • VDr vertical drive circuit
  • the vertical drive circuit 103 includes a first voltage VH for reading a signal charge from a photodiode (described later) in the solid-state imaging device 101 to a vertical transfer unit (described later) in the solid-state imaging device 101, and the vertical driving circuit 103.
  • the vertical drive pulse 201 ( ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, ⁇ V6) generated in the above is generated.
  • the solid-state imaging device 101 includes a photodiode 204 that forms a cell of one pixel, a vertical transfer unit 205 for vertically transferring a signal charge read from the photodiode 204, and the vertical transfer unit.
  • the binary pulse generation circuit 203 uses the ternary / binary switching control signal 202 (HC1, HC2) supplied from the outside of the solid-state imaging device 101 to convert the vertical drive pulse 201 into three values (VH, VM, VL). Switching between supply and binary (VM, VL) switching.
  • the ternary / binary switching control signal 202 is composed of binary pulses of a first voltage VH and a second voltage VM.
  • the drive electrodes 207 of the vertical transfer units 205 in each column have a vertical 6-phase configuration in which 6 types of drive electrodes are repeated as a set in the vertical direction.
  • the ternary / binary switching control signal 202 connected to the binary pulse generation circuit 203 is changed according to the value HC1 and the value HC2.
  • FIG. 3 shows an example of the internal configuration of the binary pulse generation circuit 203 shown in FIG.
  • a binary pulse generation circuit 203 is composed of a transistor 301.
  • a ternary / binary switching control signal 202 (HCx) is supplied to the gate of the transistor 301, and a vertical drive pulse 201 ( ⁇ Vx) is supplied to the drain.
  • HCx ternary / binary switching control signal
  • ⁇ Vx vertical drive pulse 201
  • FIG. 4 shows another configuration example of the binary pulse generation circuit 203 shown in FIG.
  • a binary pulse generation circuit 203 is composed of a diode 401 and a transistor 301, the vertical drive pulse 201 ( ⁇ Vx) is provided at the anode of the diode 401, the drain of the transistor 301 is provided at the cathode, and the gate of the transistor 301 is provided.
  • the ternary / binary switching control signal 202 (HCx) is connected to the transistor 301, and the ground (GND) of 0V is connected to the source of the transistor 301.
  • the ternary / binary switching control signal 202 when the ternary / binary switching control signal 202 is at the low level, the input vertical drive pulse 201 is output as it is. Next, when the ternary / binary switching control signal 202 is at a high level, a current flows from the diode 401 to the GND through the transistor 301, and the first voltage VH of the input vertical drive pulse 201 is suppressed.
  • FIG. 5 shows an operation timing chart of the solid-state imaging device of the present embodiment. This figure is a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.
  • ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, and ⁇ V6 are vertical drive pulses generated by the vertical drive circuit 103, and ⁇ V1 ′, ⁇ V2 ′, ⁇ V3 ′, ⁇ V4 ′, ⁇ V5 ′, and ⁇ V6 ′.
  • ⁇ V1 ′′, ⁇ V2 ′′, ⁇ V3 ′′, ⁇ V4 ′′, ⁇ V5 ′′, ⁇ V6 ′′ are vertical drive pulses generated by the binary pulse generation circuit 203
  • HC1 and HC2 are ternary / binary switching control signals 202.
  • the vertical drive pulses ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, ⁇ V1 ′, ⁇ V2 ′, ⁇ V3 ′, ⁇ V4 ′, ⁇ V5 ′, ⁇ V1 ′′, ⁇ V2 ′′, ⁇ V3 ′′, ⁇ V4 ′′, ⁇ V5 ′′ are
  • the third voltage VL is incapable of accumulating signals in the vertical transfer unit 205 (barrier state)
  • the vertical drive pulses ⁇ V6, ⁇ V6 ′, ⁇ V6 ′′ are the second voltage VM, and signals to the vertical transfer unit 205 It can be stored (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal 202 (HC1) is at the low level.
  • VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 is the first because the ternary / binary switching control signal 202 (HC2) is at the high level. Propagation of the voltage VH is suppressed, and the signal charge is not read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM. Charges are transferred in the direction of a horizontal transfer unit (not shown). The signal charge output from the horizontal transfer unit is converted into a signal voltage or a signal current and output by a signal charge detection unit (not shown).
  • 12: 1 interlace operation can be performed in a vertical 6-phase configuration.
  • a vertical 12-phase configuration is required in order to perform the 12: 1 interlace operation.
  • an n: 1 interlace operation can be realized with the number of vertical phases of n / 2, and the terminals related to the vertical drive between the solid-state imaging device 101 and the vertical drive circuit 103 are set to n / The effect that it can be reduced to two is obtained.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).
  • FIG. 6 shows a configuration of a solid-state imaging device according to the second embodiment of the present invention.
  • the basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 in the figure is the same as that of the first embodiment except for the number of vertical phases and the connection configuration of the binary pulse generation circuit 203.
  • the drive electrodes 207 of the vertical transfer unit 205 in each column have a vertical 6-phase configuration in which six types of drive electrodes are arranged as a set in the vertical direction.
  • the binary pulse generation circuit 203 is connected so that the first voltage VH is not simultaneously applied to the continuous pixels in the vertical direction connected to the same phase electrode in the pulses ⁇ V1 and ⁇ V2.
  • FIG. 7 shows an operation timing chart according to the second embodiment. This figure shows a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.
  • ⁇ V1 and ⁇ V2 are vertical drive pulses generated by the vertical drive circuit 103
  • ⁇ V1 ′ and ⁇ V2 ′ are vertical drive pulses generated by the binary pulse generation circuit 203
  • HC1 is a ternary / binary switching control signal. 202.
  • the vertical drive pulses ⁇ V2, ⁇ V3, ⁇ V5, ⁇ V6, ⁇ V2 ′, and ⁇ V2 ′′ are the third voltage VL, and the vertical transfer unit 205 cannot store signals (barrier state).
  • the vertical drive pulses ⁇ V 1, ⁇ V 4, ⁇ V 1 ′, ⁇ V 1 ′′ are the second voltage VM, and a signal can be accumulated in the vertical transfer unit 205 (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the low level. VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the high level. Is suppressed, and the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V 2 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V2 ′ to which the same drive pulse as the vertical drive pulse ⁇ V2 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the low level. VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V2 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the high level. And the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the high level. VH is suppressed and the signal charge is not read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the low level. Is applied as it is, and the signal charge is read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V2 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the high level. VH is suppressed and the signal charge is not read out.
  • the vertical drive pulse ⁇ V2 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V2 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the low level. Is applied as it is, and the signal charge is read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM, respectively, and the signal charges in the vertical transfer unit 205 are transferred horizontally. Transfer in the direction of the part.
  • the present embodiment it is possible to reduce the number of terminals related to vertical driving between the vertical driving circuit 103 and the solid-state imaging device 101 in the thinning-out operation.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).
  • FIG. 8 shows a configuration of a solid-state imaging device according to the third embodiment of the present invention.
  • the basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 shown in the figure is the same as that of the first embodiment except for the number of vertical phases and the connection configuration of the binary pulse generation circuit 203.
  • the drive electrodes 207 of the vertical transfer units 205 in each column have a vertical three-phase configuration in which three types of drive electrodes are arranged as a set in the vertical direction.
  • the binary pulse generation circuit 203 is connected so that the first voltage VH is not applied to the other peripheral pixels.
  • FIG. 9 is a diagram illustrating an operation timing chart of the solid-state imaging device according to the third embodiment. This figure shows a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.
  • vertical drive pulses ⁇ V 1, ⁇ V 2, and ⁇ V 3 are vertical drive pulses generated by the vertical drive circuit 103, and ⁇ V 1 ′, ⁇ V 2 ′, and ⁇ V 3 ′ are vertical drive pulses generated by the binary pulse generation circuit 203.
  • HC1 is a ternary / binary switching control signal 202.
  • the vertical drive pulses ⁇ V2 and ⁇ V2 ′ are the third voltage VL, and the signal cannot be accumulated in the vertical transfer unit 205 (barrier state).
  • the vertical drive pulses ⁇ V 1, ⁇ V 3, ⁇ V 1 ′, and ⁇ V 3 ′ are the second voltage VM, and the signal can be accumulated in the vertical transfer unit 205 (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM.
  • the voltage VH of 1 is suppressed and the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V3, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V3 ′ to which the same drive pulse as the vertical drive pulse ⁇ V3 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM.
  • the voltage VH of 1 is suppressed and the signal charge is not read out.
  • the first voltage VH is applied to the vertical drive pulse ⁇ V2, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V2 ′ to which the same drive pulse as the vertical drive pulse ⁇ V2 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM.
  • the voltage VH of 1 is suppressed and the signal charge is not read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM, respectively, and the signal charges in the vertical transfer unit 205 are transferred horizontally. Transfer in the direction of the part.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical three-phase configuration. However, the vertical transfer unit 205 does not have to be a vertical three-phase, and may be any number that is equal to or greater than the number of phases that can be vertically transferred (three or more phases).
  • FIG. 13 shows a configuration of a solid-state imaging device according to the fourth embodiment of the present invention.
  • the basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 in the figure is the same as that of the first embodiment except for the ternary / binary pulse switching control signal 202.
  • the horizontal drive pulse 209 of the horizontal transfer unit 210 that controls horizontal transfer is used as a ternary / binary pulse switching control signal.
  • FIG. 14 shows an operation timing chart of the solid-state imaging device of the present embodiment.
  • the figure is the same as the first embodiment except that the ternary / binary pulse switching control signal 202 is a horizontal drive pulse 209 composed of a value ⁇ H1 and a value ⁇ H2.
  • the vertical drive pulses ⁇ V1, ⁇ V2, ⁇ V3, ⁇ V4, ⁇ V5, ⁇ V1 ′, ⁇ V2 ′, ⁇ V3 ′, ⁇ V4 ′, ⁇ V5 ′, ⁇ V1 ′′, ⁇ V2 ′′, ⁇ V3 ′′, ⁇ V4 ′′, ⁇ V5 ′′ are
  • the third voltage VL is incapable of signal accumulation (barrier state) in the vertical transfer unit 205.
  • the vertical drive pulses ⁇ V6, ⁇ V6 ′, and ⁇ V6 ′′ are the second voltage VM, and the vertical transfer unit 205 In this state, the signal can be accumulated (storage state).
  • the first voltage VH is applied to the vertical drive pulse ⁇ V1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205.
  • the vertical drive pulse ⁇ V1 ′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal 202 (the horizontal drive pulse 209 of the value ⁇ H1) low. Since it is level, the first voltage VH is applied as it is, and the signal charge is read out.
  • the vertical drive pulse ⁇ V1 ′′ to which the same drive pulse as the vertical drive pulse ⁇ V1 is supplied through the binary pulse generation circuit 203 has a ternary / binary switching control signal 202 (horizontal drive pulse 209 of value ⁇ H2) at a high level. Therefore, the propagation of the first voltage VH is suppressed, and the signal charge is not read out.
  • the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL, and from the third voltage VL to the second voltage VM.
  • the charge is transferred in the direction of the horizontal transfer unit 210.
  • the signal charge output from the horizontal transfer unit 210 is converted into a signal voltage or a signal current by the signal charge detection unit 211 and output.
  • 12: 1 interlace operation can be performed in a vertical 6-phase configuration.
  • a vertical 12-phase configuration is required in order to perform the 12: 1 interlace operation.
  • an n: 1 interlace operation can be realized with the number of vertical phases of n / 2, and the terminals related to the vertical drive between the solid-state imaging device 101 and the vertical drive circuit 103 are set to n / The effect that the number can be reduced to two is obtained.
  • a configuration in which one electrode is provided in one pixel is described.
  • a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.
  • the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).
  • the present invention is particularly useful in a device using a solid-state imaging device having a high pixel count.
  • a solid-state imaging device having a high pixel count.
  • a digital still camera but also a digital video camera, a camera mounted on a mobile phone, an in-vehicle camera, a surveillance It is useful when applied to cameras.
  • Solid-state image sensor (CCD) 102 Timing signal generation circuit (TG) 103 Vertical drive circuit (VDr) 104 Pre-processing circuit (AFE) 105 Digital signal processing circuit (DSP) 201 vertical drive pulse 202 ternary / binary pulse switching control signal 203 binary pulse generation circuit 204 photodiode 205 vertical transfer unit 206 metal wiring 207 vertical drive electrode 208 bus line 209 horizontal drive pulse 210 horizontal transfer unit 211 signal charge detection unit 301 Transistor 302 Binary Pulse Generation Circuit Output Signal (Vertical Drive Pulse) 401 diode

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Abstract

Disclosed is a solid-state image capture device, wherein binary pulse generator circuits (203), which generate binary pulses from ternary pulses, are disposed; and vertical drive signals from a vertical drive circuit (103) are switched from ternary pulses to binary pulses by ternary/binary pulse switch control signals (202). The number of terminals between a solid state image capture element (101) and the vertical drive circuit (103) is thereby reduced. Thus, the number of terminals between the image capture element and the vertical drive circuit is reduced.

Description

固体撮像装置及びカメラSolid-state imaging device and camera

　本発明は、デジタルスチルカメラ等に用いられる固体撮像装置に関し、特に固体撮像素子と垂直駆動回路（ＶＤｒ）との間の端子数の削減に関する。 The present invention relates to a solid-state imaging device used for a digital still camera or the like, and more particularly to reduction of the number of terminals between a solid-state imaging device and a vertical drive circuit (VDr).

　近年、固体撮像素子の高画素化に伴い、固体撮像素子とその周辺回路における端子数の増加が問題となっている。 In recent years, with the increase in the number of pixels of a solid-state image sensor, an increase in the number of terminals in the solid-state image sensor and its peripheral circuits has become a problem.

　また、近年、High Definition動画（以下、ＨＤ動画という）と呼ばれる高解像度の動画を撮影できる機能も増加してきているが、フレームレートの低下を防ぐために、有効画素以外の行は通常よりも高速に垂直転送させており、これにより、スミアと呼ばれる高輝度光が入射した時に発生する白飛び現象が、同じ動画の一画面上で違うというスミア段差の問題が発生している。 In recent years, functions that can shoot high-definition movies called High-Definition movies (hereinafter referred to as HD movies) have increased, but in order to prevent a decrease in frame rate, rows other than effective pixels are faster than usual. Due to the vertical transfer, there is a problem of smear steps in which the whiteout phenomenon that occurs when high-luminance light called smear is incident is different on one screen of the same moving image.

　この問題を解決するために、従来では、有効画素以外は読み出さないという方法が提案されているが、この従来の方法では端子数が増加してしまう。 In order to solve this problem, a method in which only the effective pixels are not read has been proposed in the past, but this conventional method increases the number of terminals.

　そのため、端子数を削減する方法として、従来、例えば特許文献１には、タイミング信号発生回路（ＴＧ）に時分割多重回路を設け、読み出しパルスと垂直転送パルスとを時分割多重化することにより、タイミング信号発生回路と垂直駆動回路との間の端子数を削減する技術が提案されている。 Therefore, as a method for reducing the number of terminals, conventionally, for example, in Patent Document 1, a time division multiplexing circuit is provided in a timing signal generation circuit (TG), and a read pulse and a vertical transfer pulse are time division multiplexed. A technique for reducing the number of terminals between the timing signal generation circuit and the vertical drive circuit has been proposed.

特開２００３－８９９５号公報JP 2003-8995 A

　しかしながら、前記特許文献１に記載の技術では、タイミング信号発生回路と垂直駆動回路との間の端子数は削減できても、固体撮像素子と垂直駆動回路との間の端子数は削減できなかった。 However, in the technique described in Patent Document 1, even if the number of terminals between the timing signal generation circuit and the vertical drive circuit can be reduced, the number of terminals between the solid-state imaging device and the vertical drive circuit cannot be reduced. .

　このような事情に鑑み、本発明の目的は、固体撮像素子と垂直駆動回路との間の端子数を削減できる固体撮像装置を提供することにある。 In view of such circumstances, an object of the present invention is to provide a solid-state imaging device capable of reducing the number of terminals between a solid-state imaging device and a vertical drive circuit.

　前記目的を達成するために、請求項１記載の発明の固体撮像装置では、２次元状に配列されたフォトダイオードと、前記フォトダイオードで光電変換された信号電荷を垂直方向へ転送する垂直転送部と、前記垂直転送部からの信号電荷を水平方向へ転送する水平転送部とを有し、第１の電圧を印加することにより前記フォトダイオードより信号電荷を垂直転送部に読み出し、前記読み出された信号電荷を前記第１の電圧より低い第２の電圧と前記第２の電圧より低い第３の電圧を印加することにより前記水平転送部に向かって転送する固体撮像装置において、前記固体撮像装置内において前記第１、第２、第３の電圧より構成される３値パルスから前記第２、第３の電圧より構成される２値パルスを生成する２値パルス生成回路を有し、前記３値パルスと前記２値パルス生成回路で生成された２値パルスとを３値／２値切り替え制御信号により切り替えることを特徴とする。 In order to achieve the above object, in the solid-state imaging device according to the first aspect of the present invention, two-dimensionally arranged photodiodes and a vertical transfer unit that transfers signal charges photoelectrically converted by the photodiodes in the vertical direction. And a horizontal transfer unit for transferring the signal charge from the vertical transfer unit in the horizontal direction, and by applying a first voltage, the signal charge is read from the photodiode to the vertical transfer unit and the read In the solid-state imaging device that transfers the signal charge toward the horizontal transfer unit by applying a second voltage lower than the first voltage and a third voltage lower than the second voltage, the solid-state imaging device A binary pulse generating circuit for generating a binary pulse composed of the second and third voltages from a ternary pulse composed of the first, second and third voltages, Ternary pulse and the generated binary pulse generating circuit and a binary pulse and switches the 3 / bi switching control signal.

　請求項２記載の発明は、前記請求項１記載の固体撮像装置において、前記２値パルス生成回路は、トランジスタからなることを特徴とする。 According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the binary pulse generation circuit includes a transistor.

　請求項３記載の発明は、前記請求項１記載の固体撮像装置において、前記２値パルス生成回路は、トランジスタ及びダイオードからなることを特徴とする。 According to a third aspect of the present invention, in the solid-state imaging device according to the first aspect, the binary pulse generation circuit includes a transistor and a diode.

　請求項４記載の発明は、前記請求項１記載の固体撮像装置において、前記２値パルス生成回路を制御する前記３値／２値切り替え制御信号は、ＨｉｇｈレベルとＬｏｗレベルとの２値パルスからなることを特徴とする。 According to a fourth aspect of the present invention, in the solid-state imaging device according to the first aspect, the ternary / binary switching control signal for controlling the binary pulse generation circuit is obtained from a binary pulse of a high level and a low level. It is characterized by becoming.

　請求項５記載の発明は、前記請求項１記載の固体撮像装置において、１画面分の信号電荷をｎ回（ｎは２以上の整数）に分けて前記垂直転送部に読み出すｎ：１インターレース読み出しにおいて、読み出し及び垂直転送を制御する駆動パルスの数をｎ／２にすることを特徴とする。 According to a fifth aspect of the present invention, in the solid-state imaging device according to the first aspect of the invention, n: 1 interlace reading is performed in which the signal charge for one screen is divided into n times (n is an integer of 2 or more) and read to the vertical transfer unit. The number of drive pulses for controlling reading and vertical transfer is n / 2.

　請求項６記載の発明は、前記請求項１記載の固体撮像装置において、前記フォトダイオードに溜まった信号電荷を特定の行については垂直転送部に読み出さない間引き読み出しにおいて、同一位相電極に繋がる垂直方向の連続画素に同時に前記第１の電圧が印加されないように、前記２値パルス生成回路を間引こうとする行に挿入し、前記挿入された２値パルス生成回路を前記３値／２値切り替え制御信号により制御することを特徴とする。 According to a sixth aspect of the present invention, in the solid-state imaging device according to the first aspect, in the thinning readout in which the signal charges accumulated in the photodiode are not read out to the vertical transfer unit for a specific row, the vertical direction connected to the same phase electrode The binary pulse generation circuit is inserted into a row to be thinned out so that the first voltage is not simultaneously applied to the continuous pixels of the pixel, and the inserted binary pulse generation circuit is switched to the ternary / binary switching. Control is performed by a control signal.

　請求項７記載の発明は、前記請求項１記載の固体撮像装置において、画像のアスペクト比が１６：９になるように１画面の中央部分の行から信号電荷を垂直転送部に読み出す動画撮影モードにおいて、読み出さない周辺の行に前記第１の電圧が印加されないように、前記２値パルス生成回路を読み出さない行に挿入し、前記挿入された２値パルス生成回路を前記３値／２値切り替え制御信号により制御することを特徴とする。 According to a seventh aspect of the present invention, in the solid-state imaging device according to the first aspect of the present invention, a moving image photographing mode for reading out signal charges from a row in a central portion of one screen to a vertical transfer unit so that an image aspect ratio is 16: 9. In this case, the binary pulse generation circuit is inserted in a row not to be read so that the first voltage is not applied to a peripheral row not to be read, and the inserted binary pulse generation circuit is switched to the ternary / binary switching. Control is performed by a control signal.

　請求項８記載の発明は、前記請求項１記載の固体撮像装置において、前記２値パルス生成回路を制御する前記３値／２値切り替え制御信号は、水平転送を制御する駆動パルスであることを特徴とする。 According to an eighth aspect of the present invention, in the solid-state imaging device according to the first aspect, the ternary / binary switching control signal for controlling the binary pulse generation circuit is a drive pulse for controlling horizontal transfer. Features.

　請求項９記載の発明のカメラは、前記請求項１～８の何れか１項に記載の固体撮像装置を備えたことを特徴とする。 A camera according to a ninth aspect of the invention is characterized by including the solid-state imaging device according to any one of the first to eighth aspects.

　以上により、請求項１～９記載の発明の固体撮像装置では、その固体撮像装置内で３値パルスから２値パルスを生成し、制御信号で切り替える構成として、従来、固体撮像装置に３値パルスと２値パルスとを別々に入力する構成を不要にしたので、固体撮像素子と垂直駆動回路との間の端子数を削減することが可能となる。 As described above, in the solid-state imaging device according to the first to ninth aspects of the present invention, as a configuration in which a binary pulse is generated from a ternary pulse in the solid-state imaging device and is switched by a control signal, a conventional ternary pulse is applied to the solid-state imaging device. Therefore, it is possible to reduce the number of terminals between the solid-state imaging device and the vertical drive circuit.

　また、本発明によれば、ＨＤ動画モードで発生しているスミア段差を、端子数を増やさずに解消することが可能である。 Further, according to the present invention, it is possible to eliminate the smear level difference occurring in the HD moving image mode without increasing the number of terminals.

　以上説明したように、請求項１～９記載の発明の固体撮像装置によれば、固体撮像素子と垂直駆動回路との間の端子数を削減でき、また、ＨＤ動画モードで発生しているスミア段差を、端子数を増やさずに解消できる効果を奏する。 As described above, according to the solid-state imaging device of the first to ninth aspects of the invention, the number of terminals between the solid-state imaging device and the vertical drive circuit can be reduced, and smear occurring in the HD moving image mode can be achieved. The step can be eliminated without increasing the number of terminals.

図１は本発明の第１の実施形態に係るカメラの概略構成図である。FIG. 1 is a schematic configuration diagram of a camera according to the first embodiment of the present invention. 図２は本発明の第１の実施形態に係る固体撮像装置の構成図である。FIG. 2 is a configuration diagram of the solid-state imaging device according to the first embodiment of the present invention. 図３は同固体撮像装置に備える２値パルス生成回路の構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of a binary pulse generation circuit provided in the solid-state imaging device. 図４は同固体撮像装置に備える２値パルス生成回路の他の構成例を示す図である。FIG. 4 is a diagram showing another configuration example of the binary pulse generation circuit provided in the solid-state imaging device. 図５は本発明の第１の実施形態に係る固体撮像装置の動作タイミングチャート図である。FIG. 5 is an operation timing chart of the solid-state imaging device according to the first embodiment of the present invention. 図６は本発明の第２の実施形態に係る固体撮像装置の構成図である。FIG. 6 is a configuration diagram of a solid-state imaging device according to the second embodiment of the present invention. 図７は同固体撮像装置の動作タイミングチャート図である。FIG. 7 is an operation timing chart of the solid-state imaging device. 図８は本発明の第３の実施形態に係る固体撮像装置の構成図である。FIG. 8 is a configuration diagram of a solid-state imaging device according to the third embodiment of the present invention. 図９は同固体撮像装置の動作タイミングチャート図である。FIG. 9 is an operation timing chart of the solid-state imaging device. 図１０は１２：１インターレース動作を行う場合の従来の固体撮像装置の構成図である。FIG. 10 is a configuration diagram of a conventional solid-state imaging device when performing a 12: 1 interlace operation. 図１１は間引く行と間引かない行とを別々の駆動パルスで制御する場合の従来の固体撮像装置の構成図である。FIG. 11 is a configuration diagram of a conventional solid-state imaging device in the case where thinned rows and non-thinned rows are controlled by separate drive pulses. 図１２は画面中央の有効画素のみを読み出す場合の従来の固体撮像装置の構成図である。FIG. 12 is a configuration diagram of a conventional solid-state imaging device when only the effective pixel at the center of the screen is read. 図１３は本発明の第４の実施形態に係る固体撮像装置の構成図である。FIG. 13 is a configuration diagram of a solid-state imaging device according to the fourth embodiment of the present invention. 図１４は同固体撮像装置の動作タイミングチャート図である。FIG. 14 is an operation timing chart of the solid-state imaging device.

　（第１の実施形態）
　以下、本発明の第１の実施形態における固体撮像装置について、図面を参照しながら説明する。 (First embodiment)
Hereinafter, a solid-state imaging device according to a first embodiment of the present invention will be described with reference to the drawings.

　図１は、一般的な固体撮像素子を用いたカメラの構成を示す。同図において、１０１は固体撮像素子（ＣＣＤ）、１０２は固体撮像素子用の駆動タイミングを制御するタイミング信号発生回路（ＴＧ）、１０３は前記タイミング信号発生回路１０２から入力される信号を固体撮像素子１０１の駆動信号として電圧変換を行う垂直駆動回路（ＶＤｒ）、１０４は前記固体撮像素子１０１からの信号を受けて、ＣＤＳやＡ／Ｄ変換を行う前処理回路（ＡＦＥ）、１０５は前記前処理回路１０４からの信号を受けて、画素補間や輝度・色信号処理などを行うデジタル信号処理回路（ＤＳＰ）である。 FIG. 1 shows a configuration of a camera using a general solid-state image sensor. In the figure, 101 is a solid-state image sensor (CCD), 102 is a timing signal generation circuit (TG) for controlling the drive timing for the solid-state image sensor, and 103 is a signal input from the timing signal generation circuit 102. 101 is a vertical drive circuit (VDr) that performs voltage conversion as a drive signal of 101, 104 is a preprocessing circuit (AFE) that receives a signal from the solid-state image sensor 101 and performs CDS or A / D conversion, and 105 is the preprocessing. A digital signal processing circuit (DSP) that receives a signal from the circuit 104 and performs pixel interpolation, luminance / color signal processing, and the like.

　図２は、本発明の第１の実施形態に係る固体撮像装置の構成を示し、前記図１のカメラに備える固体撮像素子（ＣＣＤ）１０１と、垂直駆動回路（ＶＤｒ）１０３とを有する。 FIG. 2 shows a configuration of the solid-state imaging device according to the first embodiment of the present invention, and includes a solid-state imaging device (CCD) 101 and a vertical drive circuit (VDr) 103 provided in the camera of FIG.

　図２において、垂直駆動回路１０３は、固体撮像素子１０１内のフォトダイオード（後述）より信号電荷を固体撮像素子１０１内の垂直転送部（後述）に読み出すための第１の電圧ＶＨと、前記垂直転送部から水平転送部に向かって信号電荷を転送するための前記第１の電圧ＶＨよりも低い第２の電圧ＶＭと、前記第２の電圧ＶＭより低い第３の電圧ＶＬとの３値パルスでできた垂直駆動パルス２０１（φＶ１、φＶ２、φＶ３、φＶ４、φＶ５、φＶ６）を生成する。 In FIG. 2, the vertical drive circuit 103 includes a first voltage VH for reading a signal charge from a photodiode (described later) in the solid-state imaging device 101 to a vertical transfer unit (described later) in the solid-state imaging device 101, and the vertical driving circuit 103. A ternary pulse of a second voltage VM lower than the first voltage VH and a third voltage VL lower than the second voltage VM for transferring signal charges from the transfer unit toward the horizontal transfer unit The vertical drive pulse 201 (φV1, φV2, φV3, φV4, φV5, φV6) generated in the above is generated.

　また、図２において、固体撮像素子１０１は、１画素のセルを構成するフォトダイオード２０４と、前記フォトダイオード２０４から読み出した信号電荷を垂直に転送するための垂直転送部２０５と、前記垂直転送部２０５を駆動するための駆動電極２０７と、前記駆動電極２０７に対して垂直駆動パルス２０１を供給するための金属配線２０６と、前記金属配線２０６に対して垂直駆動パルス２０１を供給するためのバスライン２０８とを備え、前記金属配線２０６とバスライン２０８との間に２値パルス生成回路２０３を設けた構成を有する。 In FIG. 2, the solid-state imaging device 101 includes a photodiode 204 that forms a cell of one pixel, a vertical transfer unit 205 for vertically transferring a signal charge read from the photodiode 204, and the vertical transfer unit. A driving electrode 207 for driving 205, a metal wiring 206 for supplying a vertical driving pulse 201 to the driving electrode 207, and a bus line for supplying a vertical driving pulse 201 to the metal wiring 206 208, and a binary pulse generation circuit 203 is provided between the metal wiring 206 and the bus line 208.

　前記２値パルス生成回路２０３は、固体撮像素子１０１の外部から供給される３値／２値切り替え制御信号２０２（ＨＣ１、ＨＣ２）により、垂直駆動パルス２０１を３値（ＶＨ、ＶＭ、ＶＬ）で供給するのか、２値（ＶＭ、ＶＬ）で供給するのかを切り替える。また、前記３値／２値切り替え制御信号２０２は、第１の電圧ＶＨと第２の電圧ＶＭとの２値パルスで構成される。 The binary pulse generation circuit 203 uses the ternary / binary switching control signal 202 (HC1, HC2) supplied from the outside of the solid-state imaging device 101 to convert the vertical drive pulse 201 into three values (VH, VM, VL). Switching between supply and binary (VM, VL) switching. The ternary / binary switching control signal 202 is composed of binary pulses of a first voltage VH and a second voltage VM.

　図２では、各列の垂直転送部２０５の駆動電極２０７は、各々、垂直方向に６種類の駆動電極を１組として繰り返すように配置されている垂直６相構成とし、その垂直６相毎に２値パルス生成回路２０３に繋がる３値／２値切り替え制御信号２０２を値ＨＣ１と値ＨＣ２とにより変更する。 In FIG. 2, the drive electrodes 207 of the vertical transfer units 205 in each column have a vertical 6-phase configuration in which 6 types of drive electrodes are repeated as a set in the vertical direction. The ternary / binary switching control signal 202 connected to the binary pulse generation circuit 203 is changed according to the value HC1 and the value HC2.

　図３は、図２に示した２値パルス生成回路２０３の内部構成例を示す。同図において、２値パルス生成回路２０３はトランジスタ３０１で構成されており、トランジスタ３０１のゲートに３値／２値切り替え制御信号２０２（ＨＣｘ）が、ドレインに垂直駆動パルス２０１（φＶｘ）が、ソースに２値パルス生成回路２０３の出力信号３０２（φＶｘ’）が各々接続されている。 FIG. 3 shows an example of the internal configuration of the binary pulse generation circuit 203 shown in FIG. In the figure, a binary pulse generation circuit 203 is composed of a transistor 301. A ternary / binary switching control signal 202 (HCx) is supplied to the gate of the transistor 301, and a vertical drive pulse 201 (φVx) is supplied to the drain. Are connected to the output signal 302 (φVx ′) of the binary pulse generation circuit 203.

　この構成においては、３値／２値切り替え制御信号２０２がＨｉｇｈレベルの場合、トランジスタ３０１のドレインからソースに電流が流れ、入力された垂直駆動パルス２０１がそのまま出力される。一方、３値／２値切り替え制御信号２０２がＬｏｗレベルの場合には、トランジスタ３０１のドレインからソースに電流が流れないため、Ｌｏｗレベルになる直前の垂直駆動パルス２０１の状態が保持される。 In this configuration, when the ternary / binary switching control signal 202 is at a high level, a current flows from the drain to the source of the transistor 301, and the input vertical drive pulse 201 is output as it is. On the other hand, when the ternary / binary switching control signal 202 is at the low level, no current flows from the drain to the source of the transistor 301, so the state of the vertical drive pulse 201 immediately before the low level is maintained.

　図４は、前記図２に示した２値パルス生成回路２０３の別の構成例を示す。同図において、２値パルス生成回路２０３は、ダイオード４０１とトランジスタ３０１とにより構成されており、ダイオード４０１のアノードに垂直駆動パルス２０１（φＶｘ）が、カソードにトランジスタ３０１のドレインが、トランジスタ３０１のゲートに３値／２値切り替え制御信号２０２（ＨＣｘ）が、トランジスタ３０１のソースに０Ｖであるグランド（ＧＮＤ）が各々接続されている。 FIG. 4 shows another configuration example of the binary pulse generation circuit 203 shown in FIG. In the figure, a binary pulse generation circuit 203 is composed of a diode 401 and a transistor 301, the vertical drive pulse 201 (φVx) is provided at the anode of the diode 401, the drain of the transistor 301 is provided at the cathode, and the gate of the transistor 301 is provided. The ternary / binary switching control signal 202 (HCx) is connected to the transistor 301, and the ground (GND) of 0V is connected to the source of the transistor 301.

　この構成においては、３値／２値切り替え制御信号２０２がＬｏｗレベルの場合には、入力された垂直駆動パルス２０１がそのまま出力される。次に、３値／２値切り替え制御信号２０２がＨｉｇｈレベルの場合、ダイオード４０１からトランジスタ３０１を通してＧＮＤに電流が流れ、入力された垂直駆動パルス２０１の第１の電圧ＶＨが抑制される。 In this configuration, when the ternary / binary switching control signal 202 is at the low level, the input vertical drive pulse 201 is output as it is. Next, when the ternary / binary switching control signal 202 is at a high level, a current flows from the diode 401 to the GND through the transistor 301, and the first voltage VH of the input vertical drive pulse 201 is suppressed.

　図５は、本実施形態の固体撮像装置の動作タイミングチャートを示す。尚、同図は、図４に示したトランジスタ３０１とダイオード４０１とで構成された２値パルス生成回路２０３を用いた場合のタイミングチャートである。 FIG. 5 shows an operation timing chart of the solid-state imaging device of the present embodiment. This figure is a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.

　同図のタイミングチャートにおいて、φＶ１、φＶ２、φＶ３、φＶ４、φＶ５、φＶ６は垂直駆動回路１０３で生成された垂直駆動パルスであり、φＶ１’、φＶ２’、φＶ３’、φＶ４’、φＶ５’、φＶ６’、φＶ１”、φＶ２”、φＶ３”、φＶ４”、φＶ５”、φＶ６”は２値パルス生成回路２０３で生成された垂直駆動パルスであり、ＨＣ１、ＨＣ２は３値／２値切り替え制御信号２０２である。 In the timing chart of the figure, φV1, φV2, φV3, φV4, φV5, and φV6 are vertical drive pulses generated by the vertical drive circuit 103, and φV1 ′, φV2 ′, φV3 ′, φV4 ′, φV5 ′, and φV6 ′. , ΦV1 ″, φV2 ″, φV3 ″, φV4 ″, φV5 ″, φV6 ″ are vertical drive pulses generated by the binary pulse generation circuit 203, and HC1 and HC2 are ternary / binary switching control signals 202. .

　図５の時間ｔ１において、垂直駆動パルスφＶ１、φＶ２、φＶ３、φＶ４、φＶ５、φＶ１’、φＶ２’、φＶ３’、φＶ４’、φＶ５’、φＶ１”、φＶ２”、φＶ３”、φＶ４”、φＶ５”は第３の電圧ＶＬであり、垂直転送部２０５に信号蓄積不能（バリア状態）となっており、垂直駆動パルスφＶ６、φＶ６’、φＶ６”は第２の電圧ＶＭであり、垂直転送部２０５に信号蓄積可能な状態（ストレージ状態）となっている。 At time t1 in FIG. 5, the vertical drive pulses φV1, φV2, φV3, φV4, φV5, φV1 ′, φV2 ′, φV3 ′, φV4 ′, φV5 ′, φV1 ″, φV2 ″, φV3 ″, φV4 ″, φV5 ″ are The third voltage VL is incapable of accumulating signals in the vertical transfer unit 205 (barrier state), and the vertical drive pulses φV6, φV6 ′, φV6 ″ are the second voltage VM, and signals to the vertical transfer unit 205 It can be stored (storage state).

　図５の時間ｔ２において、垂直駆動パルスφＶ１に対して第１の電圧ＶＨを印加し、フォトダイオード２０４から垂直転送部２０５に信号電荷を読み出せる状態にする。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されているφＶ１’は、３値／２値切り替え制御信号２０２（ＨＣ１）がＬｏｗレベルであるため、第１の電圧ＶＨはそのまま印加され、信号電荷は読み出される。また、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１”は、３値／２値切り替え制御信号２０２（ＨＣ２）がＨｉｇｈレベルであるため、第１の電圧ＶＨの伝播が抑制され、信号電荷は読み出されない。 At time t2 in FIG. 5, the first voltage VH is applied to the vertical drive pulse φV1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205. At this time, φV1 ′ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal 202 (HC1) is at the low level. VH is applied as it is, and the signal charge is read out. Also, the vertical drive pulse φV1 ″ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 is the first because the ternary / binary switching control signal 202 (HC2) is at the high level. Propagation of the voltage VH is suppressed, and the signal charge is not read out.

　図５の時間ｔ３以降において、垂直駆動パルス２０１を第２の電圧ＶＭから第３の電圧ＶＬに、第３の電圧ＶＬから第２の電圧ＶＭに各々変化させて、垂直転送部２０５内の信号電荷を水平転送部（図示せず）の方向へ転送する。前記水平転送部から出力される信号電荷は、図示しない信号電荷検出部により、信号電圧又は信号電流に変換されて出力される。 After time t3 in FIG. 5, the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM. Charges are transferred in the direction of a horizontal transfer unit (not shown). The signal charge output from the horizontal transfer unit is converted into a signal voltage or a signal current and output by a signal charge detection unit (not shown).

　以上の動作により、垂直６相構成で１２：１インターレース動作を行うことが可能となる。従来の構成においては、図１０に示すように、１２：１インターレース動作を行うためには、垂直１２相構成が必要であった。 By the above operation, 12: 1 interlace operation can be performed in a vertical 6-phase configuration. In the conventional configuration, as shown in FIG. 10, in order to perform the 12: 1 interlace operation, a vertical 12-phase configuration is required.

　つまり、本実施形態によれば、ｎ：１インターレース動作をｎ／２の垂直相数で実現可能であり、固体撮像素子１０１と垂直駆動回路１０３との間の垂直駆動とに係わる端子をｎ／２本に削減可能という効果が得られる。 That is, according to the present embodiment, an n: 1 interlace operation can be realized with the number of vertical phases of n / 2, and the terminals related to the vertical drive between the solid-state imaging device 101 and the vertical drive circuit 103 are set to n / The effect that it can be reduced to two is obtained.

　尚、本実施形態では、１画素に１電極を設ける構成を記載したが、１画素に１電極を設ける構成である必要はなく、１画素に２電極以上を設ける構成でも良い。 In the present embodiment, a configuration in which one electrode is provided in one pixel is described. However, a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.

　また、本実施形態では、垂直転送部２０５を垂直６相構成で記載したが、垂直６相である必要はなく、垂直転送可能な相数以上（３相以上）であれば良い。 In the present embodiment, the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).

　（第２の実施形態）
　以下、本発明の第２の実施形態における固体撮像装置について、図面を参照しながら説明する。 (Second Embodiment)
Hereinafter, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to the drawings.

　図６は、本発明の第２の実施形態に係る固体撮像装置の構成を示す。尚、同図における固体撮像素子１０１と垂直駆動回路１０３との基本的な構成は、垂直相数と２値パルス生成回路２０３の接続構成とを除き、前記第１の実施形態と同じである。 FIG. 6 shows a configuration of a solid-state imaging device according to the second embodiment of the present invention. The basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 in the figure is the same as that of the first embodiment except for the number of vertical phases and the connection configuration of the binary pulse generation circuit 203.

　図６の固体撮像装置では、各列の垂直転送部２０５の駆動電極２０７は、各々、垂直方向に６種類の駆動電極を１組として繰り返すように配置されている垂直６相構成とし、垂直駆動パルスφＶ１、φＶ２において同一位相電極に繋がる垂直方向の連続画素に同時に第１の電圧ＶＨが印加されないように２値パルス生成回路２０３を接続する。 In the solid-state imaging device of FIG. 6, the drive electrodes 207 of the vertical transfer unit 205 in each column have a vertical 6-phase configuration in which six types of drive electrodes are arranged as a set in the vertical direction. The binary pulse generation circuit 203 is connected so that the first voltage VH is not simultaneously applied to the continuous pixels in the vertical direction connected to the same phase electrode in the pulses φV1 and φV2.

　図７は、本第２の実施形態に係る動作タイミングチャートを示す。尚、同図は、図４に示したトランジスタ３０１とダイオード４０１とにより構成された２値パルス生成回路２０３を用いた場合のタイミングチャートを示している。 FIG. 7 shows an operation timing chart according to the second embodiment. This figure shows a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.

　図７において、φＶ１、φＶ２は垂直駆動回路１０３で生成された垂直駆動パルス、φＶ１’、φＶ２’は２値パルス生成回路２０３で生成された垂直駆動パルス、ＨＣ１は３値／２値切り替え制御信号２０２である。 In FIG. 7, φV1 and φV2 are vertical drive pulses generated by the vertical drive circuit 103, φV1 ′ and φV2 ′ are vertical drive pulses generated by the binary pulse generation circuit 203, and HC1 is a ternary / binary switching control signal. 202.

　図７では、時間ｔ１において、垂直駆動パルスφＶ２、φＶ３、φＶ５、φＶ６、φＶ２’、φＶ２”は第３の電圧ＶＬであり、垂直転送部２０５に信号蓄積不能（バリア状態）となっている。一方、垂直駆動パルスφＶ１、φＶ４、φＶ１’、φＶ１”は第２の電圧ＶＭであり、垂直転送部２０５に信号蓄積可能な状態（ストレージ状態）となっている。 In FIG. 7, at time t1, the vertical drive pulses φV2, φV3, φV5, φV6, φV2 ′, and φV2 ″ are the third voltage VL, and the vertical transfer unit 205 cannot store signals (barrier state). On the other hand, the vertical drive pulses φV 1, φV 4, φV 1 ′, φV 1 ″ are the second voltage VM, and a signal can be accumulated in the vertical transfer unit 205 (storage state).

　時間ｔ２において、垂直駆動パルスφＶ１に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出せる状態にする。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１’は、３値／２値切り替え制御信号ＨＣ１がＬｏｗレベルであるため、第１の電圧ＶＨはそのまま印加され、信号電荷は読み出される。また、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１”は、３値／２値切り替え制御信号ＨＣ２がＨｉｇｈレベルであるため、第１の電圧ＶＨが抑制され、信号電荷は読み出されない。 At time t2, the first voltage VH is applied to the vertical drive pulse φV1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV1 ′ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the low level. VH is applied as it is, and the signal charge is read out. Further, the vertical drive pulse φV1 ″ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the high level. Is suppressed, and the signal charge is not read out.

　時間ｔ３において、垂直駆動パルスφＶ２に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出せる状態にする。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ２と同じ駆動パルスが供給されている垂直駆動パルスφＶ２’は、３値／２値切り替え制御信号ＨＣ１がＬｏｗレベルであるため、第１の電圧ＶＨはそのまま印加され、信号電荷は読み出される。また、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ２”は、３値／２値切り替え制御信号ＨＣ２がＨｉｇｈレベルであるため、第１の電圧ＶＨの電圧が抑制され、信号電荷は読み出されない。 At time t 3, the first voltage VH is applied to the vertical drive pulse φV 2 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV2 ′ to which the same drive pulse as the vertical drive pulse φV2 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the low level. VH is applied as it is, and the signal charge is read out. Further, the vertical drive pulse φV2 ″ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the high level. And the signal charge is not read out.

　時間ｔ４において、垂直駆動パルスφＶ１に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出せる状態にする。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１’は、３値／２値切り替え制御信号ＨＣ１がＨｉｇｈレベルであるため、第１の電圧ＶＨが抑制され、信号電荷は読み出されない。また、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１”は、３値／２値切り替え制御信号ＨＣ２がＬｏｗレベルであるため、第１の電圧ＶＨはそのまま印加され、信号電荷は読み出される。 At time t4, the first voltage VH is applied to the vertical drive pulse φV1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV1 ′ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the high level. VH is suppressed and the signal charge is not read out. Further, the vertical drive pulse φV1 ″ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the low level. Is applied as it is, and the signal charge is read out.

　時間ｔ５において、垂直駆動パルスφＶ１に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出せる状態にする。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ２’は、３値／２値切り替え制御信号ＨＣ１がＨｉｇｈレベルであるため、第１の電圧ＶＨが抑制され、信号電荷は読み出されない。また、２値パルス生成回路２０３を通して垂直駆動パルスφＶ２と同じ駆動パルスが供給されている垂直駆動パルスφＶ２”は、３値／２値切り替え制御信号ＨＣ２がＬｏｗレベルであるため、第１の電圧ＶＨはそのまま印加され、信号電荷は読み出される。 At time t5, the first voltage VH is applied to the vertical drive pulse φV1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV2 ′ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the first voltage because the ternary / binary switching control signal HC1 is at the high level. VH is suppressed and the signal charge is not read out. Further, the vertical drive pulse φV2 ″ to which the same drive pulse as the vertical drive pulse φV2 is supplied through the binary pulse generation circuit 203 has the first voltage VH because the ternary / binary switching control signal HC2 is at the low level. Is applied as it is, and the signal charge is read out.

　時間ｔ６以降において、垂直駆動パルス２０１を第２の電圧ＶＭから第３の電圧ＶＬへ、第３の電圧ＶＬから第２の電圧ＶＭに各々変化させ、垂直転送部２０５内の信号電荷を水平転送部方向へ転送する。 After time t6, the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM, respectively, and the signal charges in the vertical transfer unit 205 are transferred horizontally. Transfer in the direction of the part.

　以上の動作により、垂直方向の画素を間引くことが可能となり、間引く行と間引かない行とを同一位相の駆動パルスで制御することが可能となる。従来の構成においては、図１１に示すように、間引く行と間引かない行とを別々の駆動パルスで制御する必要があった。 With the above operation, it becomes possible to thin out pixels in the vertical direction, and it is possible to control thinned rows and non-thinned rows with drive pulses of the same phase. In the conventional configuration, as shown in FIG. 11, it is necessary to control the thinned rows and the non-thinned rows with separate drive pulses.

　つまり、本実施形態によれば、間引き動作において、垂直駆動回路１０３と固体撮像素子１０１との間の垂直駆動に係わる端子数を削減できるという効果が得られる。 That is, according to the present embodiment, it is possible to reduce the number of terminals related to vertical driving between the vertical driving circuit 103 and the solid-state imaging device 101 in the thinning-out operation.

　尚、本実施形態では、１画素に１電極を設ける構成を記載したが、１画素に１電極を設ける構成である必要はなく、１画素に２電極以上を設ける構成でも良い。 In the present embodiment, a configuration in which one electrode is provided in one pixel is described. However, a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.

　また、本実施形態では、垂直転送部２０５を垂直６相構成で記載したが、垂直６相である必要はなく、垂直転送可能な相数以上（３相以上）であれば良い。 In the present embodiment, the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).

　（第３の実施形態）
　続いて、本発明の第３の実施形態における固体撮像装置について、図面を参照しながら説明する。 (Third embodiment)
Subsequently, a solid-state imaging device according to a third embodiment of the present invention will be described with reference to the drawings.

　図８は、本発明の第３の実施形態に係る固体撮像装置の構成を示す。同図に示した固体撮像素子１０１と垂直駆動回路１０３との基本的な構成は、垂直相数と２値パルス生成回路２０３の接続構成とを除き、前記第１の実施形態と同じである。 FIG. 8 shows a configuration of a solid-state imaging device according to the third embodiment of the present invention. The basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 shown in the figure is the same as that of the first embodiment except for the number of vertical phases and the connection configuration of the binary pulse generation circuit 203.

　図８の固体撮像装置では、各列の垂直転送部２０５の駆動電極２０７は、各々、垂直方向に３種類の駆動電極を１組として繰り返すように配置されている垂直３相構成とし、有効画素以外の周辺画素に第１の電圧ＶＨが印加されないように２値パルス生成回路２０３を接続する。 In the solid-state imaging device of FIG. 8, the drive electrodes 207 of the vertical transfer units 205 in each column have a vertical three-phase configuration in which three types of drive electrodes are arranged as a set in the vertical direction. The binary pulse generation circuit 203 is connected so that the first voltage VH is not applied to the other peripheral pixels.

　図９は、本第３の実施形態に係る固体撮像装置の動作タイミングチャートを示す図である。尚、同図は、図４に示したトランジスタ３０１とダイオード４０１とにより構成された２値パルス生成回路２０３を用いた場合のタイミングチャートを示す。 FIG. 9 is a diagram illustrating an operation timing chart of the solid-state imaging device according to the third embodiment. This figure shows a timing chart in the case of using the binary pulse generation circuit 203 composed of the transistor 301 and the diode 401 shown in FIG.

　図９において、垂直駆動パルスφＶ１、φＶ２、φＶ３は垂直駆動回路１０３で生成された垂直駆動パルスであり、φＶ１’、φＶ２’、φＶ３’は２値パルス生成回路２０３で生成された垂直駆動パルスであり、ＨＣ１は３値／２値切り替え制御信号２０２である。 In FIG. 9, vertical drive pulses φV 1, φV 2, and φV 3 are vertical drive pulses generated by the vertical drive circuit 103, and φV 1 ′, φV 2 ′, and φV 3 ′ are vertical drive pulses generated by the binary pulse generation circuit 203. HC1 is a ternary / binary switching control signal 202.

　図９では、時間ｔ１において、垂直駆動パルスφＶ２、φＶ２’は第３の電圧ＶＬであり、垂直転送部２０５に信号蓄積不能（バリア状態）となっている。一方、垂直駆動パルスφＶ１、φＶ３、φＶ１’、φＶ３’は第２の電圧ＶＭであり、垂直転送部２０５に信号蓄積可能な状態（ストレージ状態）となっている。 In FIG. 9, at time t1, the vertical drive pulses φV2 and φV2 ′ are the third voltage VL, and the signal cannot be accumulated in the vertical transfer unit 205 (barrier state). On the other hand, the vertical drive pulses φV 1, φV 3, φV 1 ′, and φV 3 ′ are the second voltage VM, and the signal can be accumulated in the vertical transfer unit 205 (storage state).

　時間ｔ２において、垂直駆動パルスφＶ１に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出す。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１’は、３値／２値切り替え制御信号ＨＣ１が第２の電圧ＶＭであるため、第１の電圧ＶＨが抑制され、信号電荷は読み出されない。 At time t2, the first voltage VH is applied to the vertical drive pulse φV1, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV1 ′ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM. The voltage VH of 1 is suppressed and the signal charge is not read out.

　時間ｔ３において、垂直駆動パルスφＶ３に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出す。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ３と同じ駆動パルスが供給されている垂直駆動パルスφＶ３’は、３値／２値切り替え制御信号ＨＣ１が第２の電圧ＶＭであるため、第１の電圧ＶＨが抑制され、信号電荷は読み出されない。 At time t3, the first voltage VH is applied to the vertical drive pulse φV3, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV3 ′ to which the same drive pulse as the vertical drive pulse φV3 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM. The voltage VH of 1 is suppressed and the signal charge is not read out.

　時間ｔ４において、垂直駆動パルスφＶ２に対して第１の電圧ＶＨを印加し、フォトダイオード２０４より垂直転送部２０５に信号電荷を読み出す。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ２と同じ駆動パルスが供給されている垂直駆動パルスφＶ２’は、３値／２値切り替え制御信号ＨＣ１が第２の電圧ＶＭであるため、第１の電圧ＶＨが抑制され、信号電荷は読み出されない。 At time t4, the first voltage VH is applied to the vertical drive pulse φV2, and the signal charge is read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV2 ′ to which the same drive pulse as the vertical drive pulse φV2 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal HC1 being the second voltage VM. The voltage VH of 1 is suppressed and the signal charge is not read out.

　時間ｔ５以降において、垂直駆動パルス２０１を第２の電圧ＶＭから第３の電圧ＶＬへ、第３の電圧ＶＬから第２の電圧ＶＭに各々変化させ、垂直転送部２０５内の信号電荷を水平転送部方向へ転送する。 After time t5, the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL and from the third voltage VL to the second voltage VM, respectively, and the signal charges in the vertical transfer unit 205 are transferred horizontally. Transfer in the direction of the part.

　以上の動作により、例えばカメラ等の動画撮影モードにおいて、画面中央の有効画素のみを読み出し、有効画素以外の周辺画素は読み出さないことが可能となる。従来の構成においては、図１２に示すように有効画素のみを読み出すためには、第１の電圧ＶＨを印加する端子と垂直駆動パルスとの端子を各々増やす必要があった。 By the above operation, it is possible to read out only the effective pixel at the center of the screen and not read out the peripheral pixels other than the effective pixel in the moving image shooting mode such as a camera. In the conventional configuration, as shown in FIG. 12, in order to read out only effective pixels, it is necessary to increase the number of terminals for applying the first voltage VH and the number of terminals for the vertical drive pulse.

　つまり、本実施形態によれば、現在課題となっているＨＤ動画モードにおけるスミア段差を、端子数を増やすことなく解決できるという効果が得られる。 That is, according to the present embodiment, there is an effect that it is possible to solve the smear level difference in the HD moving image mode that is currently a problem without increasing the number of terminals.

　尚、本実施形態では、１画素に１電極を設ける構成で記載したが、１画素に１電極を設ける構成である必要はなく、１画素に２電極以上を設ける構成でも良い。 In the present embodiment, a configuration in which one electrode is provided in one pixel is described. However, a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.

　また、本実施形態では、垂直転送部２０５を垂直３相構成で記載したが、垂直３相である必要はなく、垂直転送可能な相数以上（３相以上）であれば良い。 In the present embodiment, the vertical transfer unit 205 is described as having a vertical three-phase configuration. However, the vertical transfer unit 205 does not have to be a vertical three-phase, and may be any number that is equal to or greater than the number of phases that can be vertically transferred (three or more phases).

　（第４の実施形態）
　続いて、本発明の第４の実施形態における固体撮像装置について、図面を参照しながら説明する。 (Fourth embodiment)
Subsequently, a solid-state imaging device according to a fourth embodiment of the present invention will be described with reference to the drawings.

　図１３は本発明の第４の実施形態に係る固体撮像装置の構成を示す。尚、同図における固体撮像素子１０１と垂直駆動回路１０３との基本的な構成は、３値／２値パルス切り替え制御信号２０２を除き、前記第１の実施形態と同じである。 FIG. 13 shows a configuration of a solid-state imaging device according to the fourth embodiment of the present invention. The basic configuration of the solid-state imaging device 101 and the vertical drive circuit 103 in the figure is the same as that of the first embodiment except for the ternary / binary pulse switching control signal 202.

　図１３に示した固体撮像装置では、水平転送を制御する水平転送部２１０の水平駆動パルス２０９を３値／２値パルス切り替え制御信号として用いている。 In the solid-state imaging device shown in FIG. 13, the horizontal drive pulse 209 of the horizontal transfer unit 210 that controls horizontal transfer is used as a ternary / binary pulse switching control signal.

　図１４は本実施形態の固体撮像装置の動作タイミングチャートを示す。尚、同図は、３値／２値パルス切り替え制御信号２０２が、値ΦＨ１と値ΦＨ２とから成る水平駆動パルス２０９になっている点を除き、前記第１の実施形態と同じである。 FIG. 14 shows an operation timing chart of the solid-state imaging device of the present embodiment. The figure is the same as the first embodiment except that the ternary / binary pulse switching control signal 202 is a horizontal drive pulse 209 composed of a value ΦH1 and a value ΦH2.

　図１４の時間ｔ１において、垂直駆動パルスφＶ１、φＶ２、φＶ３、φＶ４、φＶ５、φＶ１’、φＶ２’、φＶ３’、φＶ４’、φＶ５’、φＶ１”、φＶ２”、φＶ３”、φＶ４”、φＶ５”は第３の電圧ＶＬであり、垂直転送部２０５に信号蓄積不能（バリア状態）となっている。また、垂直駆動パルスφＶ６、φＶ６’、φＶ６”は第２の電圧ＶＭであり、垂直転送部２０５に信号蓄積可能な状態（ストレージ状態）となっている。 At time t1 in FIG. 14, the vertical drive pulses φV1, φV2, φV3, φV4, φV5, φV1 ′, φV2 ′, φV3 ′, φV4 ′, φV5 ′, φV1 ″, φV2 ″, φV3 ″, φV4 ″, φV5 ″ are The third voltage VL is incapable of signal accumulation (barrier state) in the vertical transfer unit 205. The vertical drive pulses φV6, φV6 ′, and φV6 ″ are the second voltage VM, and the vertical transfer unit 205 In this state, the signal can be accumulated (storage state).

　図１４の時間ｔ２において、垂直駆動パルスφＶ１に対して第１の電圧ＶＨを印加し、フォトダイオード２０４から垂直転送部２０５に信号電荷を読み出せる状態にする。この時、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１’は、３値／２値切り替え制御信号２０２（値ΦＨ１の水平駆動パルス２０９）がＬｏｗレベルであるため、第１の電圧ＶＨはそのまま印加され、信号電荷は読み出される。また、２値パルス生成回路２０３を通して垂直駆動パルスφＶ１と同じ駆動パルスが供給されている垂直駆動パルスφＶ１”は、３値／２値切り替え制御信号２０２（値ΦＨ２の水平駆動パルス２０９）がＨｉｇｈレベルであるため、第１の電圧ＶＨの伝播が抑制され、信号電荷は読み出されない。 At time t2 in FIG. 14, the first voltage VH is applied to the vertical drive pulse φV1 so that the signal charge can be read from the photodiode 204 to the vertical transfer unit 205. At this time, the vertical drive pulse φV1 ′ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has the ternary / binary switching control signal 202 (the horizontal drive pulse 209 of the value ΦH1) low. Since it is level, the first voltage VH is applied as it is, and the signal charge is read out. Further, the vertical drive pulse φV1 ″ to which the same drive pulse as the vertical drive pulse φV1 is supplied through the binary pulse generation circuit 203 has a ternary / binary switching control signal 202 (horizontal drive pulse 209 of value ΦH2) at a high level. Therefore, the propagation of the first voltage VH is suppressed, and the signal charge is not read out.

　図１４の時間ｔ３以降において、垂直駆動パルス２０１を第２の電圧ＶＭから第３の電圧ＶＬに、第３の電圧ＶＬから第２の電圧ＶＭに各々変化させて、垂直転送部２０５内の信号電荷を水平転送部２１０の方向へ転送する。前記水平転送部２１０から出力される信号電荷は、信号電荷検出部２１１により、信号電圧又は信号電流に変換されて出力される。 After time t3 in FIG. 14, the vertical drive pulse 201 is changed from the second voltage VM to the third voltage VL, and from the third voltage VL to the second voltage VM. The charge is transferred in the direction of the horizontal transfer unit 210. The signal charge output from the horizontal transfer unit 210 is converted into a signal voltage or a signal current by the signal charge detection unit 211 and output.

　以上の動作により、垂直６相構成で１２：１インターレース動作を行うことが可能となる。従来の構成においては、図１０に示すように、１２：１インターレース動作を行うためには、垂直１２相構成が必要であった。 By the above operation, 12: 1 interlace operation can be performed in a vertical 6-phase configuration. In the conventional configuration, as shown in FIG. 10, in order to perform the 12: 1 interlace operation, a vertical 12-phase configuration is required.

　つまり、本実施形態によれば、ｎ：１インターレース動作をｎ／２の垂直相数で実現可能であり、固体撮像素子１０１と垂直駆動回路１０３との間の垂直駆動とに係わる端子をｎ／２本に削減可能であるという効果が得られる。 That is, according to the present embodiment, an n: 1 interlace operation can be realized with the number of vertical phases of n / 2, and the terminals related to the vertical drive between the solid-state imaging device 101 and the vertical drive circuit 103 are set to n / The effect that the number can be reduced to two is obtained.

　更に、３値／２値パルス切り替え制御信号を水平駆動パルス２０９で兼用することにより、制御信号分の端子が削減可能であるという効果が得られる。 Furthermore, by sharing the ternary / binary pulse switching control signal with the horizontal drive pulse 209, an effect that the terminals for the control signal can be reduced can be obtained.

　尚、本実施形態では、１画素に１電極を設ける構成を記載したが、１画素に１電極を設ける構成である必要はなく、１画素に２電極以上を設ける構成でも良い。 In the present embodiment, a configuration in which one electrode is provided in one pixel is described. However, a configuration in which one electrode is provided in one pixel is not necessary, and a configuration in which two or more electrodes are provided in one pixel may be used.

　また、本実施形態では、垂直転送部２０５を垂直６相構成で記載したが、垂直６相である必要はなく、垂直転送可能な相数以上（３相以上）であれば良い。 In the present embodiment, the vertical transfer unit 205 is described as having a vertical 6-phase configuration, but it is not necessary to have 6 vertical phases, and the number may be more than the number of vertically transferable phases (3 or more).

　以上説明したように、本発明は、高画素数の固体撮像素子を用いた機器において特に有用であり、例えば、デジタルスチルカメラのみならず、デジタルビデオカメラ、携帯電話機搭載用カメラ、車載カメラ、監視カメラなどに適用して、有用である。 As described above, the present invention is particularly useful in a device using a solid-state imaging device having a high pixel count. For example, not only a digital still camera but also a digital video camera, a camera mounted on a mobile phone, an in-vehicle camera, a surveillance It is useful when applied to cameras.

１０１　　　固体撮像素子（ＣＣＤ）
１０２　　　タイミング信号発生回路（ＴＧ）
１０３　　　垂直駆動回路（ＶＤｒ）
１０４　　　前処理回路（ＡＦＥ）
１０５　　　デジタル信号処理回路（ＤＳＰ）
２０１　　　垂直駆動パルス
２０２　　　３値／２値パルス切り替え制御信号
２０３　　　２値パルス生成回路
２０４　　　フォトダイオード
２０５　　　垂直転送部
２０６　　　金属配線
２０７　　　垂直駆動電極
２０８　　　バスライン
２０９　　　水平駆動パルス
２１０　　　水平転送部
２１１　　　信号電荷検出部
３０１　　　トランジスタ
３０２　　　２値パルス生成回路出力信号（垂直駆動パルス）
４０１　　　ダイオード 101 Solid-state image sensor (CCD)
102 Timing signal generation circuit (TG)
103 Vertical drive circuit (VDr)
104 Pre-processing circuit (AFE)
105 Digital signal processing circuit (DSP)
201 vertical drive pulse 202 ternary / binary pulse switching control signal 203 binary pulse generation circuit 204 photodiode 205 vertical transfer unit 206 metal wiring 207 vertical drive electrode 208 bus line 209 horizontal drive pulse 210 horizontal transfer unit 211 signal charge detection unit 301 Transistor 302 Binary Pulse Generation Circuit Output Signal (Vertical Drive Pulse)
401 diode

Claims (9)

　２次元状に配列されたフォトダイオードと、前記フォトダイオードで光電変換された信号電荷を垂直方向へ転送する垂直転送部と、前記垂直転送部からの信号電荷を水平方向へ転送する水平転送部とを有し、
　第１の電圧を印加することにより前記フォトダイオードより信号電荷を垂直転送部に読み出し、前記読み出された信号電荷を前記第１の電圧より低い第２の電圧と前記第２の電圧より低い第３の電圧を印加することにより前記水平転送部に向かって転送する固体撮像装置において、
　前記固体撮像装置内において前記第１、第２、第３の電圧より構成される３値パルスから前記第２、第３の電圧より構成される２値パルスを生成する２値パルス生成回路を有し、
　前記３値パルスと前記２値パルス生成回路で生成された２値パルスとを３値／２値切り替え制御信号により切り替える
　ことを特徴とする固体撮像装置。 Two-dimensionally arranged photodiodes, a vertical transfer unit that transfers signal charges photoelectrically converted by the photodiodes in a vertical direction, and a horizontal transfer unit that transfers signal charges from the vertical transfer units in a horizontal direction Have
By applying a first voltage, a signal charge is read from the photodiode to a vertical transfer unit, and the read signal charge is a second voltage lower than the first voltage and a second voltage lower than the second voltage. In the solid-state imaging device that transfers toward the horizontal transfer unit by applying a voltage of 3,
In the solid-state imaging device, there is a binary pulse generation circuit that generates a binary pulse composed of the second and third voltages from a ternary pulse composed of the first, second, and third voltages. And
A solid-state imaging device, wherein the ternary pulse and the binary pulse generated by the binary pulse generation circuit are switched by a ternary / binary switching control signal. 　前記請求項１記載の固体撮像装置において、
　前記２値パルス生成回路は、トランジスタからなる
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
The binary pulse generation circuit includes a transistor. A solid-state imaging device. 　前記請求項１記載の固体撮像装置において、
　前記２値パルス生成回路は、トランジスタ及びダイオードからなる
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
The binary pulse generation circuit includes a transistor and a diode. 　前記請求項１記載の固体撮像装置において、
　前記２値パルス生成回路を制御する前記３値／２値切り替え制御信号は、ＨｉｇｈレベルとＬｏｗレベルとの２値パルスからなる
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
The solid-state imaging device, wherein the ternary / binary switching control signal for controlling the binary pulse generation circuit includes binary pulses of a high level and a low level. 　前記請求項１記載の固体撮像装置において、
　１画面分の信号電荷をｎ回（ｎは２以上の整数）に分けて前記垂直転送部に読み出すｎ：１インターレース読み出しにおいて、
　読み出し及び垂直転送を制御する駆動パルスの数をｎ／２にする
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
In n: 1 interlace reading, the signal charge for one screen is divided into n times (n is an integer of 2 or more) and read to the vertical transfer unit.
A solid-state imaging device characterized in that the number of drive pulses for controlling readout and vertical transfer is n / 2. 　前記請求項１記載の固体撮像装置において、
　前記フォトダイオードに溜まった信号電荷を特定の行については垂直転送部に読み出さない間引き読み出しにおいて、
　同一位相電極に繋がる垂直方向の連続画素に同時に前記第１の電圧が印加されないように、前記２値パルス生成回路を間引こうとする行に挿入し、
　前記挿入された２値パルス生成回路を前記３値／２値切り替え制御信号により制御する
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
In the thinning readout where the signal charge accumulated in the photodiode is not read out to the vertical transfer unit for a specific row,
Inserting the binary pulse generation circuit in a row to be thinned out so that the first voltage is not simultaneously applied to consecutive vertical pixels connected to the same phase electrode,
The solid-state imaging device, wherein the inserted binary pulse generation circuit is controlled by the ternary / binary switching control signal. 　前記請求項１記載の固体撮像装置において、
　画像のアスペクト比が１６：９になるように１画面の中央部分の行から信号電荷を垂直転送部に読み出す動画撮影モードにおいて、
　読み出さない周辺の行に前記第１の電圧が印加されないように、前記２値パルス生成回路を読み出さない行に挿入し、
　前記挿入された２値パルス生成回路を前記３値／２値切り替え制御信号により制御する
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
In the moving image shooting mode in which the signal charge is read from the row at the center of one screen to the vertical transfer unit so that the aspect ratio of the image is 16: 9,
Inserting the binary pulse generation circuit in a row not to be read so that the first voltage is not applied to peripheral rows not to be read,
The solid-state imaging device, wherein the inserted binary pulse generation circuit is controlled by the ternary / binary switching control signal. 　前記請求項１記載の固体撮像装置において、
　前記２値パルス生成回路を制御する前記３値／２値切り替え制御信号は、
　水平転送を制御する駆動パルスである
　ことを特徴とする固体撮像装置。 The solid-state imaging device according to claim 1,
The ternary / binary switching control signal for controlling the binary pulse generation circuit is:
A solid-state imaging device characterized by being a drive pulse for controlling horizontal transfer. 　前記請求項１～８の何れか１項に記載の固体撮像装置を備えた
　ことを特徴とするカメラ。 A camera comprising the solid-state imaging device according to any one of claims 1 to 8.
PCT/JP2011/000521 2010-04-15 2011-01-31 Solid-state image capture device and camera Ceased WO2011129039A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064753A (en) * 2000-08-16 2002-02-28 Fuji Film Microdevices Co Ltd Drive circuit for ccd charge transfer
JP2005039561A (en) * 2003-07-15 2005-02-10 Sharp Corp Solid-state imaging device and driving method thereof
JP2009130907A (en) * 2007-11-28 2009-06-11 Panasonic Corp Solid-state imaging device and driving method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064753A (en) * 2000-08-16 2002-02-28 Fuji Film Microdevices Co Ltd Drive circuit for ccd charge transfer
JP2005039561A (en) * 2003-07-15 2005-02-10 Sharp Corp Solid-state imaging device and driving method thereof
JP2009130907A (en) * 2007-11-28 2009-06-11 Panasonic Corp Solid-state imaging device and driving method thereof

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