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WO2011089178A3 - Dispositif intégré de mémoire du type dram - Google Patents

Dispositif intégré de mémoire du type dram Download PDF

Info

Publication number
WO2011089178A3
WO2011089178A3 PCT/EP2011/050739 EP2011050739W WO2011089178A3 WO 2011089178 A3 WO2011089178 A3 WO 2011089178A3 EP 2011050739 W EP2011050739 W EP 2011050739W WO 2011089178 A3 WO2011089178 A3 WO 2011089178A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
memory device
dram memory
capacitor
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2011/050739
Other languages
English (en)
Other versions
WO2011089178A2 (fr
Inventor
Sébastien Cremer
Frédéric LALANNE
Marc Vernet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to US13/522,862 priority Critical patent/US8952436B2/en
Publication of WO2011089178A2 publication Critical patent/WO2011089178A2/fr
Publication of WO2011089178A3 publication Critical patent/WO2011089178A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

Le circuit intégré comprend un dispositif de mémoire du type DRAM (DM) comportant au moins un point -mémoire (CEL) incluant un transistor (TR) possédant une première électrode (E1), une deuxième électrode (E2) et une électrode de commande (EC), et un condensateur (CDS) couplé à ladite première électrode, et au moins une première ligne électriquement conductrice (BLT, BLC) couplée à la deuxième électrode et au moins une deuxième ligne électriquement conductrice (WL) couplée à l' électrode de commande, lesdites lignes électriquement conductrices (BLT, BLC, WL) étant disposées entre le transistor (TR) et le condensateur (CDS). Le condensateur pent être réalisé au-dessus du cinquième niveau de métal.
PCT/EP2011/050739 2010-01-21 2011-01-20 Dispositif intégré de mémoire du type dram Ceased WO2011089178A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/522,862 US8952436B2 (en) 2010-01-21 2011-01-20 Integrated DRAM memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1050391A FR2955419B1 (fr) 2010-01-21 2010-01-21 Dispositif integre de memoire du type dram
FR1050391 2010-01-21

Publications (2)

Publication Number Publication Date
WO2011089178A2 WO2011089178A2 (fr) 2011-07-28
WO2011089178A3 true WO2011089178A3 (fr) 2011-09-29

Family

ID=42562489

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2011/050739 Ceased WO2011089178A2 (fr) 2010-01-21 2011-01-20 Dispositif intégré de mémoire du type dram

Country Status (3)

Country Link
US (1) US8952436B2 (fr)
FR (1) FR2955419B1 (fr)
WO (1) WO2011089178A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8779849B2 (en) * 2012-01-27 2014-07-15 Micron Technology, Inc. Apparatuses and methods for providing capacitance in a multi-chip module
US9213386B2 (en) 2012-10-22 2015-12-15 Micron Technology, Inc. Apparatuses and methods and for providing power responsive to a power loss
CN111816654A (zh) * 2014-06-27 2020-10-23 英特尔公司 去耦电容器和布置
CN110416190A (zh) * 2019-07-08 2019-11-05 南通沃特光电科技有限公司 一种半导体叠层封装结构
CN110459483A (zh) * 2019-07-10 2019-11-15 南通沃特光电科技有限公司 一种电容组件的制造方法和半导体叠层封装方法
US20220199760A1 (en) * 2020-12-21 2022-06-23 Intel Corporation Integrated circuit device having backend double-walled capacitors
US12446208B2 (en) * 2021-06-25 2025-10-14 Intel Corporation Multilevel wordline assembly for embedded DRAM
US12310001B2 (en) 2021-06-25 2025-05-20 Intel Corporation Decoupling capacitors and methods of fabrication
CN115295549A (zh) * 2022-07-29 2022-11-04 芯盟科技有限公司 半导体结构及其形成方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2274741A (en) * 1993-01-27 1994-08-03 Samsung Electronics Co Ltd Semiconductor device comprising ferroelectric capacitor
US20010028588A1 (en) * 1996-11-19 2001-10-11 Matsushita Electronics Corporation Semiconductor memory
CA2379921A1 (fr) * 2001-03-30 2002-09-30 Atmos Corporation Montage de connexion de canaux mots torsades
US20020192901A1 (en) * 1995-11-20 2002-12-19 Shinichiro Kimura Semiconductor memory device and manufacturing method thereof
US20040029298A1 (en) * 1999-07-05 2004-02-12 Stmicroelectronics S.R.L. Ferroelectric memory cell and corresponding manufacturing method
US20040190350A1 (en) * 2003-03-31 2004-09-30 Osamu Wada Semiconductor memory device
US20040232497A1 (en) * 2001-12-14 2004-11-25 Satoru Akiyama Semiconductor device and method for manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714779A (en) * 1992-06-30 1998-02-03 Siemens Aktiengesellschaft Semiconductor memory device having a transistor, a bit line, a word line and a stacked capacitor
JP3241106B2 (ja) * 1992-07-17 2001-12-25 株式会社東芝 ダイナミック型半導体記憶装置及びその製造方法
JP3853406B2 (ja) * 1995-10-27 2006-12-06 エルピーダメモリ株式会社 半導体集積回路装置及び当該装置の製造方法
SG54456A1 (en) * 1996-01-12 1998-11-16 Hitachi Ltd Semconductor integrated circuit device and method for manufacturing the same
JP2002261161A (ja) * 2001-03-05 2002-09-13 Hitachi Ltd 半導体装置の製造方法
JP3983996B2 (ja) * 2001-04-23 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置
US7642572B2 (en) * 2007-04-13 2010-01-05 Qimonda Ag Integrated circuit having a memory cell array and method of forming an integrated circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2274741A (en) * 1993-01-27 1994-08-03 Samsung Electronics Co Ltd Semiconductor device comprising ferroelectric capacitor
US20020192901A1 (en) * 1995-11-20 2002-12-19 Shinichiro Kimura Semiconductor memory device and manufacturing method thereof
US20010028588A1 (en) * 1996-11-19 2001-10-11 Matsushita Electronics Corporation Semiconductor memory
US20040029298A1 (en) * 1999-07-05 2004-02-12 Stmicroelectronics S.R.L. Ferroelectric memory cell and corresponding manufacturing method
CA2379921A1 (fr) * 2001-03-30 2002-09-30 Atmos Corporation Montage de connexion de canaux mots torsades
US20040232497A1 (en) * 2001-12-14 2004-11-25 Satoru Akiyama Semiconductor device and method for manufacturing the same
US20040190350A1 (en) * 2003-03-31 2004-09-30 Osamu Wada Semiconductor memory device

Also Published As

Publication number Publication date
FR2955419A1 (fr) 2011-07-22
WO2011089178A2 (fr) 2011-07-28
FR2955419B1 (fr) 2012-07-13
US20130039113A1 (en) 2013-02-14
US8952436B2 (en) 2015-02-10

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