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WO2009110875A1 - Charge commutable pour initialiser une tension de sortie d'une alimentation électrique - Google Patents

Charge commutable pour initialiser une tension de sortie d'une alimentation électrique Download PDF

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Publication number
WO2009110875A1
WO2009110875A1 PCT/US2008/013578 US2008013578W WO2009110875A1 WO 2009110875 A1 WO2009110875 A1 WO 2009110875A1 US 2008013578 W US2008013578 W US 2008013578W WO 2009110875 A1 WO2009110875 A1 WO 2009110875A1
Authority
WO
WIPO (PCT)
Prior art keywords
supply voltage
resistor
voltage
electronic circuit
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/013578
Other languages
English (en)
Inventor
William Vincent Fitzgerald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Priority to CN2008801277372A priority Critical patent/CN102007763A/zh
Priority to US12/735,697 priority patent/US8564338B2/en
Priority to EP08873094A priority patent/EP2248340A1/fr
Priority to JP2010549621A priority patent/JP2011514098A/ja
Publication of WO2009110875A1 publication Critical patent/WO2009110875A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches

Definitions

  • the present invention relates to a power supply control arrangement for energizing an initialization arrangement.
  • a typical power supply in a television system such as, for example, a set-top box includes a pre-regulator that produces an output supply voltage in a filter capacitor.
  • the output supply voltage energizes an electronic circuit of the set-top box.
  • the user For recovering from an invalid operational mode that might occur in the electronic circuit producing, for example, an objectionable picture "freeze", the user might wish to re-initialize or reset the electronic circuit.
  • Proper initialization or reset operation might require the output supply voltage not to exceed, for example, 0.2 volts, during at least a portion of the reset operation. This is so in order to avoid any latch-up condition in stages of the electronic circuit.
  • the reset pulse in addition to performing the reset operation, also disables the pre- regulator for stopping the generation of the output supply voltage during the reset operation.
  • the output supply voltage is coupled to supply input terminals of post regulators such that the electronic circuit is energized directly from the post regulator.
  • Each of the post-regulators includes, typically, an under-voltage lock-out feature.
  • the output supply voltage of the post regulator quickly drops to a threshold level, typically 6 or 7 volts, established by the under-voltage lock-out feature.
  • the post-regulator will reduce the loading of the filter capacitor after reaching the threshold level. Therefore, following the post-regulator output voltage quick drop to the threshold level, the output supply voltage would not be able to continue dropping at a fast rate.
  • completion of the proper initialization or reset operation, and hence the subsequent normal operation would have to be, disadvantageously, excessively extended or delayed.
  • a video apparatus embodying an inventive feature, includes a power supply for replenishing a charge in a filter capacitor of the power supply to develop an output supply voltage that energizes an electronic circuit of the video apparatus, during normal operation.
  • a first switch generates a switched, control signal that is coupled to an electronic circuit of the video apparatus to perform a reset operation in the electronic circuit when the reset operation is required.
  • the control signal is also applied to the power supply for preventing the replenishment of the charge in the filter capacitor, when the control signal occurs.
  • the apparatus includes a resistor and a second switch for selectively applying the resistor to the filter capacitor, in response to the switched control signal, to produce a switched, discharge current in the capacitor.
  • the resistor has a resistance sufficiently low to reduce the output supply voltage to less than 5% of a normal operation voltage level of the output supply voltage, at an end of a two-second interval that follows the generation of the switched, control signal. With a 10 times larger resistance, the output supply voltage would have been larger than the 5% level at the end of the two-second interval.
  • FIGURES I A and I B illustrate an arrangement, in accordance with an embodiment of the present invention
  • FIGURE 2A, 2B and 2C illustrate waveforms useful for explaining the operation of the arrangement of FIGURES I A and 1 B.
  • FIGURE IA illustrates a schematic, partially in a block diagram form, of a power supply 100 and a utilization or electronic circuit 10 for example a "set-top box". Electronic circuit 10 is energized by power supply 100.
  • Power supply 100 includes a conventional pre-regulator 15 having a controller 22.
  • Pre-regulator 15 is referenced to a common ground conductor HG referred to as "hot" ground.
  • Controller 22 produces at a gate terminal 31 of a power transistor 30 a gate drive signal 31a that controls switching operation of chopper power transistor 30.
  • Power transistor 30 is controlled in, for example, pulse-width-modulated manner.
  • the circuit configuration and operation of controller 22 is conventional. Therefore, some circuit details have been omitted for simplification purposes as unnecessary for explaining the operation and structure of power supply 100.
  • a drain terminal 32 of transistor 30 is coupled to an end terminal of a primary winding 33 of a flyback transformer 34. Terminal 32 is also coupled to a flyback capacitor
  • a second end terminal 35 of winding 33 that is remote from terminal 32 is coupled to a bridge rectifier 36 that rectifies an alternating current (AC) mains supply voltage 17 to produce an unregulated, filtered direct current (DC) voltage 41 at terminal 35 of winding 33 in a conventional manner.
  • AC alternating current
  • DC direct current
  • Diode 40 has an anode that is coupled to a common or ground terminal G, referred to as "cold" ground. Ground G and ground HG are conductively isolated from each other. Diode 40 has a cathode that is coupled to an end terminal 39a of winding 39.
  • DC output supply voltage VO is produced at a terminal 16a of a filter capacitor 23 by periodically replenishing a charge in capacitor 23.
  • DC output supply voltage VO for example, at a level of -M 2 V, is developed at an input 21b of a post- regulator 21 for producing a DC supply voltage, not shown, at an output terminal 21a of post-regulator 21 that energizes electronic circuit 10.
  • Voltage VO is coupled via a resistor 42 to a cathode of a reference, Zener diode 43.
  • An anode of Zener diode 43 is coupled to an anode of a light emitting diode 44 of an opto-coupler 45.
  • a transistor 46 of opto-coupler 45 is coupled to a charge storage capacitor 47 via a junction terminal 48 for providing a negative feedback signal to controller 22, in a conventional manner.
  • Zener diode 43 and diode 44 a current i54 flows in diode 44 to produce a collector current in transistor 46, not shown, by opto-coupling operation. Consequently, capacitor 47 is discharged in a manner to reduce a control voltage at terminal 48 in a negative feedback manner. Consequently, the duty cycle of transistor 30 is reduced. Thereby, voltage VO is reduced and regulation is provided.
  • FIGURE IB illustrates an arrangement 200, embodying an inventive feature, for performing a reset operation in electronic circuit 10 of FIGURE 1 A. Similar symbols and numerals in FIGURE IA and I B indicate similar items or functions.
  • a user controlled pulse generator 56 of FIGURE I B includes a latch 50.
  • Latch 50 includes a PNP transistor 104 having an emitter that is coupled via an emitter resistor
  • Supply voltage +12VO-SB is produced from voltage VO by storing a charge in a charge storage capacitor 53 of FIGURE 1 A via a diode 52.
  • Transistor 104 of FIGURE IB is cross-coupled to an NPN transistor 105 such that the base of transistor 104 is coupled to the collector of transistor 105 and the base of transistor 105 is coupled to the collector of transistor 104.
  • Transistor 105 has an emitter that is coupled via an emitter resistorl75 to a ground terminal G.
  • a resistor 177 is coupled between the base and emitter terminals of transistor 104.
  • the user For recovering from an invalid operational mode that might occur in electronic circuit 10, the user might wish to re-initialize or reset electronic circuit 10. Therefore, the user can initiate the generation of a signal PS-RESET at zero volts relative to ground potential G by manually closing a switch 49.
  • signal PS-RESET Prior to closing switch 49, signal PS-RESET is at an inactive level of 4 volts that is determined by a voltage divider formed by a pair of resistors 55 and 179.
  • the closing of switch 49 produces a voltage drop transition in signal PS-RESET that is capacitively coupled via a series arrangement of a capacitor 182 and a resistor 102 to an input terminal 51 of latch 50. Consequently, a base current and a collector current are produced in transistor 104.
  • latch 50 is triggered to maintain both transistors 104 and 105 turned on.
  • an emitter voltage VPI is developed at the emitter of transistor 105 of latch 50 and across an emitter resistor 175.
  • Voltage VPl is coupled via a resistor 174 to a base electrode of a transistor switch 102.
  • the collector of transistor 102 is coupled to a base of transistor 155 via a resistor 163.
  • a cathode voltage V40 of diode 40 is coupled via a resistor 142 of FIGURE IB to an anode of a diode 145.
  • a cathode of diode 145 is coupled to a parallel arrangement of a filter capacitor 148 and a voltage divider formed by a resistor 152 coupled in series with a resistor 153 to form a peak rectifier arrangement.
  • the base of a comparator transistor 155 is coupled at a junction between resistors 152 and 153.
  • a threshold voltage of comparator transistor 155 is determined by a breakdown voltage of a Zener diode 187 that is coupled to the emitter of transistor 155.
  • Zener diode 187 is coupled to supply voltage + 12VO-SB via a resistor 186 that maintains Zener diode 187 conductive.
  • the collector terminal of transistor switch 168 is coupled via a pull-up resistor 169 to capacitor 23.
  • Voltage VPl is also coupled via series coupled arrangement of a resistor 161 , a resistor 144, diode 54 and diode 44 of opto-coupler 45.
  • a filter capacitor 173 is coupled between ground G and a junction terminal 161a, between resistors 161 and 144. Consequently, capacitor 47 that is coupled to feedback terminal 48 of FIGURE I A of controller 22 will be discharged.
  • the voltage drop in terminal 48 of controller 22, produced when voltage VPl is generated, will prevent transistor 30 from being turned on. Consequently, the charge in capacitor 23 will no longer be replenished, as long as voltage VPl is generated. The result is that pre-regulator 15 is disabled.
  • FIGURES 2A, 2B and 2C illustrate waveforms useful for explaining the operation of power supply 100 of FIGURES IA and arrangement 200 of FIGURE I B.
  • FIGURE I A, I B, 2A, 2B and 2C indicate similar items or functions.
  • FIGURE 2a illustrates the manner by which output supply voltage VO decreases as a function of time following a leading edge LE of signal EPF of FIGURE 2C, when the value selected for resistor 169 of FIGURE IB is 2200 Ohm.
  • FIGURE 2B illustrates the manner by which output supply voltage VO decreases as a function of time following leading edge LE of signal EPF of FIGURE 2C at a time t ⁇ , when the value selected for resistor 169 of FIGURE IB is 220 Ohm, in accordance with an inventive feature.
  • post regulator 21 heavily loads capacitor 23 so as to discharge capacitor 23 at a first rate. Therefore, output supply voltage VO quickly drops, as shown in each of FIGURES 2A and 2B in the vicinity of time t ⁇ .
  • dropping supply voltage VO reaches a threshold level of 6 volts, established by a conventional under-voltage lock-out feature, not shown, of post regulator
  • post regulator 21 forms a much lighter load with respect to capacitor 23. As a result, the discharge rate of capacitor 23 is reduced relative to the first rate.
  • Proper initialization or reset operation can require output supply voltage VO not to exceed, for example, 0.2 volts, during the reset operation. This can be required in order to avoid any latch-up condition in stages of electronic circuit 10. Slow discharge of capacitor 23 can have delay or extend significantly the completion of proper initialization or reset operation.
  • pulse generator 56 of FIGURE 1 B that produces user initiated pulse voltage VPl is energized by the charge previously stored in capacitor 53.
  • capacitor 53 is, typically, restricted to a value permitting no more than 3 seconds of energizing pulse generator 56.
  • the value of resistor 169 is selected to be sufficiently low such that filter capacitor 23 becomes heavily loaded.
  • FIGURE 2B shows that voltage VO is at 0.2V at time tl, at the end of the 2-second interval from leading edge LE of FIGURE 2C.
  • voltage VO at 0.2V does meet the voltage requirement for proper reset operation.
  • resistor 169 forms only a negligible load with respect to filter capacitor 23 in normal operation, when transistor switch 168 is non-conductive.
  • I A is at a normal operation level and signal EPF is at an inactive level.
  • peak rectified voltage V40 would no longer produce the base voltage of transistor 155 of FIGURE I B at the level that is sufficient to maintain transistor 155 non- conductive.
  • a time constant associated with discharging capacitor 148 is smaller than a period of AC voltage 17 of FIGURE I A that is approximately 20 millisecond. Therefore, soon after the amplitude of AC voltage 17 becomes smaller than the normal operation range, transistor 168 of FIGURE 1 B will turn on to generate signal EPF.
  • signal EPF provides, advantageously, an early power fail warning.
  • Early Power Fail signal EPF indicates an interruption or a power outage in AC mains supply voltage 17 of FIGURE IA long before output supply voltage VO drops outside the normal operation range of voltage VO.
  • Early Power Fail signal EPF can initiate a power down procedure in a microprocessor, not shown, of electronic circuit 10 in a well known manner.
  • transistor 168 of FIGURE I B provides both proper reset operation for user initiated reset operation and a shut-down operation of electronic circuit 10.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Television Receiver Circuits (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention porte sur un commutateur à transistor conducteur qui a un collecteur qui applique une impulsion de réinitialisation à un circuit électronique. Une résistance de polarisation à l'alimentation est couplée entre le collecteur du commutateur à transistor et une tension d'alimentation électrique développée dans un condensateur de filtre qui excite le circuit électronique. Une opération de réinitialisation correcte nécessite que la tension d'alimentation de sortie ne dépasse pas, par exemple, 0,2 volt, durant au moins une partie de l'opération de réinitialisation. L'utilisateur initie l'impulsion de réinitialisation qui désactive momentanément une alimentation électrique pour arrêter la génération de la tension d'alimentation de sortie lorsque l'opération de réinitialisation est effectuée. La valeur de la résistance est sélectionnée pour être suffisamment faible, de telle sorte que lorsque le commutateur à transistor est conducteur, la décharge du condensateur de filtre par l'intermédiaire de la résistance de polarisation à l'alimentation est accélérée pour achever la décharge du condensateur de filtre en pas plus de, par exemple, 2 secondes pour fournir un niveau maximal de la tension d'alimentation de sortie qui n’est pas supérieur à 5 % de son niveau de tension de fonctionnement normal.
PCT/US2008/013578 2008-03-03 2008-12-11 Charge commutable pour initialiser une tension de sortie d'une alimentation électrique Ceased WO2009110875A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008801277372A CN102007763A (zh) 2008-03-03 2008-12-11 用于初始化电源输出电压的可切换的负载
US12/735,697 US8564338B2 (en) 2008-03-03 2008-12-11 Switchable load for initializing an output voltage of a power supply
EP08873094A EP2248340A1 (fr) 2008-03-03 2008-12-11 Charge commutable pour initialiser une tension de sortie d'une alimentation électrique
JP2010549621A JP2011514098A (ja) 2008-03-03 2008-12-11 電源の出力電圧を初期化する切り替え可能な負荷

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6790208P 2008-03-03 2008-03-03
US61/067,902 2008-03-03

Publications (1)

Publication Number Publication Date
WO2009110875A1 true WO2009110875A1 (fr) 2009-09-11

Family

ID=40328417

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/013578 Ceased WO2009110875A1 (fr) 2008-03-03 2008-12-11 Charge commutable pour initialiser une tension de sortie d'une alimentation électrique

Country Status (6)

Country Link
US (1) US8564338B2 (fr)
EP (1) EP2248340A1 (fr)
JP (1) JP2011514098A (fr)
KR (1) KR20100127769A (fr)
CN (1) CN102007763A (fr)
WO (1) WO2009110875A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9819274B2 (en) 2014-11-20 2017-11-14 Microchip Technology Incorporated Start-up controller for a power converter
US10277130B2 (en) 2015-06-01 2019-04-30 Microchip Technolgoy Incorporated Primary-side start-up method and circuit arrangement for a series-parallel resonant power converter
US9912243B2 (en) 2015-06-01 2018-03-06 Microchip Technology Incorporated Reducing power in a power converter when in a standby mode
US9705408B2 (en) 2015-08-21 2017-07-11 Microchip Technology Incorporated Power converter with sleep/wake mode
CN109116960B (zh) * 2017-06-26 2020-08-07 纬创资通（中山）有限公司 电源放电控制装置、电路及其控制方法

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JPH08205391A (ja) * 1995-01-24 1996-08-09 Fuji Electric Co Ltd 計算機の給電装置
US5999429A (en) * 1997-12-19 1999-12-07 Dell Usa, L.P. Bulk filter capacitor discharge in a switching power supply
JP2002023863A (ja) * 2000-07-03 2002-01-25 Techno Collage:Kk 電源電圧制御回路
JP2002165155A (ja) * 2000-11-28 2002-06-07 Toshiba Corp 電源電圧制御装置
US20070274104A1 (en) * 2004-08-18 2007-11-29 Sanken Electric Co., Ltd. Switching Power Supply Apparatus

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Publication number Priority date Publication date Assignee Title
JPH08205391A (ja) * 1995-01-24 1996-08-09 Fuji Electric Co Ltd 計算機の給電装置
US5999429A (en) * 1997-12-19 1999-12-07 Dell Usa, L.P. Bulk filter capacitor discharge in a switching power supply
JP2002023863A (ja) * 2000-07-03 2002-01-25 Techno Collage:Kk 電源電圧制御回路
JP2002165155A (ja) * 2000-11-28 2002-06-07 Toshiba Corp 電源電圧制御装置
US20070274104A1 (en) * 2004-08-18 2007-11-29 Sanken Electric Co., Ltd. Switching Power Supply Apparatus

Also Published As

Publication number Publication date
US8564338B2 (en) 2013-10-22
CN102007763A (zh) 2011-04-06
KR20100127769A (ko) 2010-12-06
JP2011514098A (ja) 2011-04-28
EP2248340A1 (fr) 2010-11-10
US20100308875A1 (en) 2010-12-09

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