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WO2009028235A1 - 回路基板及び表示装置 - Google Patents

回路基板及び表示装置 Download PDF

Info

Publication number
WO2009028235A1
WO2009028235A1 PCT/JP2008/058121 JP2008058121W WO2009028235A1 WO 2009028235 A1 WO2009028235 A1 WO 2009028235A1 JP 2008058121 W JP2008058121 W JP 2008058121W WO 2009028235 A1 WO2009028235 A1 WO 2009028235A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit substrate
display device
thin film
film transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/058121
Other languages
English (en)
French (fr)
Inventor
Hiroyuki Moriwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to US12/595,366 priority Critical patent/US8304781B2/en
Priority to CN200880010292XA priority patent/CN101647121B/zh
Publication of WO2009028235A1 publication Critical patent/WO2009028235A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本発明は、モノリシック回路に、特性バラツキを抑制した高性能薄膜トランジスタを有する回路基板及び上記回路基板を備える表示装置を提供する。本発明の回路基板は、薄膜トランジスタを有するモノリシック回路を基板上に備える回路基板であって、上記薄膜トランジスタは、半導体層、ゲート絶縁膜及びゲート電極がこの順に積層され、上記ゲート電極は、半導体層との重なり面積が４０μｍ２以下であり、膜厚が３００ｎｍ以下である回路基板である。
PCT/JP2008/058121 2007-08-24 2008-04-25 回路基板及び表示装置 Ceased WO2009028235A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/595,366 US8304781B2 (en) 2007-08-24 2008-04-25 Circuit board provided with monolithic circuit having thin film transistor on substrate, and display device having the circuit board
CN200880010292XA CN101647121B (zh) 2007-08-24 2008-04-25 电路基板和显示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007218769 2007-08-24
JP2007-218769 2007-08-24

Publications (1)

Publication Number Publication Date
WO2009028235A1 true WO2009028235A1 (ja) 2009-03-05

Family

ID=40386966

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/058121 Ceased WO2009028235A1 (ja) 2007-08-24 2008-04-25 回路基板及び表示装置

Country Status (3)

Country Link
US (1) US8304781B2 (ja)
CN (1) CN101647121B (ja)
WO (1) WO2009028235A1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825488B2 (en) * 2000-01-26 2004-11-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2011027467A1 (ja) * 2009-09-04 2011-03-10 株式会社 東芝 薄膜トランジスタ及びその製造方法
US9324739B1 (en) * 2014-11-03 2016-04-26 Ishiang Shih Thin film transistors with metal oxynitride active channels for electronic displays
CN104658891B (zh) * 2015-03-03 2019-03-15 京东方科技集团股份有限公司 低温多晶硅薄膜的制备方法、薄膜晶体管及显示装置
JP2019101145A (ja) * 2017-11-30 2019-06-24 シャープ株式会社 電子デバイス
US11362215B2 (en) * 2018-03-30 2022-06-14 Intel Corporation Top-gate doped thin film transistor
US11257956B2 (en) 2018-03-30 2022-02-22 Intel Corporation Thin film transistor with selectively doped oxide thin film
JP7352826B2 (ja) * 2019-10-21 2023-09-29 セイコーエプソン株式会社 電気光学装置および電子機器
CN120475747A (zh) * 2024-02-07 2025-08-12 华为技术有限公司 芯片及其制备方法、电子设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144300A (ja) * 1999-08-31 2001-05-25 Fujitsu Ltd 半導体装置及びその製造方法並びにシリコン薄膜の形成方法
JP2002170956A (ja) * 2000-11-30 2002-06-14 Fujitsu Ltd 薄膜トランジスタ及びその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0430475A (ja) 1990-05-25 1992-02-03 Mitsubishi Electric Corp 薄膜トランジスタアレイ基板
US6190933B1 (en) * 1993-06-30 2001-02-20 The United States Of America As Represented By The Secretary Of The Navy Ultra-high resolution liquid crystal display on silicon-on-sapphire
CN1154490A (zh) * 1995-12-08 1997-07-16 Lg半导体株式会社 薄膜晶体管的液晶显示装置及其制造方法
US6680223B1 (en) * 1997-09-23 2004-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6369410B1 (en) * 1997-12-15 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US6255148B1 (en) * 1998-07-13 2001-07-03 Fujitsu Limited Polycrystal thin film forming method and forming system
US6582996B1 (en) * 1998-07-13 2003-06-24 Fujitsu Limited Semiconductor thin film forming method
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7719043B2 (en) * 2004-07-12 2010-05-18 Nec Corporation Semiconductor device with fin-type field effect transistor and manufacturing method thereof.
US7317434B2 (en) * 2004-12-03 2008-01-08 Dupont Displays, Inc. Circuits including switches for electronic devices and methods of using the electronic devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144300A (ja) * 1999-08-31 2001-05-25 Fujitsu Ltd 半導体装置及びその製造方法並びにシリコン薄膜の形成方法
JP2002170956A (ja) * 2000-11-30 2002-06-14 Fujitsu Ltd 薄膜トランジスタ及びその製造方法

Also Published As

Publication number Publication date
US20100051959A1 (en) 2010-03-04
CN101647121A (zh) 2010-02-10
US8304781B2 (en) 2012-11-06
CN101647121B (zh) 2011-05-25

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