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WO2009005699A1 - Cellule de mémoire utilisant un élément de commutation de résistance réversible à croissance sélective et procédés de formation correspondants - Google Patents

Cellule de mémoire utilisant un élément de commutation de résistance réversible à croissance sélective et procédés de formation correspondants Download PDF

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Publication number
WO2009005699A1
WO2009005699A1 PCT/US2008/007985 US2008007985W WO2009005699A1 WO 2009005699 A1 WO2009005699 A1 WO 2009005699A1 US 2008007985 W US2008007985 W US 2008007985W WO 2009005699 A1 WO2009005699 A1 WO 2009005699A1
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WIPO (PCT)
Prior art keywords
forming
switching element
reversible resistance
memory cell
tio
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PCT/US2008/007985
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English (en)
Inventor
April Schricker
S. Brad Herner
Mark Clark
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SanDisk 3D LLC
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SanDisk 3D LLC
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Priority claimed from US11/772,082 external-priority patent/US7824956B2/en
Priority claimed from US11/772,088 external-priority patent/US7902537B2/en
Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
Priority to JP2010514823A priority Critical patent/JP2010532568A/ja
Priority to CN2008800226674A priority patent/CN101720508B/zh
Priority to EP08768806A priority patent/EP2162917A1/fr
Publication of WO2009005699A1 publication Critical patent/WO2009005699A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/206—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of combinations of capacitors and resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • Non-volatile memories formed from reversible resistance-switching elements are known.
  • U.S. Patent Application Serial No. 11/125,939 filed May 9, 2005 and titled “REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL" (hereinafter "the ⁇ 939
  • a rewriteable non-volatile memory cell that includes a diode coupled in series with a reversible resistivity-switching material such as a metal oxide or metal nitride.
  • FIG. 2C is a simplified perspective view of a portion of a first exemplary three dimensional memory array provided in accordance with the present invention.
  • the titanium oxide layer 212 may include, for example, TiO, TiO 2 , TiO x , TiO x N y or the like. While the reversible resistance- switching element 202 is shown as being positioned below the diode 204 in FIG. 2A, it will be understood that in alternative embodiments, the reversible resistance-switching element 202 may be positioned above the diode 204. Additional details for the reversible resistance-switching element 202 are described below with reference to FIG. 3.
  • the diode 204 may include any suitable diode such as a vertical polycrystalline p-n or p-i-n diode, whether upward pointing with an n-region above a p-region of the diode or downward pointing with a p-region above an n-region of the diode. Exemplary embodiments of the diode 204 are described below with reference to FIG. 3.
  • reversible resistance-switching element 202 may be used to form the reversible resistance-switching element 202.
  • materials such as Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V, VN, etc., may be similarly deposited over (and/or patterned and etched with) the first conductor 206 and then oxidized to form the layer 212, which includes the reversible resistance-switching element 202.
  • FIG. 2B is a simplified perspective view of a portion of a first memory level 214 formed from a plurality of the memory cells 200 of FIG. 2A.
  • the memory array 214 is a "cross-point" array including a plurality of bit lines (second conductors 208) and word lines (first conductors 206) to which multiple memory cells are coupled (as shown) .
  • Other memory array configurations may be used, as may multiple levels of memory.
  • FIG. 2C is a simplified perspective view of a portion of a monolithic three dimensional array 216 that includes a first memory level 218 positioned below a second memory level 220.
  • each memory level 218, 220 includes a plurality of memory cells 200 in a cross-point array. It will be understood that one or more additional layers (e.g., an interlevel dielectric) may be present between the first and second memory levels 218 and 220, but are not shown in FIG. 2C for simplicity. Other memory array configurations may be used, as may additional levels of memory. In the embodiment of FIG. 2C, all diodes may be present.
  • the memory levels may be formed, as described, for example, in U.S. Patent No. 6,952,030, "High-density three-dimensional memory cell” which is hereby incorporated by reference herein in its entirety for all purposes.
  • the upper conductors of a first memory level may be used as the lower conductors of a second memory level that is positioned above the first memory level as shown in FIG. 2D.
  • the diodes on adjacent memory levels preferably point in opposite directions as described in U.S.
  • the diodes of the first memory level 218 may be upward pointing diodes as indicated by arrow Ai (e.g., with p regions at the bottom of the diodes), while the diodes of the second memory level 220 may be downward pointing diodes as indicated by arrow A 2 (e.g., with n regions at the bottom of the diodes), or vice versa.
  • a monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates.
  • the layers forming one memory level are deposited or grown directly over the layers of an existing level or levels.
  • stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Patent No. 5,915,167, "Three dimensional structure memory.”
  • the substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
  • FIG. 3 is a cross-sectional view of an exemplary embodiment of the memory cell 200 of FIG. 2A.
  • the memory cell 200 includes the reversible resistance-switching element 202 (e.g., a portion of a layer of reversible resistivity-switching material, namely titanium oxide layer 212 in this embodiment) , the diode 204 and the first and second conductors 206, 208.
  • the reversible resistance-switching element 202 may be a portion of the titanium oxide layer 212 that vertically overlies and/or overlaps with the diode 204.
  • the reversible resistance- switching element 202 is formed by a selective growth process.
  • the titanium oxide layer 212 may be selectively formed on the titanium-containing layer 210 by oxidizing the titanium-containing layer 210. In this manner, only the titanium-containing layer 210, and not the titanium oxide layer 212, is etched, such as during the pattern and etch step(s) for the first conductor 206.
  • the titanium-containing layer 210 may be oxidized by any suitable process. For instance, the titanium-containing layer 210 may be oxidized using thermal oxidation in oxygen, ozone, a combination of the same or another oxygen source (e.g., using rapid thermal oxidation).
  • the titanium-containing layer 210 may be oxidized using oxygen diffusion in a CVD chamber with an ozone or other oxygen source, using gaseous or liquid ozone cleaning, or using any other suitable oxidation process to form titanium oxide.
  • other reversible resistance-switching materials may be similarly formed by oxidizing Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V, VN, etc.
  • rapid thermal oxidation may be performed at a temperature of about 300 0 C to about 800 0 C for about one second to about 5 minutes at an oxygen flow rate of about 2 seem to about 40 seem, depending on the desired oxide thickness and/or other properties.
  • Other oxidizing species, temperatures, times and/or flow rates may be used.
  • Oxidation by ozone diffusion in a CVD chamber may be performed at a temperature of about 300 0 C to about 800°C, more preferably at a temperature of about 350 0 C to about 450 0 C, for about 2 minutes to about 4 hours, more preferably for about 15 to 25 minutes, at a suitable ozone flow rate, such as between about 10 and 60 seem, depending on the desired oxide thickness and/or other properties.
  • Other oxidizing species, temperatures, times and/or flow rates may be used.
  • any desired thickness of titanium oxide may be formed.
  • the diode 204 may be a vertical p-n or p-i-n diode, which may either point upward or downward.
  • adjacent memory levels preferably have diodes that point in opposite directions such as downward-pointing p-i-n diodes for a first memory level and upward-pointing p- i-n diodes for an adjacent, second memory level (or vice versa) .
  • a suicide layer 310 may be formed on the diode 204 to place the deposited silicon in a low resistivity state, as fabricated.
  • a low resistivity state allows for easier programming of the memory cell 200 as a large voltage is not required to switch the deposited silicon to a low resistivity state.
  • a silicide-forming metal layer 312 such as titanium or cobalt, may be deposited on the p+ polysilicon region 306.
  • FIGS. 4A-D illustrate cross sectional views of a portion of a substrate 400 during fabrication of a first memory level in accordance with the present invention.
  • the single memory level includes a plurality of memory cells that each include a reversible resistance-switching element formed using a selective growth process. Additional memory levels may be fabricated above the first memory level (as described previously with reference to FIGS. 2C-2D) .
  • the substrate 400 is shown as having already undergone several processing steps.
  • the substrate 400 may be any suitable substrate such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (SOI) or other substrate with or without additional circuitry.
  • the substrate 400 may include one or more n-well or p-well regions (not shown) .
  • a silicon nitride or similar protective layer may be formed over active regions (not shown) of the substrate 400 prior to isolation region formation (e.g., to protect the active regions).
  • a localized oxidation of silicon (LOCOS) process or any other suitable process may be employed to define the isolation layer 402.
  • the conductive layer 406 may include any suitable conductive material such as tungsten or another appropriate metal, heavily doped semiconductor material, a conductive suicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., chemical vapor deposition, physical vapor deposition, etc.). In at least one embodiment, the conductive layer 406 may comprise about 200 to about 2500 angstroms of tungsten. Other conductive layer materials and/or thicknesses may be used.
  • a titanium-containing layer 407 such as titanium nitride, is formed over the conductive layer 406 (e.g., using physical vapor deposition or another method) .
  • the titanium-containing layer 407 includes about 20 to about 1200 angstroms of titanium nitride.
  • Other titanium- containing layer materials such as titanium, a titanium alloy, TiSi 2 , TiW, etc., and/or thicknesses may be used.
  • the adhesion layer 404, the conductive layer 406 and the titanium-containing layer 407 are patterned and etched.
  • the adhesion layer 404, the conductive layer 406 and the titanium-containing layer 407 may be patterned and etched using conventional lithography techniques, with a soft or hard mask, and wet or dry etch processing.
  • the adhesion layer 404, the conductive layer 406 and the titanium-containing layer 407 are patterned and etched so as to form substantially parallel, substantially co-planar conductors 408 (as shown in FIG. 4A) .
  • Exemplary widths for the conductors 408 and/or spacings between the conductors 408 range from about 200 to about 2500 angstroms, although other conductor widths and/or spacings may be used.
  • a dielectric layer 410 is deposited over the substrate 400 so as to fill the voids between the conductors 408.
  • a dielectric layer 410 is deposited over the substrate 400 so as to fill the voids between the conductors 408.
  • approximately 3000-7000 angstroms of silicon dioxide may be deposited on the substrate 400 and planarized using chemical mechanical polishing or an etchback process to form a planar surface 412.
  • the planar surface 412 includes exposed, discrete regions 407a-f of titanium-containing layer material 407 separated by dielectric material 410, as shown.
  • the discrete titanium-containing layer regions 407a-f may be used to selectively form a titanium oxide reversible resistance-switching element for each memory cell being formed above the substrate 400 (as described further below) .
  • dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric layer thicknesses may be used.
  • Exemplary low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.
  • the titanium-containing layer 407 may be replaced with a layer of the material to be oxidized, such as Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V, VN, etc.
  • a reversible resistance-switching element 413a-f is formed over each titanium-containing layer region 407a-f.
  • a titanium oxide layer may be selectively formed over each titanium-containing layer region 407a-f by oxidizing the titanium-containing layer regions 407a-f. Some or all of each titanium-containing layer region 407a-f may be consumed during oxidation to create reversible resistance-switching elements 413a-f.
  • any suitable method may be employed to oxidize the titanium-containing layer regions 407a-f such as rapid thermal oxidation in an oxygen environment such as O 2 , ozone, a combination of the same, or using any other suitable oxidizing species.
  • a titanium- containing layer region may be oxidized using oxygen diffusion in a CVD chamber with an ozone or other oxygen source, using gaseous or liquid ozone cleaning, or using any other suitable oxidation process to form titanium oxide.
  • the diode structures of each memory cell are formed.
  • An optional thin conductive layer (not shown) , such as about 10 to about 300 angstroms of titanium, nickel, etc., may be formed over the titanium oxide layer regions (e.g., for work function tuning).
  • a barrier layer 414 such as titanium nitride, tantalum nitride, tungsten nitride, etc., may also be formed over the titanium oxide layer regions prior to diode formation (e.g., to prevent and/or reduce migration of metal atoms into the polysilicon regions) .
  • the barrier layer 414 may be on top of, in addition to or in place of the thin conductive layer and may be about 20 to about 500 angstroms, and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalum nitride, tungsten nitride, combinations of one or more barrier layers, barrier layers in combination with other layers such as titanium/titanium nitride, tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or the like. Other barrier layer materials and/or thicknesses may be employed.
  • each diode may be a vertical p-n or p-i-n diode as previously described.
  • each diode is formed from a polycrystalline semiconductor material such as polysilicon, a polysilicon-germanium alloy, germanium or any other suitable material. For convenience, formation of a polysilicon, downward-pointing diode is described herein. It will be understood that other materials and/or diode configurations may be used.
  • n+ silicon layer 416 is deposited on the barrier layer 414.
  • the n+ silicon layer 416 is in an amorphous state as deposited.
  • the n+ silicon layer 416 is in a polycrystalline state as deposited.
  • Chemical vapor deposition or another suitable process may be employed to deposit the n+ silicon layer 416.
  • the n+ silicon layer 416 may be formed, for example, from about 100 to about 1000 angstroms, preferably about 100 angstroms, of phosphorus or arsenic doped silicon having a doping concentration of about 10 21 cm "3 .
  • n+ silicon layer 416 may be doped in situ, for example, by flowing a donor gas during deposition. Other doping methods may be used (e.g., implantation).
  • a lightly doped, intrinsic and/or unintentionally doped silicon layer 418 is formed over the n+ silicon layer 416.
  • the intrinsic silicon layer 418 is in an amorphous state as deposited. In other embodiments, the intrinsic silicon layer 418 is in a polycrystalline state as deposited. Chemical vapor deposition or another suitable deposition method may be employed to deposit the intrinsic silicon layer 418.
  • the intrinsic silicon layer 418 may be about 500 to about 4800 angstroms, preferably about 2500 angstroms, in thickness. Other intrinsic layer thicknesses may be used.
  • a thin (e.g., a few hundred angstroms or less) germanium and/or silicon-germanium alloy layer may be formed on the n+ silicon layer 416 prior to deposition of the intrinsic silicon layer 418 to prevent and/or reduce dopant migration from the n+ silicon layer 416 into the intrinsic silicon layer 418 (as described in the ⁇ 331 Application, previously incorporated) .
  • the n+ silicon layer 416, the intrinsic silicon layer 418, the barrier layer 414 and/or any conductive layer are patterned and etched so as to form silicon pillars 420 overlying the conductors 408 (as shown) .
  • Conventional lithography techniques, with a soft or hard mask, and wet or dry etch processing may be employed to form the silicon pillars 420.
  • a dielectric layer 422 is deposited to fill the voids between the silicon pillars 420.
  • a dielectric layer 422 is deposited to fill the voids between the silicon pillars 420.
  • approximately 200- 7000 angstroms of silicon dioxide may be deposited and planarized using chemical mechanical polishing or an etchback process to form a planar surface 424.
  • the planar surface 424 includes exposed top surfaces of the silicon pillars 420 separated by dielectric material 422, as shown.
  • dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric layer thicknesses may be used.
  • Exemplary low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.
  • a p+ silicon region 426 is formed within each silicon pillar 420, near the upper surface of the silicon pillars 420.
  • a blanket p+ implant may be employed to implant boron a predetermined depth within the silicon pillars 420.
  • Exemplary implantable molecular ions include BF 2 , BF 3 , B and the like.
  • an implant dose of about 1- 5xlO 15 ions/cm 2 may be employed.
  • Other implant species and/or doses may be used.
  • a diffusion process may be employed to dope the upper portion of the silicon pillars 420.
  • the p+ silicon regions 426 have a depth of about 100-700 angstroms, although other p+ silicon region sizes may be used. (Note that if the diodes to be formed are upward pointing p-n or p-i-n diodes, the upper portion of the silicon pillars 420 will be doped n-type) . Each silicon pillar 420 thereby includes a downward-pointing, p-i-n diode 428. With reference to FIG. 4D, after completion of the p-i- n diodes 428, a silicide-forming metal layer 430 is deposited over the substrate 400. Exemplary silicide- forming metals include sputter or otherwise deposited titanium or cobalt.
  • the silicide- forming metal layer 430 has a thickness of about 10 to about 200 angstroms, preferably about 20 to about 50 angstroms and more preferably about 20 angstroms. Other silicide-forming metal layer materials and/or thicknesses may be used. As will be described further below, annealing of the structure causes metal from the silicide-forming metal layer 430 and silicon from the p+ silicon regions 426 to react to form a suicide region 432 adjacent each p+ silicon region 426.
  • a second set of conductors 436 may be formed above the diodes 428 in a manner similar to the formation of the bottom set of conductors 408.
  • one or more barrier layers and/or adhesion layers 438 may be placed over the silicide-forming metal layer 430 prior to deposition of a conductive layer 440 used to form the upper, second set of conductors 436.
  • the conductive layer 440 may be formed from any suitable conductive material such as tungsten, another suitable metal, heavily doped semiconductor material, a conductive suicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., chemical vapor deposition, physical vapor deposition, etc.). Other conductive layer materials may be used.
  • Barrier layers and/or adhesion layers 438 may include titanium nitride or another suitable layer such as tantalum nitride, tungsten nitride, combinations of one or more layers, or any other suitable material (s).
  • the deposited conductive layer 440, barrier and/or adhesion layer 438, and/or silicide-forming metal layer 430 may be patterned and/or etched to form the second set of conductors 436.
  • the upper conductors 436 are substantially parallel, substantially coplanar conductors that extend in a different direction than the lower conductors 408.
  • the structure may be annealed to crystallize the deposited semiconductor material of the diodes 428 (and/or to form the suicide regions 432) .
  • the anneal may be performed for about 10 seconds to about 2 minutes in nitrogen at a temperature of about 600 to 800 0 C, and more preferably between about 650 and 750 0 C. Other annealing times, temperatures and/or environments may be used.
  • the suicide regions 432 may serve as
  • diodes 432 “crystallization templates” or “seeds” during annealing for underlying deposited semiconductor material that forms the diodes 432 (e.g., changing any amorphous semiconductor material to polycrystalline semiconductor material and/or improving overall crystalline properties of the diodes 432). Lower resistivity diode material thereby is provided.
  • FIG. 5 is a cross sectional view of an exemplary memory cell 500 provided in accordance with the present invention.
  • the memory cell 500 includes a thin film transistor (TFT) , such as a thin film, metal oxide semiconductor field effect transistor (MOSFET) 502 coupled to a reversible resistance- switching element 504 formed above a substrate 505.
  • TFT thin film transistor
  • MOSFET metal oxide semiconductor field effect transistor
  • the MOSFET 502 may be an n-channel or a p-channel thin film MOSFET formed on any suitable substrate.
  • an insulating region 506 such as silicon dioxide, silicon nitride, oxynitride, etc., is formed above the substrate 505 and a deposited semiconductor region 507 such as deposited silicon, germanium, silicon-germanium, etc., is formed above the insulating region 506.
  • the thin film MOSFET 502 is formed within the deposited semiconductor region 507 and is insulated from the substrate 505 by the insulating region 506.
  • the titanium oxide layer 522 may be formed by oxidizing the titanium-containing layer 521 using oxygen diffusion in a chemical vapor deposition (CVD) chamber with an ozone or other oxygen source, using gaseous or liquid ozone cleaning, or using any other suitable oxidation process.
  • CVD chemical vapor deposition
  • the need for etching of titanium oxide layers may be eliminated and memory cell fabrication significantly simplified.
  • Other materials may be selectively oxidized in accordance with the present invention to form reversible resistivity-switching materials for use in memory cell 500 (e.g., Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V, VN, etc.). As shown in FIG.
  • the dielectric layer 532 may include any suitable dielectric such as silicon dioxide, silicon nitride, silicon oxynitride, low K dielectrics, etc.
  • the reversible resistance- switching element 504 includes a titanium oxide layer having a thickness of about 500 angstroms or less, and more preferably a thickness of about 300 angstroms or less. Other titanium oxide thicknesses may be employed.

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Abstract

Dans certains de ces aspects, l'invention concerne un procédé de formation d'une cellule de mémoire qui consiste (1) à former un premier conducteur sur un substrat; (2) à former un élément de commutation de résistance réversible sur le premier conducteur au moyen d'un procédé de croissance sélectif; (3) à former une diode sur le premier conducteur; et (4) à former un second conducteur sur la diode et l'élément de commutation de résistance réversible. L'invention concerne de nombreux autres aspects.
PCT/US2008/007985 2007-06-29 2008-06-27 Cellule de mémoire utilisant un élément de commutation de résistance réversible à croissance sélective et procédés de formation correspondants Ceased WO2009005699A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010514823A JP2010532568A (ja) 2007-06-29 2008-06-27 選択成長による可逆的抵抗スイッチング素子を使用するメモリセルおよびその形成方法
CN2008800226674A CN101720508B (zh) 2007-06-29 2008-06-27 利用选择性生长的可逆电阻切换元件的存储器单元以及形成该存储器单元的方法
EP08768806A EP2162917A1 (fr) 2007-06-29 2008-06-27 Cellule de mémoire utilisant un élément de commutation de résistance réversible à croissance sélective et procédés de formation correspondants

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US11/772,082 US7824956B2 (en) 2007-06-29 2007-06-29 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US11/772,088 US7902537B2 (en) 2007-06-29 2007-06-29 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
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CN102709471A (zh) 2012-10-03
CN101720508B (zh) 2012-05-23
CN101720508A (zh) 2010-06-02
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KR20100031698A (ko) 2010-03-24
JP2010532568A (ja) 2010-10-07
TW200915543A (en) 2009-04-01

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