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WO2009088069A1 - Procédé de fabrication pour dispositif de condensateur sous boîtier et procédé de fabrication pour boîtier de condensateur sous boîtier - Google Patents

Procédé de fabrication pour dispositif de condensateur sous boîtier et procédé de fabrication pour boîtier de condensateur sous boîtier Download PDF

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Publication number
WO2009088069A1
WO2009088069A1 PCT/JP2009/050200 JP2009050200W WO2009088069A1 WO 2009088069 A1 WO2009088069 A1 WO 2009088069A1 JP 2009050200 W JP2009050200 W JP 2009050200W WO 2009088069 A1 WO2009088069 A1 WO 2009088069A1
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Prior art keywords
capacitor
built
substrate
forming
conductor
Prior art date
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Ceased
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PCT/JP2009/050200
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English (en)
Japanese (ja)
Inventor
Koichi Takemura
Akinobu Shibuya
Akira Ouchi
Yasuhiro Ishii
Tooru Mori
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NEC Corp
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NEC Corp
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Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2009548964A priority Critical patent/JP5423399B2/ja
Publication of WO2009088069A1 publication Critical patent/WO2009088069A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H01L2224/16268—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component the bump connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Definitions

  • the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-002340 (filed on Jan. 9, 2008), the entire description of which is incorporated herein by reference. Shall.
  • the present invention relates to a method for manufacturing a capacitor built-in device (particularly a semiconductor device) in which a capacitor is built in an electronic device, and a method for manufacturing a capacitor built-in package in which the capacitor built-in device is mounted on a circuit board.
  • a voltage drop ⁇ V generated at the time of switching is generally expressed by the following equation (1).
  • ⁇ V ⁇ L ⁇ di / dt (1)
  • di / dt is the time change of the load current flowing through the circuit by switching
  • L is the inductance of the wiring between the LSI and the power supply device.
  • a decoupling capacitor is arranged between the LSI and the power supply so that L in Expression (1) is reduced.
  • Patent Documents 1 to 4 disclose a mounting structure in which an interposer-type capacitor is disposed between an LSI and a circuit board or inside a circuit board surface immediately below the LSI and directly connected to the LSI only through solder bumps. Has been.
  • an interposer type capacitor in which a capacitor is formed on one surface of a substrate on which a through via (through wiring) is formed is manufactured as a discrete component.
  • the manufactured interposer type capacitor is electrically connected to the semiconductor element and the circuit board via solder bumps at connection pads formed at both ends of the through wiring.
  • a cavity is formed on one surface of the substrate on which the capacitor is formed, Cu is embedded in the cavity, and then the other side of the substrate is formed.
  • a substrate via (through wiring) is formed by mechanically grinding the substrate from the surface side to expose Cu at the bottom of the cavity.
  • Patent Documents 1 to 4 The entire disclosures of Patent Documents 1 to 4 above are incorporated herein by reference. The following analysis is given from the viewpoint of the present invention.
  • the interposer type capacitors described in Patent Documents 1 to 4 are manufactured as discrete components (single unit), a sufficient thickness is required so that they can be handled easily during manufacturing and mounting.
  • the thickness that facilitates handling depends on the size of the workpiece or wafer. However, considering that it is possible to manufacture a large number of workpieces simultaneously, the interposer capacitor itself needs to have a thickness of, for example, 200 ⁇ m or more. . Since the interposer type capacitor is inserted, for example, between the semiconductor element and the circuit board, the thickness of the package also increases by the thickness of the interposer type capacitor. If the thickness of the package is increased, it is disadvantageous for downsizing and thinning of the device on which the package is mounted.
  • the signal line of the package becomes longer by the thickness of the interposer type capacitor, causing an increase in transmission loss.
  • many LSIs that require an interposer type capacitor have a large number of I / O pads of 1000 or more, and the interposer type capacitor requires fine through vias (wiring) with a diameter of 50 ⁇ m or less.
  • the diameter of the through via must be increased (in general, the aspect ratio (depth / via diameter) of the through via is about 1). Therefore, it is difficult to form such a fine through via so as to penetrate a substrate having a sufficient thickness so as to be easily handled.
  • the interposer type capacitor is made thin in order to solve these problems, it will be difficult to handle this time, and there will be a problem that the production and mounting of the interposer type capacitor will not be realized at a low cost.
  • an interposer type capacitor is manufactured with a thickness of 100 ⁇ m or less that can solve the above problem, the mechanical strength is weakened, and it is damaged during the manufacturing process, and the thermal history and warpage due to the material laminated on the substrate increase. For this reason, it is difficult to manufacture and mount the interposer type capacitor with high productivity.
  • the method of thinning the capacitor after being connected to the LSI without manufacturing the capacitor as a discrete component for example, a wafer-on-wafer to be connected between wafer states, and an LSI chip selected on the wafer on which the capacitor is formed are used.
  • the former has the disadvantages that the LSI and the capacitor must be made of wafers of the same shape, and that good products cannot be selected and connected. In the latter case, the non-defective products can be selected, but after the LSI and the capacitor are integrated, the process is performed in the shape of the wafer on which the capacitor is formed. Therefore, when the LSI test is performed in this state, there is a drawback that a different probe card or test program must be prepared even when the same test as the wafer state test before dicing the LSI is performed.
  • An object of the present invention is to provide a method of manufacturing a capacitor built-in device in which a thin capacitor having fine through vias is built in an electronic device, not as a discrete component, and a package with a built-in capacitor in which the capacitor built-in device is mounted on a circuit board. It is to provide a method of manufacturing.
  • a method of manufacturing a capacitor built-in device in which a capacitor built-in element is mounted on an electronic device, wherein at least one capacitor having an upper electrode, a dielectric and a lower electrode is used as a unit, and the capacitor substrate.
  • a conductor forming step of forming a conductor electrically connected to any of the above, and a capacitor built-in element formed by each step Capacitor-embedded element singulation process that separates the unit into one unit of the capacitor-embedded element, and a plurality of capacitors with one surface facing the electronic element so that the conductor and the electronic element are electrically connected
  • Capacitor-embedded element mounting process for flip-chip mounting of the capacitor-embedded element on the electronic element, capacitor substrate thinning process for thinning the capacitor board so that the conductor in the recess is exposed, and a capacitor built-in formed by each process
  • a manufacturing method of a device with a built-in capacitor including a
  • the method for manufacturing the capacitor-embedded device when the capacitor substrate is non-insulating, is configured so that the capacitor substrate and the conductor are not electrically connected in the interlayer insulating film forming step.
  • An insulating film forming step is further included in which an insulating film is formed on the other surface of the capacitor substrate so that the conductor in the recess is exposed after the capacitor thinning step.
  • a method of manufacturing a capacitor built-in device in which a capacitor built-in element is mounted on an electronic device, wherein at least one capacitor having an upper electrode, a dielectric and a lower electrode is used as a unit, and the capacitor substrate
  • a capacitor forming step of forming a plurality of capacitors on one surface of the capacitor, an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate, and at least a part of one surface of the electronic device A conductor forming process for forming a conductor that is in contact with a predetermined region where a capacitor is not formed, penetrates the interlayer insulating film, and is electrically connected to either the upper electrode or the lower electrode, and is formed by each process.
  • Capacitor-embedded element mounting process for flip-chip mounting a plurality of capacitor-embedded elements on the electronic element with one surface of the capacitor substrate facing the electronic element so as to be electrically connected, and the capacitor substrate is thinned to a predetermined thickness
  • a through-hole conductor forming step for forming a through-hole conductor for covering or filling the through-hole, and a capacitor built-in device that separates the assembly of capacitor built-in devices formed by each step into units for each capacitor built-in element
  • a method for manufacturing a device with a built-in capacitor including a device dividing step.
  • the method for manufacturing the capacitor-embedded device when the capacitor substrate is non-insulating, is configured so that the capacitor substrate and the conductor are not electrically connected in the interlayer insulating film forming step. It further includes an insulating film step of forming an insulating film and forming an insulating film on the inner surface of the through hole and the other surface of the capacitor substrate before the through hole conductor forming step.
  • the capacitor substrate in the capacitor substrate thinning step, is thinned by at least one of grinding and etching.
  • the method for manufacturing a device with a built-in capacitor further includes an electronic element thinning step for thinning the electronic device before the step of separating the device with a built-in capacitor.
  • the method for manufacturing a capacitor-embedded device further includes a first non-defective product selection step of electrically testing the capacitor-embedded element and the electronic element before the capacitor-embedded element mounting step. Including.
  • a dummy chip is mounted in at least one area instead of the built-in capacitor element.
  • the method for manufacturing a capacitor built-in device further includes a second non-defective product selection step of electrically testing the capacitor built-in device before the capacitor built-in device individualization step.
  • a method for manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board, the device including at least an upper electrode, a dielectric, and a lower electrode.
  • Capacitor board so that the assembly of the capacitor built-in device formed in each process is divided into individual units for each element with built-in capacitor, and the conductor and the circuit board are electrically connected
  • Mounting the built-in capacitor device by flip-chip mounting the separated capacitor built-in device on the circuit board with the other side of the capacitor facing the circuit board
  • a method for manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board.
  • One capacitor as a unit a capacitor forming step of forming a plurality of units on one surface of the capacitor substrate, an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate, and at least A part of the electronic device is in contact with a predetermined region where a capacitor is not formed, penetrates the interlayer insulating film, and forms a conductor electrically connected to either the upper electrode or the lower electrode.
  • Capacitor-embedded device singulation process that separates the assembly into individual capacitors-embedded elements, and the through-hole conductor and circuit board are electrically connected
  • the other surface of the capacitor substrate by the circuit board facing to provide a method of manufacturing a capacitor built-in package comprising a built-in capacitor device mounting step of flip-chip mounting a capacitor-containing apparatus which is sectioned in the circuit board, the.
  • the present invention has at least one of the following effects.
  • the capacitor built-in element can be made thicker than the final form and subjected to processing such as mounting with a thickness that is easy to handle, damage during the process can be prevented, and the capacitor built-in device and Productivity and quality reliability of the capacitor built-in package can be improved.
  • the capacitor substrate is thinned to a desired thickness, so that a thinner capacitor built-in device and a capacitor built-in package can be manufactured.
  • the thickness of the element part with a built-in capacitor can be set to 100 ⁇ m or less including the height of one solder bump.
  • the diameter of the recess or the through hole can be kept small.
  • the device with a built-in capacitor and the package with a built-in capacitor can be further downsized.
  • the diameter of the recess or the through hole can be set to 50 ⁇ m or less.
  • the electronic element is, for example, a semiconductor element (for example, an LSI)
  • the device with a built-in capacitor and the package with a built-in capacitor can be further reduced in thickness by thinning the substrate of the semiconductor element.
  • the capacitor built-in element can be subjected to an electrical test even before the capacitor substrate is thinned, the electrical test of the capacitor built-in element and the electronic element is performed in advance before mounting the capacitor built-in element.
  • the productivity of the capacitor built-in device and the capacitor built-in package can be improved.
  • the arrangement of the pads of the electronic element does not change before and after mounting the built-in capacitor element.
  • FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
  • FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
  • FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
  • FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
  • FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
  • FIG. 9 is a schematic partial cross-sectional view showing details of one unit of the capacitor built-in device in FIG. 8.
  • FIG. 9 is a schematic partial cross-sectional view showing details of one unit of the capacitor built-in device in FIG. 8.
  • FIG. 1 to 5 are schematic process diagrams for explaining a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the first embodiment of the present invention.
  • FIG. 1 is an overall schematic cross-sectional view of a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the first embodiment of the present invention
  • FIGS. 2 to 5 show details of one unit of the capacitor built-in device in FIG. It is a general
  • the lower electrode 3 and the dielectric On one surface 2a of the plate-like capacitor substrate 2 made of a heat-resistant material such as glass and having a thickness that is easy to handle (for example, 0.2 mm or more, preferably 0.5 mm or more), the lower electrode 3 and the dielectric A plurality of units of at least one capacitor 10 are formed using at least one thin film capacitor 10 composed of the body 4 and the upper electrode 5 as a unit (capacitor forming step; FIG. 2A) (in FIG. 3 units of capacitor 10 is formed with the capacitor as one unit). Details of one unit are set as appropriate according to the power supply configuration inside the electronic element to be mounted later.
  • a suitable thickness of the capacitor substrate 2 that is easy to handle depends on the thickness of the capacitor substrate 2.
  • the thickness is about 0.5 mm or more and the diameter is about 150 mm ( 6 inches) is preferably 0.6 mm or more, and in the case of a diameter of about 200 mm (8 inches), 0.7 mm or more is preferable.
  • the method of forming the lower electrode 3 and the upper electrode 5 of the capacitor 10 is not limited, but a sputtering method, a chemical vapor deposition method (CVD method), and the like, which are easy to deposit a uniform metal film or alloy film. Etc.) are preferred.
  • a method for forming the dielectric 4 is not limited, but a sputtering method, a CVD method, a sol-gel method, or the like that can form a uniform and good insulating oxide film or nitride film at a low temperature is preferable.
  • the electrodes 3 and 5 and the dielectric film 4 are preferably processed and formed by dry etching that enables accurate processing.
  • the capacitor 10 is not formed in a region where a through wiring that connects connection pads to an electronic element or a circuit board is formed later.
  • the capacitor substrate 2 is preferably made of a material having high surface smoothness and high heat resistance in order to form a thin and high-capacity capacitor.
  • a semiconductor substrate such as Si or GaAs or an inorganic material such as glass, sapphire, or quartz.
  • An insulator substrate can be used. However, it is not limited to these materials, and it is also possible to use a ceramic whose surface is polished, a high heat resistance resin, or a metal whose insulating layer is formed on the surface. A method using the non-insulating capacitor substrate 2 will be described in the second embodiment.
  • the material of the dielectric 4 of the capacitor 10 is not limited, but a material having a high relative dielectric constant and capable of being thinned and having good insulating properties is preferable.
  • a material having a high relative dielectric constant and capable of being thinned and having good insulating properties is preferable.
  • High dielectric constant oxide having silicon nitride, titanium oxide or perovskite structure is more preferable.
  • As a high dielectric constant oxide having a perovskite structure SrTiO 3 , BaTiO 3 , PbTiO 3 , SrBi 2 Ta 2 O 9 , PbBi 2 Ta 2 O 9 and a solid solution thereof, or at least one of them are mainly composed. Compounds as components are preferred.
  • the material of the electrodes 3 and 5 of the capacitor is not limited, but a high melting point metal such as Pt, Ru, Ir, or TiN is preferable. It is more preferable to form a laminated structure in which Ti, Cr, Ta, Mo or the like is inserted in order to ensure adhesion between the electrode metal and the capacitor substrate 2 or an interlayer insulating film to be formed later and to prevent diffusion.
  • a high melting point metal such as Pt, Ru, Ir, or TiN is preferable. It is more preferable to form a laminated structure in which Ti, Cr, Ta, Mo or the like is inserted in order to ensure adhesion between the electrode metal and the capacitor substrate 2 or an interlayer insulating film to be formed later and to prevent diffusion.
  • a region on one surface 2a of the capacitor substrate 2 corresponding to a region where a pad is formed on the other surface 2b side of the capacitor substrate 2 (later electrically with the circuit substrate).
  • a resist 6 is formed on one surface 2a of the capacitor substrate 2 so that a region where a contact hole for connection is formed is exposed (FIG. 2B).
  • a recess (cavity) 7 having a predetermined depth not penetrating the capacitor substrate 2 is formed on one surface 2a of the capacitor substrate 2 by a dry etching method or the like (recess formation step; FIG. 1 (c), FIG. 2 (c)).
  • the depth of the recess 7 is designed to be at least equal to the thickness of the capacitor substrate 2 in the final capacitor built-in device.
  • the depth of the concave portion 7 is not limited, but the concave portion 7 can be formed from the viewpoint of suppressing the final increase in the thickness of the capacitor built-in device or the entire package, reducing the transmission loss of the signal wiring, or facilitating the formation of the through wiring.
  • the depth of is preferably shallower, for example, preferably 50 ⁇ m or less, and more preferably 20 ⁇ m.
  • the formation method of the recessed part 7 is not limited, Reactive dry etching, wet etching, laser processing, sandblasting, drilling, etc. are preferable.
  • An interlayer insulating film 8a having a contact hole is formed of a photosensitive resin or the like so that the region and the recess 7 are exposed (interlayer insulating film forming step; FIG. 2D).
  • the interlayer insulating film 8a is preferably formed by a CVD method or a sol-gel method if it is an inorganic material, or by a spin coating method if it is a resin, because it is easy to form a uniform insulating film.
  • the contact hole is preferably formed by a dry etching method if the interlayer insulating film 8a is an inorganic material or a non-photosensitive resin, and photolithography is preferable if it is a photosensitive resin.
  • a resist 6 is formed in a region where an interlayer insulating film is to be formed, and a conductor 9 is formed on the recess 7, the lower electrode 3, the upper electrode 5, and the interlayer insulating film 8a (conductor forming step; FIG. 2). (E)).
  • the conductor 9 is covered in the recess 7 or filled in the recess 7.
  • the conductor 9 is electrically connected to either the lower electrode 3 or the upper electrode 5 (which can be connected to the power supply or ground of the electronic element, respectively) and is formed so as to penetrate the interlayer insulating film 8a.
  • the lower electrodes 3 and the upper electrodes 5 in one unit may be electrically connected to each other by the conductor 9.
  • the filling method of the conductor 9 is not limited, but it is preferable to deposit the conductor 9 by a plating method, a printing method, an aerosol by a position (AD) method or the like because the conductor 9 can be embedded in the recess 7 at the same time.
  • the material of the conductor 9 is not limited, but Cu, Ag, Au, or an alloy containing these as main components is particularly preferable because it has a low resistance value and can be easily filled.
  • an interlayer insulating film 8b is formed (FIG. 3 (f)), and a connection pad 11 for electrical connection with an electronic element is formed (FIG. 1 (g), FIG. 3 (g)).
  • an electrical test is performed to select non-defective products (accepted products) (first non-defective product selection step).
  • the test method is not limited. For example, it is possible to select non-defective products by measuring the impedance using an alternating current or a physical quantity corresponding to the impedance or measuring the leakage current of a direct current low voltage.
  • the aggregate of the capacitor built-in elements 12 is singulated for each unit of the capacitor built-in element mounted on the electronic element (capacitor built-in element individualization step; FIG. 1 (h)).
  • a cover insulating film 13 and a solder bump 14 are formed on the capacitor built-in element 12 selected as a non-defective product (FIG. 3 (i)), and an electronic element having a plurality of units to be mounted on a circuit board (for example, on a substrate (wafer))
  • a plurality of capacitor built-in elements 12 are flip-chip mounted on a plurality of LSIs 15 (capacitor built-in element mounting step; FIG. 1 (j)).
  • the capacitor built-in element 12 is mounted in units of electronic elements that have been selected as non-defective products in a prior electrical test, and when there are electronic element units that have been selected as defective products, a dummy chip is placed on the defective electronic elements.
  • the dummy chip is not a non-defective capacitor built-in element, but is preferably formed of the same size and the same substrate material (the capacitor 10 is not formed).
  • a dummy chip is also mounted when a region where the capacitor built-in element 12 is not mounted is large (for example, when a region where an LSI is not formed is large at the wafer peripheral portion or the like).
  • capacitors or dummy chips of the same material are evenly mounted on the entire surface of the electronic device, and the thinning in the subsequent process can be performed uniformly, and stress that causes cracks and the like is not concentrated on a specific location. Can be.
  • an underfill resin 16 is filled in the solder connection portion between the capacitor built-in element 12 and the electronic element 15 and the periphery of the capacitor built-in element 12. Thereby, destruction tolerance and connection reliability can be improved in a later process.
  • a mold resin 17 is filled in the gap between the mounted capacitor built-in element 12 and the dummy chip, and the peripheral edge of the electronic element where these do not exist (FIG. 1 (k), FIG. 4 (k)). Thereby, it is possible to further improve the uniformity of thinning and the fracture resistance in the subsequent process.
  • the capacitor substrate 2 is thinned to a predetermined thickness until at least the conductor 9 filled in the recess 7 is exposed using the substrate of the electronic element 15 (for example, a wafer on which an LSI is formed) as a support.
  • the substrate of the electronic element 15 for example, a wafer on which an LSI is formed
  • the other surface 2b side of the capacitor substrate 2 of the capacitor built-in element 12 can be mechanically ground until the bottom of the recess 7 is exposed.
  • mechanical grinding may be performed to such an extent that the bottom of the recess 7 is not exposed, and then the conductor 9 in the recess 7 may be exposed by reactive dry etching. According to this method, it is possible to selectively thin the material when the recess 7 is exposed, and it is possible to suppress breakage due to mechanical processing at the boundary between the conductor 9 and the capacitor substrate 2.
  • a connection pad, a cover insulating film 18 and a solder bump 19 are formed on the other surface 2b side of the capacitor substrate 2 of the capacitor built-in element 12.
  • the entire thickness of the electronic element 15 can be adjusted to a desired thickness by grinding the back side of the electronic element 15 (for example, the back side of the wafer on which the LSI is formed) in this state (electronic element). Thinning process).
  • the I / O pad on the electronic device substrate (for example, LSI wafer) is in the same state as before the capacitor built-in device 12 is mounted, and as a circuit, a capacitor is formed between the power supply and the ground.
  • the same test as the electrical test after the electronic element 15 is formed should be performed using the same test apparatus, the same probe card, etc. Is possible. Furthermore, even when the electronic device 15 alone is insufficient in decoupling capacity and a sufficient electrical test cannot be performed, it is possible to perform an electrical test of the electronic device 15 in a state where the decoupling capacitor is mounted. 2 good product selection process).
  • the assembly of the capacitor built-in device 1 is separated into individual units by dicing so that the capacitor built-in device 1 in which the capacitor is built in the electronic device (for example, the capacitor decoupling capacitor and the LSI are integrated). (Semiconductor device) is obtained (capacitor built-in device singulation step; FIG. 1 (m), FIG. 5 (m)).
  • the capacitor built-in device 1 is mounted on the circuit board 20 and the underfill resin 21 is filled between the capacitor built-in device 1 and the circuit board 20 to manufacture the capacitor built-in package 31 (capacitor built-in device mounting step; FIG. 1 (n), FIG. 5 (n)).
  • a mounting method of the capacitor built-in device for example, a method similar to that of a normal semiconductor device mounting method or device can be adopted.
  • a thin capacitor built-in device and capacitor built-in package can be obtained without going through a thin capacitor built-in element that is difficult to handle.
  • non-defective capacitors with built-in capacitors and electronic elements can be combined, and more than one can be manufactured at the same time, so that devices with built-in capacitors and capacitors with built-in capacitors can be manufactured with high yield. Since the capacitor built-in element in a state where the conductor in the recess is not exposed is mounted on the electronic element, the same electrical test as before mounting the capacitor built-in element can be performed with the capacitor element mounted. Further, for mounting the capacitor built-in device on the circuit board, the same method and apparatus as those for mounting a normal electronic device can be used. Therefore, it is possible to improve manufacturability, productivity, quality reliability, and cost as compared with a method of manufacturing a capacitor built-in element as a discrete component.
  • the bonding method between the capacitor built-in element 12 and the electronic element 15 and the bonding method between the capacitor built-in device 1 and the circuit board 20 are not limited to solder bumps, and for example, pads may be bonded directly.
  • the material of the interlayer insulating film 8 and the cover insulating films 13 and 18 is not limited.
  • inorganic insulating materials such as SiO 2 and Si 3 N 4 and resins such as polyimide and epoxy are preferable because they can be easily processed.
  • FIGS. 6 and 7 are schematic process diagrams for explaining a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the second embodiment of the present invention.
  • 6 and 7 are schematic partial sectional views showing details of one unit of the capacitor built-in device.
  • the capacitor built-in device using the insulating substrate and the method for manufacturing the capacitor built-in package have been described.
  • the capacitor built-in device and the capacitor using a non-insulating substrate such as a semiconductor or metal are used.
  • a method for manufacturing the built-in package will be described. This manufacturing method can also be applied to an insulating substrate.
  • a capacitor 10 is formed on the capacitor substrate 2 and a recess 7 is formed (FIG. 6A).
  • a first oxide such as a silicon oxide film is formed on the capacitor substrate 2 (including the inner wall of the recess 7) and the capacitor 10 using a CVD method or the like so that the conductor formed below and the capacitor substrate are not electrically connected.
  • An interlayer insulating film 38 is formed (FIG. 6B).
  • a contact hole 38a for forming an electrical connection with the lower electrode 3 or the upper electrode 5 is formed in the first interlayer insulating film 38 (FIG. 6C).
  • connection pads 11 for electrical connection, electrical test of the capacitor 10, separation of the assembly of elements with built-in capacitors, formation of the cover insulating film 13 and the solder bumps 14 are performed (FIG. 6 (e)). .
  • the built-in capacitor element 42 is mounted on the electronic element 15, the underfill resin 16 and the mold resin 17 are formed, and the capacitor substrate 2 is thinned. It implements (FIG.7 (f)).
  • the capacitor substrate 2 is thinned, the capacitor substrate 2 is thinned at least until the conductor 9 in the recess 7 is exposed.
  • a third insulating film 43 for insulating from the capacitor substrate 2 is formed, and a contact hole 43a for electrical connection with the conductor 9 in the recess 7 is formed in the third insulating film 43 (third insulating film). Film formation step; FIG. 7 (g)).
  • the third insulating film 43 may be an inorganic material typified by SiO 2 or a resin, but if the same material as the first interlayer insulating film 38 covering the thin film capacitor 10 is used, the stress on the front and back of the capacitor substrate 2 is balanced. This is preferable in that the warpage of the sheet becomes small.
  • the capacitor built-in device 41 is manufactured by forming the connection pad, the cover insulating film 18 and the solder bump 19 and separating the capacitor built-in device into individual pieces (FIG. 7 (h)).
  • a capacitor built-in package can be manufactured by mounting the capacitor built-in device 41 on a circuit board (not shown).
  • FIGS. 9 to 10 are schematic process diagrams for explaining a method for manufacturing a capacitor built-in device and a capacitor built-in package according to a third embodiment of the present invention.
  • FIG. 8 is an overall schematic cross-sectional view of a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the third embodiment of the present invention.
  • FIGS. 9 to 10 are details of a unit of the capacitor built-in device in FIG. It is a general
  • the alphabets indicating the process order shown in FIG. 8 and the alphabets indicating the process order shown in FIGS. 9 to 10 correspond to each other.
  • the concave portion is formed in the capacitor substrate before the capacitor built-in element is mounted on the electronic device.
  • the through hole is formed in the capacitor substrate. (Cavity) is formed.
  • the capacitor 10 is formed on the capacitor substrate 2 in the same manner as in the first embodiment (capacitor forming step; FIGS. 8A and 9A).
  • a capacitor built-in element 52 is formed in the same manner as in the first embodiment except that no recess is formed in the capacitor substrate 2 (interlayer insulating film forming process, conductor forming process, capacitor built-in element individualizing process) FIG. 8 (b) and FIG. 9 (b)).
  • the capacitor built-in element 52 is mounted on the electronic element 15 to form the underfill resin 16 and the mold resin 17 (capacitor built-in element mounting process; FIGS. 8C to 8D). ), FIG. 9 (d)).
  • the capacitor substrate 2 is thinned to a predetermined thickness (capacitor substrate thinning step; FIGS. 8E and 9E).
  • a through hole 53 is formed in the capacitor substrate 2 so as to expose the conductor 9 in a region for electrical connection with the conductor 9 (through hole forming step; FIG. 8 (f), FIG. f)).
  • a method for forming the through hole 53 a method similar to the method for forming a recess in the first embodiment can be used.
  • a connection pad (through wiring) 54 is formed in the through hole 53 so as to be electrically connected to the conductor 9 (through hole conductor forming step; FIG. 10G).
  • the capacitor built-in device 51 can be obtained by forming the cover insulating film 18 and the solder bump 19 and separating the assembly of the capacitor built-in device (single-capacitor device separation step). FIG. 8 (h) and FIG. 10 (h)).
  • the capacitor built-in package 61 can be obtained by mounting the capacitor built-in device 51 on the circuit board 20 (FIG. 8I).
  • the capacitor substrate can be made thinner than when the recess is present, for example, when mechanical grinding is used.
  • the third embodiment has been described based on the first embodiment in which the capacitor substrate is an insulating substrate.
  • the capacitor substrate in the third embodiment is a non-insulating substrate.
  • a form similar to the third embodiment in which the through hole is formed after the capacitor substrate is thinned can be implemented based on the second embodiment.
  • the main change is that the capacitor substrate is not electrically connected to the conductor and the connection pad.
  • the third insulating film is also formed on the inner wall of the through hole.
  • a semiconductor element for example, LSI
  • LSI semiconductor element
  • the present invention is particularly applicable to LSIs in general, and suppresses switching noises of LSIs in electronic devices such as computers, mobile phones, digital home appliances, and the like that are particularly required to operate at low voltage and high speed, thereby enabling stable operation. Can be applied.
  • the disclosures of the aforementioned patent documents and the like are incorporated herein by reference.
  • the embodiments and examples can be changed and adjusted based on the basic technical concept.
  • Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Inorganic Chemistry (AREA)
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Abstract

La présente invention a trait à un procédé permettant de produire très efficace un dispositif de condensateur sous boîtier, dans lequel un condensateur de type mince équipé de fins trous d'interconnexion traversants est mis sous boîtier, non pas en tant que composants discrets d'un dispositif électronique, et à un procédé de fabrication de boîtier de condensateur sous boîtier, dans lequel le dispositif de condensateur sous boîtier est mis sous boîtier dans un substrat de circuit. Le procédé de fabrication de dispositif de condensateur sous boîtier comprend une étape consistant à former un condensateur dans un substrat de condensateur, une étape consistant à former un évidement dont la profondeur, dans une zone prédéterminée du substrat de condensateur, ne s'étend pas à travers le substrat de condensateur, une étape consistant à former un film isolant de couche intermédiaire et un conducteur (comprenant un évidement à l'intérieur) sur le substrat de condensateur et à former un élément de condensateur sous boîtier au moyen d'une individualisation, une étape consistant à monter l'élément de condensateur sous boîtier dans un élément électronique de manière à ce que la surface de formation de condensateur du substrat de condensateur et l'élément électronique puissent se faire face, une étape consistant à affiner le substrat de condensateur de manière à ce que le conducteur présent dans l'évidement puisse être exposé à l'extérieur, et une étape consistant à former le dispositif de condensateur sous boîtier au moyen de l'individualisation.
PCT/JP2009/050200 2008-01-09 2009-01-09 Procédé de fabrication pour dispositif de condensateur sous boîtier et procédé de fabrication pour boîtier de condensateur sous boîtier Ceased WO2009088069A1 (fr)

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CN118073332A (zh) * 2024-02-26 2024-05-24 广州增芯科技有限公司 一种倒装芯片结构、半导体器件及制备方法

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US9698195B2 (en) 2012-05-30 2017-07-04 Olympus Corporation Method for producing image pickup apparatus and method for producing semiconductor apparatus
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JPWO2013179764A1 (ja) * 2012-05-30 2016-01-18 オリンパス株式会社 撮像装置の製造方法および半導体装置の製造方法
JPWO2013179766A1 (ja) * 2012-05-30 2016-01-18 オリンパス株式会社 撮像装置、半導体装置および撮像ユニット
JPWO2013179767A1 (ja) * 2012-05-30 2016-01-18 オリンパス株式会社 撮像装置の製造方法および半導体装置の製造方法
US9240398B2 (en) 2012-05-30 2016-01-19 Olympus Corporation Method for producing image pickup apparatus and method for producing semiconductor apparatus
US9123618B2 (en) 2012-05-30 2015-09-01 Olympus Corporation Method for producing image pickup apparatus, and method for producing semiconductor apparatus
WO2013179764A1 (fr) * 2012-05-30 2013-12-05 オリンパス株式会社 Procédés de fabrication de dispositif d'imagerie, et de dispositif à semi-conducteurs
JPWO2013179765A1 (ja) * 2012-05-30 2016-01-18 オリンパス株式会社 撮像装置の製造方法および半導体装置の製造方法
CN108022916A (zh) * 2016-11-04 2018-05-11 三星电子株式会社 半导体封装和制造半导体封装的方法
CN108022916B (zh) * 2016-11-04 2022-11-08 三星电子株式会社 半导体封装和制造半导体封装的方法
US20220230806A1 (en) * 2021-01-20 2022-07-21 Powerchip Semiconductor Manufacturing Corporation Multi-layer capacitor unit and manufacturing process thereof
CN114864819A (zh) * 2021-01-20 2022-08-05 力晶积成电子制造股份有限公司 电容集成结构、电容单元及其制造方法
US11854742B2 (en) * 2021-01-20 2023-12-26 Powerchip Semiconductor Manufacturing Corporation Capacitor intergated structure.capacitor unit and manufacturing process thereof
US20240062957A1 (en) * 2021-01-20 2024-02-22 Powerchip Semiconductor Manufacturing Corporation Capacitor integrated structure and capacitor unit
CN118073332A (zh) * 2024-02-26 2024-05-24 广州增芯科技有限公司 一种倒装芯片结构、半导体器件及制备方法
CN118073332B (zh) * 2024-02-26 2025-10-28 广州增芯科技有限公司 一种倒装芯片结构、半导体器件及制备方法

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