[go: up one dir, main page]

WO2008139915A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2008139915A1
WO2008139915A1 PCT/JP2008/058173 JP2008058173W WO2008139915A1 WO 2008139915 A1 WO2008139915 A1 WO 2008139915A1 JP 2008058173 W JP2008058173 W JP 2008058173W WO 2008139915 A1 WO2008139915 A1 WO 2008139915A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
silicon substrate
type
side wall
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/058173
Other languages
English (en)
French (fr)
Inventor
Masaru Takaishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to US12/598,961 priority Critical patent/US8399915B2/en
Publication of WO2008139915A1 publication Critical patent/WO2008139915A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

　チャネル領域のホール移動度を向上させることによって、オン抵抗を低減させることが可能な半導体装置を提供する。このトレンチゲート型のＭＯＳＦＥＴ（半導体装置）（５０）は、主表面の結晶面が（１１０）面であるｐ型のシリコン基板（１）と、シリコン基板（１）上に形成されたエピタキシャル層（２）と、エピタキシャル層（２）に形成され、シリコン基板（１）の厚み方向（Ｚ方向）と平行な側壁を含むトレンチ（３）と、トレンチ（３）内にゲート絶縁膜（４）を介して形成されたゲート電極（５）と、トレンチ（３）の側壁に沿って形成されるｎ型のチャネル領域（２ｂ）と、シリコン基板（１）の厚み方向（Ｚ方向）に、チャネル領域（２ｂ）を挟むように形成されたｐ型のソース領域（２ｃ）およびｐ型のドレイン領域（２ａ）とを備えている。また、トレンチ（３）は、側壁の結晶面が（１１０）面となるように形成されている。
PCT/JP2008/058173 2007-05-08 2008-04-28 半導体装置 Ceased WO2008139915A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/598,961 US8399915B2 (en) 2007-05-08 2008-04-28 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-123408 2007-05-08
JP2007123408A JP2008282859A (ja) 2007-05-08 2007-05-08 半導体装置

Publications (1)

Publication Number Publication Date
WO2008139915A1 true WO2008139915A1 (ja) 2008-11-20

Family

ID=40002129

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/058173 Ceased WO2008139915A1 (ja) 2007-05-08 2008-04-28 半導体装置

Country Status (4)

Country Link
US (1) US8399915B2 (ja)
JP (1) JP2008282859A (ja)
TW (1) TW200910592A (ja)
WO (1) WO2008139915A1 (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20122226A1 (it) * 2012-12-21 2014-06-22 St Microelectronics Srl Realizzazione di dispositivi elettronici in un wafer in materiale semiconduttore con trincee aventi direzioni diverse
US9209304B2 (en) * 2014-02-13 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. N/P MOS FinFET performance enhancement by specific orientation surface
JP6566512B2 (ja) 2014-04-15 2019-08-28 ローム株式会社 半導体装置および半導体装置の製造方法
KR20170099444A (ko) * 2016-02-23 2017-09-01 삼성전자주식회사 반도체 장치 및 그 제조 방법
JPWO2019103135A1 (ja) * 2017-11-24 2020-11-19 ローム株式会社 半導体装置
KR102662765B1 (ko) 2018-08-02 2024-05-02 삼성전자주식회사 기판과 이를 포함하는 집적회로 소자 및 그 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231948A (ja) * 2001-02-06 2002-08-16 Denso Corp トレンチゲート型半導体装置及びその製造方法
JP2004349428A (ja) * 2003-05-21 2004-12-09 Tadahiro Omi 半導体装置およびその製造方法
JP2005244168A (ja) * 2004-01-27 2005-09-08 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667906B2 (ja) 1996-11-25 2005-07-06 三洋電機株式会社 半導体装置及び半導体装置の製造方法
JP3715971B2 (ja) * 2003-04-02 2005-11-16 ローム株式会社 半導体装置
US7372088B2 (en) 2004-01-27 2008-05-13 Matsushita Electric Industrial Co., Ltd. Vertical gate semiconductor device and method for fabricating the same
US8039877B2 (en) * 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231948A (ja) * 2001-02-06 2002-08-16 Denso Corp トレンチゲート型半導体装置及びその製造方法
JP2004349428A (ja) * 2003-05-21 2004-12-09 Tadahiro Omi 半導体装置およびその製造方法
JP2005244168A (ja) * 2004-01-27 2005-09-08 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US8399915B2 (en) 2013-03-19
TW200910592A (en) 2009-03-01
US20100090258A1 (en) 2010-04-15
JP2008282859A (ja) 2008-11-20

Similar Documents

Publication Publication Date Title
WO2009063588A1 (ja) 半導体装置及びその製造方法
WO2008123352A1 (ja) 半導体装置
TW200625630A (en) Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
TW200623414A (en) Semiconductor device and fabrication method thereof
TW200701460A (en) Semiconductor device and production method thereof
WO2010036942A3 (en) Power mosfet having a strained channel in a semiconductor heterostructure on metal substrate
TW200631175A (en) Semiconductor device
WO2008105077A1 (ja) 化合物半導体装置とその製造方法
WO2008102451A1 (ja) 半導体装置及びその製造方法
TW200715562A (en) Thin film transistor substrate and fabrication thereof
WO2007110832A3 (en) Trench-gate semiconductor device and method of fabrication thereof
JP2009283496A5 (ja)
WO2007147102A3 (en) High voltage ldmos
NZ590751A (en) Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making
SG139632A1 (en) Structure and method to implement dual stressor layers with improved silicide control
WO2018002048A8 (en) Short channel trench power mosfet
WO2008002879A3 (en) Lateral trench gate fet with direct source-drain current path
JP2011077509A5 (ja) トランジスタ
EP2600402A4 (en) SEMICONDUCTOR DEVICE
TW200633125A (en) Semiconductor device and method of semiconductor device
GB2497060A (en) Method and structure for pFET junction profile with SiGe channel
WO2008099528A1 (ja) 表示装置、表示装置の製造方法
WO2011133339A3 (en) Monolayer dopant embedded stressor for advanced cmos
SG169278A1 (en) Integrated circuit system with band to band tunneling and method of manufacture thereof
WO2008139915A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08740905

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12598961

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08740905

Country of ref document: EP

Kind code of ref document: A1