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WO2008111205A1 - Procédé de fabrication d'un dispositif semiconducteur, tranche et appareil de nettoyage de tranche - Google Patents

Procédé de fabrication d'un dispositif semiconducteur, tranche et appareil de nettoyage de tranche Download PDF

Info

Publication number
WO2008111205A1
WO2008111205A1 PCT/JP2007/055194 JP2007055194W WO2008111205A1 WO 2008111205 A1 WO2008111205 A1 WO 2008111205A1 JP 2007055194 W JP2007055194 W JP 2007055194W WO 2008111205 A1 WO2008111205 A1 WO 2008111205A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
cleaning
semiconductor device
cutting out
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/055194
Other languages
English (en)
Japanese (ja)
Inventor
Masayuki Kikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to PCT/JP2007/055194 priority Critical patent/WO2008111205A1/fr
Publication of WO2008111205A1 publication Critical patent/WO2008111205A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67051—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

L'invention vise à proposer un procédé pour la fabrication d'un dispositif semiconducteur, dans lequel l'occurrence de matières de défaut par accumulation statique au niveau du nettoyage d'une surface de tranche peut être supprimée, un procédé apparent de nettoyage de tranche et un appareil de nettoyage ; et une tranche appropriée pour ceux-ci. A cet effet, le procédé de fabrication d'un dispositif semiconducteur comprend l'étape de formation de motifs consistant à former des motifs de circuit sur une tranche sur ses zones partitionnées ; l'étape de nettoyage consistant à nettoyer la surface de tranche par l'application d'un jet de liquide de nettoyage sur celle-ci tout en faisant tourner la tranche dotée des motifs de circuit ; l'étape de découpe consistant à découper des morceaux de tranche par des partitions ; et l'étape de séparation, ayant défini en tant que zone de contre-mesure contre l'accumulation statique une zone contenant une région à l'intérieur d'un rayon donné à partir du centre de rotation ou des charges apparaissant sur la tranche à l'étape de nettoyage sont susceptibles de s'accumuler, consistant à découper la zone de contre-mesure contre l'accumulation statique et à retirer celle-ci des puces semiconductrices en tant que produit.
PCT/JP2007/055194 2007-03-15 2007-03-15 Procédé de fabrication d'un dispositif semiconducteur, tranche et appareil de nettoyage de tranche Ceased WO2008111205A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055194 WO2008111205A1 (fr) 2007-03-15 2007-03-15 Procédé de fabrication d'un dispositif semiconducteur, tranche et appareil de nettoyage de tranche

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055194 WO2008111205A1 (fr) 2007-03-15 2007-03-15 Procédé de fabrication d'un dispositif semiconducteur, tranche et appareil de nettoyage de tranche

Publications (1)

Publication Number Publication Date
WO2008111205A1 true WO2008111205A1 (fr) 2008-09-18

Family

ID=39759156

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055194 Ceased WO2008111205A1 (fr) 2007-03-15 2007-03-15 Procédé de fabrication d'un dispositif semiconducteur, tranche et appareil de nettoyage de tranche

Country Status (1)

Country Link
WO (1) WO2008111205A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2011135979A1 (ja) * 2010-04-28 2013-07-18 コニカミノルタ株式会社 撮像用レンズの製造方法
CN115036207A (zh) * 2022-06-28 2022-09-09 上海华力集成电路制造有限公司 改善晶圆尖端放电缺陷的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04114425A (ja) * 1990-09-04 1992-04-15 Fujitsu Ltd 半導体装置の製造方法
JPH08330594A (ja) * 1995-05-31 1996-12-13 Sony Corp 絶縁体基板の製造方法および半導体装置の製造方法
JPH10308374A (ja) * 1997-03-06 1998-11-17 Ebara Corp 洗浄方法及び洗浄装置
JP2002100750A (ja) * 2000-09-25 2002-04-05 Mitsubishi Materials Silicon Corp Ｓｏｉ基板及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04114425A (ja) * 1990-09-04 1992-04-15 Fujitsu Ltd 半導体装置の製造方法
JPH08330594A (ja) * 1995-05-31 1996-12-13 Sony Corp 絶縁体基板の製造方法および半導体装置の製造方法
JPH10308374A (ja) * 1997-03-06 1998-11-17 Ebara Corp 洗浄方法及び洗浄装置
JP2002100750A (ja) * 2000-09-25 2002-04-05 Mitsubishi Materials Silicon Corp Ｓｏｉ基板及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2011135979A1 (ja) * 2010-04-28 2013-07-18 コニカミノルタ株式会社 撮像用レンズの製造方法
CN115036207A (zh) * 2022-06-28 2022-09-09 上海华力集成电路制造有限公司 改善晶圆尖端放电缺陷的方法

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