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WO2008007705A1 - Inducteur multicouche - Google Patents

Inducteur multicouche Download PDF

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Publication number
WO2008007705A1
WO2008007705A1 PCT/JP2007/063820 JP2007063820W WO2008007705A1 WO 2008007705 A1 WO2008007705 A1 WO 2008007705A1 JP 2007063820 W JP2007063820 W JP 2007063820W WO 2008007705 A1 WO2008007705 A1 WO 2008007705A1
Authority
WO
WIPO (PCT)
Prior art keywords
magnetic
electrically insulating
layer
pattern
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/063820
Other languages
English (en)
Japanese (ja)
Inventor
Kiyohisa Yamauchi
Makoto Kawaguchi
Kenji Okuda
Shinya Hitakatsu
Shigenori Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FDK Corp
Original Assignee
FDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FDK Corp filed Critical FDK Corp
Priority to KR1020097002211A priority Critical patent/KR101373243B1/ko
Publication of WO2008007705A1 publication Critical patent/WO2008007705A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F3/00—Cores, Yokes, or armatures
    • H01F3/10—Composite arrangements of magnetic circuits
    • H01F3/14—Constrictions; Gaps, e.g. air-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F37/00—Fixed inductances not covered by group H01F17/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/04—Fixed inductances of the signal type with magnetic core

Definitions

  • the present invention relates to a multilayer inductor having a structure in which a coil is embedded in a magnetic body. More specifically, the present invention relates to a case where one or more electrically insulating nonmagnetic layers are disposed over the entire multilayer surface.
  • the present invention relates to a multilayer inductor having a structure in which an electrically insulating nonmagnetic pattern corresponding to the shape of the conductor pattern is arranged between conductor patterns overlapping each other at close intervals. This multilayer inductor is particularly useful for inductors for DC-DC converters that require high bias.
  • Transformers and choke coils used in power circuits such as DC—DC converters have been generally configured with a coil wound around a magnetic core.
  • S small power circuit components in recent years
  • multilayer chip components In response to demands for reduction in thickness and thickness, multilayer chip components have been developed and put to practical use.
  • an electrically insulating magnetic layer and a conductor pattern are alternately stacked and the conductor patterns are sequentially connected to each other, so that a coil that wraps around in a spiral shape while being superimposed in the stacking direction in the magnetic body.
  • both ends of the coil are drawn to the outer surface of the laminated chip via lead conductors and connected to electrode terminals. That is, the coil is embedded in a chip-type magnetic body.
  • the magnetic layer and the conductor pattern are formed and stacked using, for example, a screen printing technique.
  • such a structure has a certain effect in suppressing the increase in AC resistance at the time of a low DC bias current and in reducing the deterioration of DC superposition characteristics.
  • the effects were not always sufficient, and problems such as a decrease in the effect as the number of coil turns increased were recognized.
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-45108
  • the problem to be solved by the present invention is to exhibit excellent DC superposition characteristics, to suppress AC resistance at low DC bias current, and to reduce inductance in the entire current region within the rated range. It is to obtain a high characteristic whose change is relatively gradual. Means for solving the problem
  • an electrically insulating magnetic layer and a conductor pattern are laminated and the conductor patterns are sequentially connected, thereby forming a coiner that circulates in a spiral shape while being superimposed in the lamination direction in the magnetic material.
  • a multilayer inductor in which both ends of the coil are respectively drawn out to the outer surface of the multilayer chip via lead conductors and connected to electrode terminals, one or more electrically insulating magnetic gap layers are arranged over the entire multilayer surface.
  • an electrically insulating nonmagnetic pattern corresponding to the shape of the conductor pattern is disposed between conductor patterns that overlap with each other at an interval.
  • the electrically insulating nonmagnetic pattern may have a shape that matches the conductor pattern, but is preferably a shape that is slightly larger or slightly smaller than the conductor pattern. In particular, it is more preferable to make the shape slightly larger than the conductor pattern.
  • the electrically insulating magnetic gap layer and the electrically insulating nonmagnetic pattern are arranged in the stacking direction. It is preferable to arrange them symmetrically with respect to the center.
  • the electrically insulating magnetic gap layer is a single layer, the magnetic gap layer is arranged in the center of the stacking direction, and the electrically insulating nonmagnetic pattern is symmetrically formed with respect to the center of the stacking direction.
  • the thickness of the electrically insulating magnetic gap layer can be set smaller than the interval between the conductor patterns that overlap each other.
  • the electrically insulating nonmagnetic pattern is preferably disposed between all the overlapping conductor patterns at intervals.
  • the multilayer inductor according to the present invention since one or more electrically insulating magnetic gap layers are disposed over the entire multilayer surface, the overall magnetic saturation level is increased, the DC superposition characteristics are increased, and the rated current (predetermined) Increase the current upper limit value that can guarantee the above inductance by the force S.
  • an electrically insulating nonmagnetic pattern corresponding to the shape of the conductor pattern is disposed between the conductor patterns that overlap with each other at an interval. The ability to prevent the occurrence of a micro-magnetization loop around the coil during DC bias current, so that there is no sudden flow of magnetic flux between conductor patterns, preventing sudden changes in inductance and suppressing the increase in AC resistance. Touch with S.
  • FIG. 1A is an explanatory view showing an example of a multilayer inductor according to the present invention.
  • FIG. 1B is an explanatory view showing an example of a multilayer inductor according to the present invention.
  • FIG. 1C is an explanatory view showing an embodiment of the multilayer inductor according to the present invention.
  • FIG. 1D is an explanatory view showing an embodiment of the multilayer inductor according to the present invention.
  • FIG. 2A is a longitudinal sectional view showing another embodiment of the present invention.
  • FIG. 2B is a longitudinal sectional view showing another embodiment of the present invention.
  • FIG. 3A is a graph showing a difference in DC superposition characteristics between the product of the present invention and a comparative example.
  • FIG. 3B is a graph showing a difference in DC superposition characteristics between the product of the present invention and a comparative example.
  • FIG. 4A is a graph showing a difference in frequency characteristics between the product of the present invention and a comparative example.
  • FIG. 4B is a graph showing a difference in frequency characteristics between the product of the present invention and a comparative example.
  • FIG. 4C is a graph showing a difference in frequency characteristics between the product of the present invention and a comparative example.
  • a decrease in inductance due to an increase in DC superimposed current is caused by an increase in DC current, an increase in coil force and a generated magnetic flux, and saturation of a magnetic material.
  • the sudden decrease in inductance and increase in AC resistance at low DC bias currents are caused by a small magnetization loop around the conductor pattern.
  • an electrically insulating magnetic gear layer is disposed over the entire multilayer surface, and the conductor pattern is formed in proximity to the conductor pattern between the conductor patterns that overlap with each other. Arranged almost insulative non-magnetic pattern of electrical insulation.
  • the electrically insulating magnetic gap layer is positioned at the center in the stacking direction, and the electrically insulating nonmagnetic pattern is disposed between all the conductor patterns overlapping each other at intervals.
  • FIG. 1A to 1D are explanatory views showing an embodiment of the multilayer inductor according to the present invention.
  • Fig. 1A shows the appearance
  • Fig. 1B shows the transparent state seen from the top of the conductor pattern
  • Fig. 1C shows the longitudinal section
  • Fig. 1D shows the structure of the conductor pattern and the nonmagnetic pattern.
  • This multilayer inductor 10 is a chip component for surface mounting that has a substantially rectangular parallelepiped shape, and a coil is embedded in a material that is mostly made of a magnetic material (eg, Ni—Zn ferrite material). Both ends of the coil are electrically connected to the electrode terminals 12 formed at both ends of the chip! (See Fig. 1A).
  • a magnetic material eg, Ni—Zn ferrite material
  • the internal coil structure is formed by printing and laminating a substantially annular (or semi-annular) conductor pattern 20 and an electrically insulating magnetic layer 22 by a screen printing method or the like.
  • the conductor pattern 20 is connected so as to circulate in a spiral shape while being superimposed in the stacking direction in the magnetic material of the magnetic layer 22 to form a coil.
  • the conductor pattern 20 is wound in a rectangular shape while being bent at a right angle, but may of course be a circle or an oval. Both ends of the coil are respectively drawn out to opposite end surfaces of the outer surface of the multilayer chip through lead conductors 24 and connected to the electrode terminals 12.
  • an electrical insulation is provided between the layer of the conductor pattern 20 that forms a part of the coil and another layer of the conductor pattern 20 that overlaps with a gap therebetween.
  • a non-magnetic material for example, Zn ferrite material.
  • One part is an electrically insulating magnetic gap layer 26 over the entire laminated surface, and the other part is a nonmagnetic pattern 28 (see FIG. 1D) that almost matches the shape of the conductor pattern. For example, print a non-magnetic pattern, remove the part, and print a shaped magnetic layer (the procedure may be reversed! /). Also, print the conductor pattern and print the magnetic layer excluding that part (the procedure may be reversed).
  • the upper and lower conductor patterns may be electrically connected using via holes or the like.
  • four conductor patterns 20 are provided, and the gap between the second layer and the third layer from the bottom is the magnetic gap layer 26 over the entire laminated surface, and from the bottom between the first layer and the second layer, A nonmagnetic pattern 28 is formed between the third layer and the fourth layer.
  • the boundary between the non-magnetic pattern 28 and the magnetic material is made slightly larger than the conductor pattern 20 to prevent the occurrence of a short circuit due to the inflow of the conductor paste. It is preferable to set it so that it can be placed on the magnetic layer with a sufficient force on the magnetic layer.
  • the multilayer inductor having the structure of the present invention can satisfy the required specifications with a relatively small amount of coil and the number of coil turns in applications such as a DC-DC converter. Magnetic gap layer and The position where the nonmagnetic pattern is inserted is appropriately determined according to the coil shape, the number of turns, and the like.
  • FIG. 2A and FIG. 2B show another embodiment of the multilayer inductor according to the present invention.
  • FIG. 2A shows an example in which the thickness of the electrically insulating magnetic gap layer 26 is set smaller than the interval between the conductor patterns 20 that overlap each other. Since the basic configuration is the same as that shown in FIGS. 1A to 1D, the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the interval between the conductive patterns 20 that overlap with each other at an interval in the vertical direction is usually required to be about 15 111 for ensuring electric insulation.
  • the thickness of the magnetic gap layer 26 is set to a desired size (for example, about 7.5 ⁇ 111), and a thin non-magnetic pattern is formed with a difference from the distance between the conductor patterns 20 (here, 7.5 m). It is additionally arranged (in this example, it may be provided on the lower side of the force provided above the magnetic gap layer, or may be provided equally on both upper and lower sides). As a result, the gap between the conductor patterns 20 without worrying about the short circuit of the coil is set to a size that can sufficiently ensure electrical insulation, and the magnetic gap layer 26 can be set to a desired thickness. it can.
  • a desired size for example, about 7.5 ⁇ 111
  • a thin non-magnetic pattern is formed with a difference from the distance between the conductor patterns 20 (here, 7.5 m). It is additionally arranged (in this example, it may be provided on the lower side of the force provided above the magnetic gap layer, or may be provided equally on both upper and lower sides).
  • FIG. 2B is a modification of the multilayer inductor shown in FIG. 2A, and this is also basically the same configuration as that shown in FIG. Detailed description is omitted.
  • six layers of conductor patterns 20 forming a part of the coil are laminated so as to overlap each other with a gap therebetween.
  • the region between the conductor patterns 20 is entirely composed of an electrically insulating nonmagnetic material, and an electrically insulating magnetic gap layer 26 is provided over a part of the laminated surface (two locations in this case).
  • Nonmagnetic patterns 28 are formed between the third layer and the fourth layer, and between the fifth layer and the sixth layer.
  • the thickness of the magnetic gap layer 26 is set to be thin (for example, about 7.5 m), and a nonmagnetic pattern having a thickness different from the conductor pattern interval (here, 7.5 m) is additionally arranged. Yes.
  • the number of conductor patterns forming a coil can be increased or decreased according to required specifications, and the number of magnetic gap layers, the thickness of magnetic gap layers, and the layers of nonmagnetic patterns.
  • the number and the like can be changed as appropriate.
  • examples of magnetic materials include For example, Ni-Zn ferrite can be used.
  • a nonmagnetic material for forming a magnetic gap layer or a nonmagnetic pattern for example, Zn ferrite can be used.
  • FIGS. 3A, 3B, and 4A to 4C Examples of measurement results are shown in FIGS. 3A, 3B, and 4A to 4C.
  • the product of the present invention has the same structure as that of the multilayer inductor shown in FIGS. 1A to 1D, and a single electrically insulating magnetic gap layer is formed in the center over the entire multilayer surface, with an interval.
  • electrically insulating non-magnetic patterns are arranged between all overlapping conductor patterns.
  • the comparative example has a structure in which only one electrically insulating magnetic gap layer is formed in the center over the entire laminated surface! (No electrical insulating nonmagnetic pattern). In all cases, the conductor pattern is 4 layers, and a 4.5-turn coil is formed!
  • FIG. 3A and 3B show the DC bias current characteristics.
  • Fig. 3A shows the change in inductance.
  • the product of the present invention can maintain a relatively high inductance up to high current, and the inductance can be maintained even if the DC current changes. It can be seen that there is little change in.
  • Fig. 3B shows the change in AC resistance.
  • the product of the present invention has a particularly low change in AC resistance even when the DC current changes with a low AC resistance. I understand that.
  • an electrically insulating magnetic gap layer is formed over the entire laminated surface, and an electrically insulating nonmagnetic pattern is formed between conductor patterns that overlap with each other at an interval. It can be seen that the DC superimposition characteristics can be improved and the AC resistance at low DC bias current can be reduced by arranging the.
  • FIG. 4A to 4C show frequency characteristics.
  • Fig. 4A shows the Q value
  • Fig. 4B shows the inductance
  • Fig. 4C shows the AC characteristics.
  • the product of the present invention has a higher Q value and lower AC resistance. Although the inductance is slightly low, it can be made almost constant regardless of the frequency.
  • the operating frequency of DC-DC converters is expected to be about 1 to 3 MHz, and is expected to increase in the future (eg, approaching 10 MHz). Since the product of the present invention has good high frequency characteristics, it is considered that the present invention becomes more useful as the frequency increases.
  • the number of coil turns can be appropriately increased or decreased according to the required specifications. However, the number of coil turns If the number is excessively large, the number of manufacturing steps increases and the cost also increases.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

La présente invention concerne un inducteur multicouche capable de présenter une excellente caractéristique de superposition de courant continu et de suppression de résistance de courant alternatif lors d'une faible circulation de courant de polarisation cc ainsi qu'une caractéristique élevée qu'un changement d'inductance s'opère de manière souple dans toute la zone de courant où le courant de bobine se trouve dans une plage nominale. L'inducteur multicouche selon l'invention (10) comporte une couche magnétique d'isolation électrique (22) et une impression conductrice (20) qui sont superposées de sorte que les couches conductrices soient connectées successivement pour former une bobine enroulée en spirale tout en étant superposée dans la direction de superposition dans le corps magnétique. Chacune des deux extrémités de la bobine est tirée hors de la surface extérieure de la puce de corps superposée via un conducteur escamotable (24) et connectée à une borne d'électrode (12). Au moins une couche (26) de l'entrefer magnétique isolant est disposée sur toute la surface multicouche. Une impression non magnétique d'isolation électrique (28) correspondant à la forme de l'impression conductrice est disposée à proximité de l'impression conductrice entre les impressions conductrices superposées avec un entrefer.
PCT/JP2007/063820 2006-07-12 2007-07-11 Inducteur multicouche Ceased WO2008007705A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020097002211A KR101373243B1 (ko) 2006-07-12 2007-07-11 적층 인덕터

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-191611 2006-07-12
JP2006191611A JP5339398B2 (ja) 2006-07-12 2006-07-12 積層インダクタ

Publications (1)

Publication Number Publication Date
WO2008007705A1 true WO2008007705A1 (fr) 2008-01-17

Family

ID=38923261

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/063820 Ceased WO2008007705A1 (fr) 2006-07-12 2007-07-11 Inducteur multicouche

Country Status (3)

Country Link
JP (1) JP5339398B2 (fr)
KR (1) KR101373243B1 (fr)
WO (1) WO2008007705A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010067758A (ja) * 2008-09-10 2010-03-25 Murata Mfg Co Ltd 電子部品
CN104810131A (zh) * 2014-01-27 2015-07-29 三星电机株式会社 片式电子组件及其制造方法
CN107871585A (zh) * 2016-09-26 2018-04-03 株式会社村田制作所 电子部件

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5193845B2 (ja) * 2008-12-25 2013-05-08 Ｆｄｋ株式会社 積層インダクタ
JP5193844B2 (ja) * 2008-12-25 2013-05-08 Ｆｄｋ株式会社 積層インダクタ
JP5193843B2 (ja) * 2008-12-25 2013-05-08 Ｆｄｋ株式会社 積層インダクタ
JP4929483B2 (ja) 2009-07-08 2012-05-09 株式会社村田製作所 電子部品及びその製造方法
KR101214731B1 (ko) * 2011-07-29 2012-12-21 삼성전기주식회사 적층형 인덕터 및 이의 제조 방법
KR101332100B1 (ko) 2011-12-28 2013-11-21 삼성전기주식회사 적층형 인덕터
KR101367952B1 (ko) 2012-05-30 2014-02-28 삼성전기주식회사 적층형 전자부품용 비자성체 조성물, 이를 이용한 적층형 전자부품 및 이의 제조방법
JP5816145B2 (ja) * 2012-09-06 2015-11-18 東光株式会社 積層型インダクタ
KR101420525B1 (ko) * 2012-11-23 2014-07-16 삼성전기주식회사 적층형 인덕터 및 이의 제조방법
JP6569451B2 (ja) * 2015-10-08 2019-09-04 Tdk株式会社 積層コイル部品
JP7077835B2 (ja) * 2018-07-17 2022-05-31 株式会社村田製作所 インダクタ部品

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JPH0677022A (ja) * 1992-03-31 1994-03-18 Tdk Corp 複合積層部品用非磁性フェライトおよび複合積層部品
JPH06224043A (ja) * 1993-01-27 1994-08-12 Taiyo Yuden Co Ltd 積層チップトランスとその製造方法
WO2002056322A1 (fr) * 2001-01-15 2002-07-18 Matsushita Electric Industrial Co., Ltd. Filtre antiparasite et appareil electronique comprenant ledit filtre
WO2005010901A2 (fr) * 2003-07-24 2005-02-03 Fdk Corporation Bobine d'inductance stratifiee du type noyau
JP2005268455A (ja) * 2004-03-17 2005-09-29 Murata Mfg Co Ltd 積層型電子部品

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JPH1092645A (ja) * 1996-09-18 1998-04-10 Tokin Corp 積層型インピーダンス素子
JP3245835B2 (ja) * 1998-07-13 2002-01-15 株式会社村田製作所 積層型インダクタの製造方法
JP2000216024A (ja) * 2000-01-01 2000-08-04 Murata Mfg Co Ltd 積層型インダクタ
JP2005136037A (ja) * 2003-10-29 2005-05-26 Sumida Corporation 積層トランス

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677022A (ja) * 1992-03-31 1994-03-18 Tdk Corp 複合積層部品用非磁性フェライトおよび複合積層部品
JPH06224043A (ja) * 1993-01-27 1994-08-12 Taiyo Yuden Co Ltd 積層チップトランスとその製造方法
WO2002056322A1 (fr) * 2001-01-15 2002-07-18 Matsushita Electric Industrial Co., Ltd. Filtre antiparasite et appareil electronique comprenant ledit filtre
WO2005010901A2 (fr) * 2003-07-24 2005-02-03 Fdk Corporation Bobine d'inductance stratifiee du type noyau
JP2005268455A (ja) * 2004-03-17 2005-09-29 Murata Mfg Co Ltd 積層型電子部品

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010067758A (ja) * 2008-09-10 2010-03-25 Murata Mfg Co Ltd 電子部品
CN104810131A (zh) * 2014-01-27 2015-07-29 三星电机株式会社 片式电子组件及其制造方法
CN107871585A (zh) * 2016-09-26 2018-04-03 株式会社村田制作所 电子部件
CN107871585B (zh) * 2016-09-26 2020-04-10 株式会社村田制作所 电子部件

Also Published As

Publication number Publication date
KR101373243B1 (ko) 2014-03-12
JP2008021788A (ja) 2008-01-31
KR20090033378A (ko) 2009-04-02
JP5339398B2 (ja) 2013-11-13

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