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WO2007119442A1 - Transistor organique à mobilité de charge améliorée et son procédé de fabrication - Google Patents

Transistor organique à mobilité de charge améliorée et son procédé de fabrication Download PDF

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Publication number
WO2007119442A1
WO2007119442A1 PCT/JP2007/055625 JP2007055625W WO2007119442A1 WO 2007119442 A1 WO2007119442 A1 WO 2007119442A1 JP 2007055625 W JP2007055625 W JP 2007055625W WO 2007119442 A1 WO2007119442 A1 WO 2007119442A1
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drain electrode
organic
source electrode
electrode
layer
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Japanese (ja)
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Masaaki Kurita
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Brother Industries Ltd
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Brother Industries Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited

Definitions

  • the present invention relates to an organic transistor having improved charge mobility and a method for manufacturing the same, and more particularly to a bottom contact type organic transistor and a method for manufacturing the same.
  • each pixel of this flexible display has an active drive circuit equipped with a thin film transistor (TFT). Embedded.
  • TFT thin film transistor
  • an organic thin film transistor using an organic semiconductor can be produced at room temperature and can be formed on a flexible plastic substrate at a low cost, so that its general purpose is expected.
  • Organic semiconductor materials used for such organic thin film transistors are generally known to have inferior chemical resistance and heat resistance compared to inorganic semiconductors, but source / drain electrodes formed in organic thin film transistors
  • the insulating film is formed by a high-temperature process, wet etching, or a coating process. For this reason, in an organic thin film transistor in which an organic semiconductor, a metal for an electrode, and an organic material such as an insulating film are mixed, the organic semiconductor film may be deteriorated in the process of forming each layer. From such a viewpoint, as shown in FIG.
  • the organic thin film transistor 101 includes a gate electrode 106, a gate insulating layer 105, a source electrode 103, and a drain electrode 104 formed on an insulating substrate 102, and then an organic semiconductor layer.
  • the so-called “bottom contact structure” in which 109 is formed is said to be suitable.
  • an organic semiconductor layer 109 between the source electrode 103 and the drain electrode 104 is defined as a channel region.
  • the organic semiconductor layer 109 is formed of an organic material that grows in a polycrystalline manner such as pentacene, the size of the semiconductor crystal is smaller than that of the source electrode 103 or the drain electrode 104. On the surface, it is one or more orders of magnitude smaller than on the surface of the gate insulating layer 105. As a result, as shown in FIG. 2, a large number of crystal grains are formed in the channel region near the boundary between the source electrode 103 or the drain electrode 104 and the organic semiconductor layer 109. There was a problem in that the contact resistance at the source electrode / semiconductor interface or the drain electrode / semiconductor interface increased due to the presence of the boundary.
  • a semiconductor device and a manufacturing method thereof are known in which the taper width in the channel length direction of the source electrode or drain electrode is made shorter than the average grain size of the semiconductor crystal grown on the surface of the source electrode or drain electrode.
  • the “channel length” in FIG. 1 is defined as the middle position of the end surface of the source electrode 103 in the thickness direction and the distance to the middle position of the end surface of the drain electrode 104 in the thickness direction.
  • a perpendicular line is drawn from the channel side end of the upper surface of the drain electrode 104 to the substrate 102, and the lower surface of the source electrode 103 or the drain electrode 104 from the intersection of the force and the vertical line with the lower surface of the source electrode 103 or the drain electrode 104. It is defined as the distance to the end of the channel side.
  • the taper width when the taper width is long, a semiconductor that forms a channel in contact with a region on the channel side of the source electrode 103 or the drain electrode 104 that is 1 Onm or less in height from the gate insulating layer 105 Part of the crystal grows from the nucleus on the electrode. That is, in the vicinity of the source electrode 103 or the drain electrode 104, the number of crystal grain boundaries that trap carriers increases, so that the contact resistance at the source electrode semiconductor interface or the drain electrode / semiconductor interface is smaller than that of a thin film transistor with a short taper width. Contact resistance increases.
  • the taper width is shorter than the average grain size of the semiconductor crystal on the source electrode or the drain electrode, the height from the gate insulating film (layer) is in contact with the region of 10 nm or less.
  • Organic semiconductor crystals can be grown from nuclei on the gate insulating film (layer). As a result, the contact resistance of the source electrode 'semiconductor interface and the contact resistance of the drain electrode' semiconductor interface can be lowered, so that the charge mobility in the organic semiconductor layer can be improved.
  • Patent Document 1 JP 2005-93542 A
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide an organic thin film transistor having improved charge mobility related to the shape of the source electrode or the drain electrode, and a method for manufacturing the same.
  • an organic transistor according to claim 1 includes a substrate, a gate electrode formed on the substrate, and a gate formed on the substrate so as to cover the gate electrode.
  • An insulating layer, a source electrode and a drain electrode formed on the gate insulating layer and spaced apart from each other, and formed between the source electrode and the drain electrode, the source electrode and the drain electrode A layered flat member for flattening with a gap between and an organic semiconductor layer formed on the surface of the source electrode and the surface of the drain electrode so as to cover the flattening member
  • the organic transistor according to claim 2 is the organic transistor according to claim 1, wherein the flat member is a resin made of an organic substance.
  • the organic transistor according to claim 3 is the organic transistor according to claim 1, wherein the planarizing member is an inorganic material, and the surface of the planarizing member that faces the gate insulating layer is provided. A self-assembled film is formed on the opposite surface.
  • the organic transistor according to claim 4 is the organic transistor according to claim 1, wherein the relative dielectric constant of the gate insulating layer is 4 or more.
  • the method of manufacturing an organic transistor according to claim 5 includes a gate electrode forming step of forming a gate electrode on the substrate, and an insulating process of forming a gate insulating layer on the substrate so as to cover the gate electrode. Forming a layer, and forming a source electrode and a drain electrode on the gate insulating layer. A source and drain electrode forming step in which poles are formed apart from each other, and a layered state formed between the source electrode and the drain electrode and flattened between the source electrode and the drain electrode. A planarizing member forming step for forming the planarizing member, and an organic semiconductor layer forming step for forming an organic semiconductor layer on the surface of the source electrode and the drain electrode so as to cover the planarizing member. It is characterized by that.
  • the manufacturing method of the organic transistor according to claim 6 is the manufacturing method of the organic transistor according to claim 5, wherein the planarizing member is a resin made of an organic substance, A flattening step of flattening the member by an ashing method using oxygen plasma is provided, and the surfaces of the source electrode and the drain electrode are exposed from the flattening member.
  • the planarizing member is a resin made of an organic substance
  • the method for producing an organic transistor according to claim 7 is the method for producing an organic transistor according to claim 5, wherein the planarizing member is a resin made of an organic substance.
  • the method for producing an organic transistor according to claim 8 is the method for producing an organic transistor according to claim 5, wherein in the step of forming the flat member, the flat member is formed by an inkjet method. By the above, it is formed between the source electrode and the drain electrode.
  • the manufacturing method of the organic transistor according to claim 9 is the manufacturing method of the organic transistor according to claim 5, wherein, in the flat member forming step, the flat member is formed by spin coating. It is formed between the source electrode and the drain electrode by a method.
  • the manufacturing method of the organic transistor according to claim 10 is the manufacturing method of the organic transistor according to claim 5, wherein in the flat member forming step, the planarizing member is formed by a dip coating method. In this case, the drain electrode is formed between the source electrode and the drain electrode.
  • the surface of the source electrode and the drain electrode which is located on the opposite side of the substrate with the flattening member between the source electrode and the drain electrode, The surface of the flattening member is flush. Therefore, since the surface on which the organic semiconductor layer is formed becomes substantially smooth, the orientation of crystal growth of the organic semiconductor layer is determined by any one of the source electrode, the drain electrode, and the planarizing member, or the interface thereof. And the generation of a large number of grain boundaries can be suppressed. As a result, both the contact resistance at the interface between the source electrode and the organic semiconductor layer and the contact resistance at the interface between the drain electrode and the organic semiconductor layer can be lowered, and the charge mobility can be improved. In addition, since it is not necessary to process the shapes of the source electrode and the drain electrode themselves before forming the organic semiconductor layer, the manufacturing cost of the organic transistor can be suppressed.
  • the flat member is a resin made of an organic material, it can assist the orientation of crystal growth of the organic semiconductor layer. Further, since the flat plate member can be formed on the substrate at normal pressure and normal temperature, an organic transistor can be manufactured at low cost without requiring an expensive vacuum device or the like.
  • the self-assembled film is formed on the surface of the flat plate member on the side opposite to the substrate. Since the organic semiconductor is bonded to the organic functional group of the film, it is possible to align the crystal growth orientation of the organic semiconductor layer formed on the self-assembled film. Further, since the self-assembled film is stably formed on the surface of the planarizing member, the organic semiconductor layer formed via the self-assembled film can be stably formed on the surface of the flattened member.
  • the gate electrode By applying a voltage to the source electrode, it is possible to reliably form a directivity channel on the drain electrode through the gate insulating layer.
  • the flat member is a resin made of an organic substance
  • the film thickness of the flat member can be adjusted by an ashing method using oxygen plasma, and the source can be easily obtained.
  • the drain electrode, the drain electrode, and the flat plate member can be flush with each other. In other words, the surface on which the organic semiconductor layer is formed can be flattened to align the crystal growth orientation of the organic semiconductor layer.
  • the flat member is a resin made of an organic material
  • the film thickness of the flat member can be adjusted by a polishing method, and the source electrode, drain electrode, and The planarizing member can be flush. That is, the surface on which the organic semiconductor layer is formed can be flattened to align the crystal growth orientation of the organic semiconductor layer.
  • the flat member is formed by directly dropping between the source electrode and the drain electrode by the ink jet method, so that the dropped flat member is not wasted.
  • a planarizing member can be formed. As a result, the material cost for the flat member can be saved, and the number of steps for forming the flat member can be reduced.
  • the flat member can be formed by spin coating, the thickness of the flat member can be formed with high accuracy.
  • the flat member can be formed by the dip coating method, the number of steps of the flat member forming process can be reduced.
  • FIG. 1 is a cross-sectional view of a conventional organic thin film transistor.
  • FIG. 2 is a diagram for explaining a crystal arrangement of an organic semiconductor layer in the vicinity of a channel of a drain electrode of a conventional organic thin film transistor.
  • FIG. 3 is a cross-sectional view illustrating an organic thin film transistor of the present invention.
  • FIG. 4 is a cross-sectional view for explaining the crystal state of the organic semiconductor layer 4 formed on the flat layer and the drain electrode of the organic thin film transistor shown in FIG. 3.
  • FIG. 5 is a flowchart for explaining a method for producing an organic thin film transistor of the present invention.
  • FIG. 6 is a cross-sectional view of a substrate constituting the organic thin film transistor of the present invention.
  • FIG. 7 is a cross-sectional view showing a state where a gate electrode is formed on the substrate shown in FIG.
  • FIG. 8 is a cross-sectional view showing a state where a gate insulating layer is formed on the substrate shown in FIG.
  • FIG. 9 is a cross-sectional view showing a state where a source electrode and a drain electrode are formed on the gate insulating layer shown in FIG.
  • FIG. 10 is a cross-sectional view showing a state in which a flat layer is formed on the source electrode and the drain electrode shown in FIG.
  • FIG. 11 is a cross-sectional view showing a state in which the planarizing layer is flush with the source electrode and the drain electrode by reducing the film thickness of the planarizing layer shown in FIG.
  • An organic thin film transistor 1 shown in FIG. 3 is a bottom contact type, and includes a substrate 2 made of an insulating material such as glass or plastic.
  • the material for forming the substrate 2 include polyethersulfone (PES), polyethylene terephthalate (PET), polyimide (PI), and polyethylene naphthalate (PEN).
  • PES polyethersulfone
  • PET polyethylene terephthalate
  • PI polyimide
  • PEN polyethylene naphthalate
  • the gate electrode 3 is formed on the upper surface of the substrate 2.
  • conductive polymers such as poly 3,4-ethylenedioxythiophene (PEDOT) can be used.
  • PEDOT is a conductive polymer made by polymerizing 3,4-ethylenedioxythiophene) in high molecular weight polystyrene sulfonic acid.
  • a gate insulating layer 4 is formed on the upper surface of the substrate 2 so as to cover the gate electrode 3.
  • this gate insulating layer 4 is made of an inorganic insulating film, Al ⁇ , Si ⁇ , SiN, etc.
  • the gate insulating layer 4 is formed so that the relative dielectric constant is 4 or more.
  • the relative dielectric constant is the ratio of the dielectric constant of a material to the vacuum dielectric constant.
  • the source electrode 5 and the drain electrode 6 are formed on the upper surface of the gate insulating layer 4 with a predetermined separation width, respectively.
  • the source electrode 5 and the drain electrode 6 are made of conductive polymers such as polyimide (PI), polymethyl methacrylate (PMMA), polyparabutanol (PVP), or PEDOT in addition to metals such as Al, Mo, Au, and Cr. Ranaru.
  • a distance between the source electrode 5 and the drain electrode 6 is defined as a channel length.
  • the channel length is defined as the distance from the middle position in the thickness direction of the end face of the drain electrode 6 to the middle position in the thickness direction of the end face of the drain electrode 6.
  • the flat layer 7 is formed between the source electrode 5 and the drain electrode 6 so as to support a groove formed between the source electrode 5 and the drain electrode 6.
  • the flat layer 7 is made of a resin made of an organic material, and is made of polyimide (PI), polymethylmetatalylate (PMMA), polyparavinylphenol (PVP), or the like.
  • the flat layer 7 covers both the channel side surface of the source electrode 5 and the channel side surface of the drain electrode 6, and a groove between the source electrode 5 and the drain electrode 6 is formed in the flat layer 7. Is flattened. As a result, the corners where the channel-side side surfaces of the source electrode 5 and the drain electrode 6 intersect with the respective upper surfaces can be flush with the flat layer 7.
  • the flat layer 7 is made of an inorganic material such as SiO 2 or SiN.
  • SAM film 15 a self-assembled film 15 on the surface of the flat layer 7.
  • SAM film self-assembled film
  • the organic semiconductor layer 8 is formed on the surfaces of the source electrode 5 and the drain electrode 6 so as to cover the surface of the planarization layer 7.
  • the organic semiconductor layer 8 is disposed so as to face the gate electrode 3 with the gate insulating layer 4 interposed therebetween.
  • the organic semiconductor layer 8 is formed of a low molecular semiconductor material or a polymer semiconductor material.
  • Small molecule semiconductor materials examples thereof include condensed aromatic hydrocarbons such as tetracene, taricene, pentacene, pyrene, perylene, coronene, and derivatives thereof, and metal complexes of porphyrin and phthalocyanine compounds such as copper phthalocyanine and lutetium bisphthalocyanine.
  • polymer semiconductor materials include poly (3-hexylthiophene) (P3HT) and polyparaphenylenevinylene (PPV).
  • the groove between the source electrode 5 and the drain electrode 6 is flattened by being supported by the flattening layer 7, and the surface of the source electrode 5 and the drain electrode 6 are formed. Are formed flush with the surface of the flat layer 7. That is, the portion where the organic semiconductor layer 8 is in contact with the source electrode 5 and the portion where the organic semiconductor layer 8 is in contact with the drain electrode 6 can both be planar. Further, since the flat layer 7 is made of an organic resin, the direction of the crystal growth of the semiconductor crystal of the organic semiconductor layer 8 on the surface of the flat layer 7 can be aligned as shown in FIG. And the orientation of the semiconductor crystal of the organic semiconductor layer 8 can be improved.
  • the surface of the planarizing layer 7 grows larger than the semiconductor crystal force of the organic semiconductor layer 8.
  • the orientation of the organic semiconductor crystal constituting the organic semiconductor layer 8 is improved, the interface between the source electrode 5 and the organic semiconductor layer 8 and the interface between the drain electrode 6 and the organic semiconductor layer 8 are improved.
  • Each contact resistance can be reduced. That is, charge mobility can be improved.
  • the gate insulating layer 4 is formed so that the relative dielectric constant is 4 or more.
  • the gate insulating layer If 4 is formed so as to have a relative dielectric constant of 4 or more, when a voltage is applied to the gate electrode 3, it is possible to secure a direction force and a high channel from the source electrode 3 to the drain electrode 4 through the gate insulating layer 4. .
  • the manufacturing method of the organic thin film transistor 1 includes a gate electrode forming step (S1) for forming the gate electrode 3 on the upper surface of the substrate 2, and a cover for covering the gate electrode 3 on the upper surface of the substrate 2.
  • a flattening layer forming step (S4) in which a flattening resin is buried in the groove between the source electrode 5 and the drain electrode 6 to form the flattening layer 7, and the source so as to cover the flattening layer 7 is covered.
  • Example 1 a manufacturing method of the organic thin film transistor 1 in which the flat layer is made of PMMA will be described.
  • the gate electrode formation step S1 is performed.
  • the substrate 2 is sufficiently cleaned as shown in FIG.
  • the substrate 2 is degassed, and a gate electrode 3 made of A1 is formed on the substrate 2 by mask vapor deposition as shown in FIG.
  • the conditions of the mask deposition at this time, the vacuum degree is 3 X 10 _4 Pa, the substrate 2 is heated Shinare. In this way, the gate electrode 3 having a thickness of 60 nm is formed on the upper surface of the substrate 2.
  • a gate insulating layer forming step S2 is performed.
  • a gate insulating layer 4 having a polyimide (PI) force is formed on the upper surface of the substrate 2 on which the gate electrode 3 is formed by spin coating.
  • a 5 wt% polyimide solution of high heat resistant polyimide resin manufactured by Kyocera Chemical Co., Ltd .: trade name “CT4112”
  • CT4112 trade name of high heat resistant polyimide resin
  • a source / drain electrode formation step S3 is performed.
  • a source electrode 5 and a drain electrode 6 made of Au are formed on the surface of the gate insulating layer 4 by mask vapor deposition.
  • the conditions of the mask vapor deposition at this time are as follows: the degree of vacuum is 3 ⁇ 10 — 4 Pa, and heating of the substrate 2 is unnecessary.
  • the source electrode 5 and the drain electrode 6 each having a thickness of lOOnm can be formed on the surface of the gate insulating layer 4.
  • a planarization layer forming step S4 is performed.
  • a planarization layer 7 made of PMMA is formed by spin coating on the surface of the gate insulating layer 4 on which the source electrode 5 and the drain electrode 6 are formed.
  • the surface of the gate insulating layer 4, the source electrode 5 and the drain electrode 6 provided on the substrate 2 is coated with 5 wt% xylene of PM MA (Mitsubishi Chemical Corporation: trade name “Ataripet”). Applied the solution Later, the substrate 2 is rotated horizontally. Thereafter, the planarization layer 7 having a thickness of 200 nm is formed by drying at 110 ° C. for one hour.
  • the merit of the spin coating method is that the film thickness of the planarizing layer 7 can be easily controlled precisely.
  • the planarizing layer 7 is decomposed with oxygen plasma from its surface using a known ashing device, thereby reducing the thickness of the planarizing layer 7 by lOOnm.
  • the planarization layer 7 formed on the surfaces of the source electrode 5 and the drain electrode 6 can be removed. Therefore, the surface of the source electrode 5 and the drain electrode 6 and the surface of the planarization layer 7 can be flush with each other, and the planarization layer 7 can provide a gap between the source electrode 5 and the gate insulating layer between the drain electrode 6. Can be flat.
  • the merit of the ashing method using oxygen plasma is that the planarization layer 7 can be processed in a short time.
  • the treatment of the planarizing layer 7 can also be performed by a polishing method that is not limited to the ashing method.
  • the merit of the polishing method is that the film thickness of the planarizing layer 7 can be easily controlled.
  • the policing method is performed by a known policing apparatus.
  • an organic semiconductor layer forming step S5 is performed.
  • pentacene manufactured by Aldrich
  • This vacuum deposition is performed by a well-known vacuum deposition apparatus, and pentacene is sublimated in a vacuum space to form the organic semiconductor layer 8 on the surface of the planarizing layer 7, the source electrode 5, and the drain electrode 6.
  • the vacuum deposition conditions at this time are as follows: the degree of vacuum is 8 ⁇ 10 _5 Pa, and the substrate 2 is heated to a temperature of 60 ° C. In this manner, the organic semiconductor layer 8 having a thickness of 60 nm is formed on the surfaces of the source electrode 5, the drain electrode 6, and the planarizing layer 7.
  • the organic thin film transistor 1 shown in FIG. 3 is manufactured through the above-described forming steps including S1 to S5.
  • the organic thin film transistor 1 includes, for example, a flat layer 7 in the groove between the source electrode 5 and the drain electrode 6 to make the space between the source electrode 5 and the drain electrode 6 flat, for example, As shown in FIG. 4, the step between the surface 7A of the planarizing layer 7 and the surface 6A of the drain electrode 6 is eliminated, and the orientation of the semiconductor crystals of the organic semiconductor layer 8 can be made uniform. Similarly, there is no step between the surface 7A of the flat layer 7 and the surface of the source electrode 5, and the orientation of the semiconductor crystal of the organic semiconductor layer 8 can be made uniform. Therefore, charge Mobility can be improved.
  • the planarization layer 7 of the organic thin film transistor 1 of Example 1 is made of PMMA.
  • two samples were prepared: 1. an organic thin film transistor without the flat layer 7, and 2. an organic thin film transistor with the flat layer 7.
  • the mobility and threshold voltage of each organic thin film transistor Each was measured and compared.
  • FIG. 12 shows the mobility of each organic thin film transistor.
  • the organic thin film transistor without the planarization layer 7 had a mobility of 0.15 cm 2 / Vs, whereas the organic thin film transistor with the planarization layer 7 had a mobility of 0.45 cm 2 / Vs. Met.
  • the threshold voltage was 15 V for the organic thin film transistor without the flattening layer 7, whereas it was 5 V for the organic thin film transistor with the flattening layer 7.
  • the mobility of the organic thin film transistor having the flat layer 7 made of PMMA was three times as large as that of the organic thin film transistor having no flat layer 7. It was done.
  • the source electrode 5 and the drain electrode 6 are flush with the flattening layer 7, and the organic semiconductor layer to be formed next 8 is an organic semiconductor crystal that grows as an organic semiconductor layer 8 because it is formed on the source electrode 5, drain electrode 6, and planarization layer 7 whose upper surfaces are flush with each other, that is, on a flat surface. Can be aligned. Therefore, since the generation of crystal grain boundaries can be suppressed, the contact resistances at the interface between the source electrode 5 and the organic semiconductor layer 8 and the interface between the drain electrode 6 and the organic semiconductor layer 8 can be reduced, respectively. Mobility can be improved.
  • the threshold voltage of the organic thin film transistor having the planarizing layer 7 was greatly reduced as compared with the threshold voltage of the organic thin film transistor not having the planarizing layer 7.
  • Example 2 a method for manufacturing the organic thin film transistor 1 having the flat film layer 7 made of PVP will be described.
  • the forming steps S1 to S5 shown in FIG. 5 from the gate electrode forming step S1 to the gate insulating layer forming step S2 and the source / drain electrode forming step S3. Since this is the same as that of Example 1, the description of each forming process from S1 to S3 will be omitted, and only each forming process after S4 will be described.
  • the PVP that forms the planarizing layer 7 is a homopolymer of parabiphenol, and has a high molecular weight and excellent reactivity and stability as compared with a condensed phenol resin having a similar structure.
  • the planarization layer forming step S4 the surface of the gate insulating layer 4 on which the source electrode 5 and the drain electrode 6 are formed is applied to the planarization layer made of PVP by spin coating as shown in FIG. 7 is formed.
  • IPA isopropyl alcohol
  • PVP manufactured by Maruzen Petrochemical Co., Ltd .: trade name “Marcarinkaichi”
  • the planarization layer 7 having a thickness of 200 nm is formed by drying at 110 ° C. for one hour.
  • planarization layer 7 is decomposed by oxygen plasma using an ashing device to reduce the film thickness by lOOnm. Thereby, the flat layer 7 formed on the source electrode 5 and the drain electrode 6 can be removed, and the surface of the source electrode 5 and the drain electrode 6 and the surface of the flat layer 7 are faced. Can be one.
  • an organic semiconductor layer forming step S5 is performed.
  • a polymer semiconductor P3HT manufactured by Aldrich
  • P3HT manufactured by Aldrich
  • the organic semiconductor layer 8 is formed on the surface of the planarizing layer 7, the source electrode 5, and the drain electrode 6 by drying in a vacuum oven at 110 ° C. for one hour.
  • the planarization layer 7 of the organic thin film transistor 1 of Example 2 is made of PVP.
  • two samples were prepared: 1. an organic thin film transistor having no flattened layer 7, and 2. an organic thin film transistor having a flattened layer 7.
  • a comparative study was conducted by measuring the mobility and threshold voltage of thin film transistors.
  • the mobility of the organic thin film transistor without the flat layer 7 was 0.0 012 cm 2 ZVs, whereas the organic thin film transistor with the flat layer 7 was , 0. It was 0041 cm 2 / Vs.
  • the threshold voltage was 15 V in the organic thin film transistor not having the flattening layer 7, whereas it was 14 V in the organic thin film transistor having the flattening layer 7.
  • the mobility of the organic thin film transistor having the flat layer 7 made of PVP was improved by about 3 times compared to the organic thin film transistor having no flat layer 7. It has been certified. That is, in the same manner as in Example 1, the flat layer 7 is provided in the groove between the source electrode 5 and the drain electrode 6 and the flat between the source electrode 5 and the drain electrode 6 The organic semiconductor layer 8 is formed on the source electrode 5, the drain electrode 6, and the planarization layer 7 whose upper surfaces are flush with each other, that is, the flat surface is formed on the plane, so that the organic semiconductor constituting the organic semiconductor layer 8 The crystal orientation can be aligned. Therefore, the generation of crystal grain boundaries can be suppressed, so that the contact resistance at the interface between the source electrode 5 and the organic semiconductor layer 8 and the interface between the drain electrode 6 and the organic semiconductor layer 8 can be reduced. Mobility can be improved.
  • the threshold voltage of the organic thin film transistor having the planarizing layer 7 hardly changed compared to the threshold voltage of the organic thin film transistor not having the planarizing layer 7.
  • the organic thin film transistor 1 according to the first embodiment is of a bottom contact type, and the groove between the source electrode 5 and the drain electrode 6 is filled with the flattening layer 7, thereby flattening.
  • the layer 7 can flatten the surface of the source electrode 5 and the surface of the drain electrode 6.
  • the surface on which the organic semiconductor layer 8 is laminated can be made flat with no corners or protrusions of the source electrode 5 and the drain electrode 6.
  • the planarizing layer 7 is formed of an organic material, the orientation of crystal growth of the organic semiconductor constituting the organic semiconductor layer 8 can be made uniform.
  • the organic thin film transistor 10 is a modification of the organic thin film transistor 1 and has a flat layer 7 that is inorganic. As shown in FIG. 14, the organic thin film transistor 10 basically has a bottom contour type structure, and a SAM film 15 is formed at the boundary between the planarization layer 7 and the organic semiconductor layer 8. . In the present embodiment, the SAM film 15 and its function will be mainly described, and the structure common to the other organic thin film transistors 1 will be omitted.
  • the planarizing layer 7 of the organic thin film transistor 10 is made of, for example, inorganic substances such as Si_ ⁇ 2, SiN. Since the flat layer 7 is made of an inorganic material and does not have a reactive group, the organic semiconductor crystal cannot be well bonded to the surface of the flat layer 7. Therefore, in the planarization layer forming step (S4) shown in FIG. 4, a self-assembled film (SAM film) 15 is formed on the surface of the planarization layer 7 whose thickness has been reduced by the ashing method.
  • SAM film self-assembled film
  • the self-assembled film is formed by chemical adsorption of a compound having a reactive functional group such as silane or thiol as a hydrolyzable group from a solution containing such a compound onto the surface of the substrate.
  • the SAM film 15 of this embodiment is formed from hexamethyldisilazane (H MDS), which is an organic silane.
  • H MDS hexamethyldisilazane
  • HMDS has a hydrolyzable group that easily binds to inorganic substances, an organic functional group that easily binds to organic substances, and these hydrolyzed groups and organic functional groups are both bonded to a silicon atom (Si). It is a substance. Therefore, as shown in FIG.
  • HMDS octadecyltrichlorosilane
  • ODS octadecylsilane
  • the crystal growth orientation of the organic semiconductor can be aligned by forming the SAM 15 on the surface of the planarizing layer 7.
  • the orientation of the organic semiconductor crystal can be aligned from the source electrode 5 through the organic semiconductor layer 8 to the drain electrode 6 to suppress the generation of crystal grain boundaries.
  • the contact resistance between the interface with the body layer 8 and the interface between the drain electrode 6 and the organic semiconductor layer 8 can be reduced. Accordingly, the charge mobility of the organic thin film transistor 10 can be increased.
  • the organic thin film transistor 10 has the planarization layer 7 made of an inorganic material, and the SAM film 15 is formed between the planarization layer 7 and the organic semiconductor layer 8. It has been.
  • the SAM film 15 is generated from HMDS and has an organic functional group that easily binds to an organic substance. By doing this, the orientation of crystal growth of the organic semiconductor crystal formed on the flat layer 7 can be made uniform.
  • the organic transistor and the method for manufacturing the organic transistor of the present invention are not limited to the above-described embodiment, and various modifications are possible.
  • the flattening layer forming step (S4) for manufacturing the organic thin film transistor 1 the flattening resin is directly dropped into the groove between the source electrode 5 and the drain electrode 6 by the ink jet method and cured.
  • the cocoon layer 7 can also be produced.
  • there is no need to process the flattening layer 7 to a predetermined thickness using the spin coat method so the number of steps in the flattening layer forming process can be reduced and the manufacturing cost can be reduced. it can.
  • material costs can be saved.
  • the planarization layer 7 is formed on the surfaces of the gate insulating layer 4, the source electrode 5 and the drain electrode 6 by dip coating, and then the flat layer 7 is formed by ashing or polishing. It can also be cut into a predetermined film thickness.
  • the dip coating method is simpler than the spin coating method and the ink jet method, and can be easily performed without the need for special equipment.
  • the present invention can be applied to a bottom contact type organic thin film transistor and a method for manufacturing the same.

Landscapes

  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

Un transistor organique du type à contact inférieur et son procédé de fabrication, dans lequel les orientations de croissance de cristal d'une couche semi-conductrice organique sont alignées, moyennant quoi la résistance de contact entre l'électrode source et la couche semi-conductrice organique et celle entre l'électrode drain et la couche semi-conductrice organique sont réduites, et la mobilité de charge est améliorée en conséquence. L'espace entre les électrodes source et drain formé sur une couche isolante de grille est rempli d'un élément de planarisation pour que les électrodes source et drain et l'élément de planarisation soient mutuellement en affleurement. Une couche semi-conductrice organique est formée sur celui-ci, conduisant ainsi à la fabrication d'un transistor organique.
PCT/JP2007/055625 2006-03-29 2007-03-20 Transistor organique à mobilité de charge améliorée et son procédé de fabrication Ceased WO2007119442A1 (fr)

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JP2006090133A JP2007266355A (ja) 2006-03-29 2006-03-29 有機トランジスタ及び有機トランジスタの製造方法
JP2006-090133 2006-03-29

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CN117518649A (zh) * 2023-07-25 2024-02-06 武汉华星光电技术有限公司 一种显示面板
WO2024124566A1 (fr) * 2022-12-16 2024-06-20 京东方科技集团股份有限公司 Substrat de réseau, son procédé de fabrication, écran d'affichage et appareil d'affichage

Families Citing this family (5)

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JP5833439B2 (ja) 2009-04-10 2015-12-16 三菱化学株式会社 電界効果トランジスタ、その製造方法及びそれを用いた電子デバイス
JPWO2011122206A1 (ja) 2010-03-30 2013-07-08 凸版印刷株式会社 積層体の製造方法及び積層体
JP5725614B2 (ja) * 2011-08-04 2015-05-27 国立大学法人大阪大学 有機トランジスタ及びその製造方法
CN115881799B (zh) * 2023-01-31 2023-06-02 广州粤芯半导体技术有限公司 半导体结构及其制备方法
CN118173612A (zh) * 2024-03-07 2024-06-11 深圳平湖实验室 薄膜晶体管及其制备方法、阵列基板、电子设备

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JPH07202115A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 半導体装置の製造
JPH09241419A (ja) * 1996-03-06 1997-09-16 Hitachi Ltd 無溶剤組成物ならびに多層配線基板、およびそれらの製造方法
JP2005519486A (ja) * 2002-03-07 2005-06-30 スリーエム イノベイティブ プロパティズ カンパニー ゲート絶縁膜の改質した表面を有する有機薄膜トランジスタ
JP2006041219A (ja) * 2004-07-28 2006-02-09 Sony Corp 半導体装置及びその製造方法

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JPH07202115A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 半導体装置の製造
JPH09241419A (ja) * 1996-03-06 1997-09-16 Hitachi Ltd 無溶剤組成物ならびに多層配線基板、およびそれらの製造方法
JP2005519486A (ja) * 2002-03-07 2005-06-30 スリーエム イノベイティブ プロパティズ カンパニー ゲート絶縁膜の改質した表面を有する有機薄膜トランジスタ
JP2006041219A (ja) * 2004-07-28 2006-02-09 Sony Corp 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024124566A1 (fr) * 2022-12-16 2024-06-20 京东方科技集团股份有限公司 Substrat de réseau, son procédé de fabrication, écran d'affichage et appareil d'affichage
CN117518649A (zh) * 2023-07-25 2024-02-06 武汉华星光电技术有限公司 一种显示面板

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