WO2006134550A3 - Memory controller - Google Patents

Abstract

A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface. The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data stream (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B) and for dynamically allocating buffers (PFB, WBB) for at least one of the data streams (STl - ST4). The second interlace is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. Furthermore, a buffer dimensioning unit (BDU) is provided for dimensioning the buffer (B) for at least one of the data streams (STl - ST4).