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WO2006052992A3 - High speed and low power scram macro architecture and method - Google Patents

High speed and low power scram macro architecture and method Download PDF

Info

Publication number
WO2006052992A3
WO2006052992A3 PCT/US2005/040478 US2005040478W WO2006052992A3 WO 2006052992 A3 WO2006052992 A3 WO 2006052992A3 US 2005040478 W US2005040478 W US 2005040478W WO 2006052992 A3 WO2006052992 A3 WO 2006052992A3
Authority
WO
WIPO (PCT)
Prior art keywords
mps31
transistors
turning
power
source transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/040478
Other languages
French (fr)
Other versions
WO2006052992A2 (en
Inventor
Joeng-Duk Sohn
Young Tae Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZMOS Technology Inc
Original Assignee
ZMOS Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZMOS Technology Inc filed Critical ZMOS Technology Inc
Priority to EP05851440A priority Critical patent/EP1828896A2/en
Priority to JP2007540180A priority patent/JP2008519538A/en
Publication of WO2006052992A2 publication Critical patent/WO2006052992A2/en
Anticipated expiration legal-status Critical
Publication of WO2006052992A3 publication Critical patent/WO2006052992A3/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)

Abstract

Circuits and methods are described for reducing leakage power in integrated circuit devices whose logic transistors (e.g., logic circuits, latches, and/or output stages) are powered through one or more controllable source transistors. By way of example the circuit has at least one source transistor (MPS31) (e.g., power, ground, or both power and ground) for selectively supplying power to a stage within an integrated circuit device. A means for modulating (CS) the state of the source transistor (MPS31) operates in response to changes in the operating mode (high/low) of the integrated circuit to turn on the source transistor (MPS31) prior to turning on the logic transistors (MNL31-33), and/or to turn off the source transistor (MPS31) after turning off the logic transistors (MNL31-33). In one aspect the delay (ABUF & Pre-Dec) prior to turning off the logic transistors (MNL31-33) can be sufficiently extended to reduce power consumption arising from unnecessarily turning on and off the source transistors (MPS31) for short periods.
PCT/US2005/040478 2004-11-08 2005-11-07 High speed and low power scram macro architecture and method Ceased WO2006052992A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05851440A EP1828896A2 (en) 2004-11-08 2005-11-07 High speed and low power sram macro architecture and method
JP2007540180A JP2008519538A (en) 2004-11-08 2005-11-07 High speed low power SRAM macro architecture and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62612004P 2004-11-08 2004-11-08
US60/626,120 2004-11-08

Publications (2)

Publication Number Publication Date
WO2006052992A2 WO2006052992A2 (en) 2006-05-18
WO2006052992A3 true WO2006052992A3 (en) 2008-07-10

Family

ID=36337149

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/040478 Ceased WO2006052992A2 (en) 2004-11-08 2005-11-07 High speed and low power scram macro architecture and method

Country Status (6)

Country Link
EP (1) EP1828896A2 (en)
JP (1) JP2008519538A (en)
KR (1) KR20070101243A (en)
CN (1) CN101305517A (en)
TW (1) TWI290717B (en)
WO (1) WO2006052992A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5234858B2 (en) * 2006-07-14 2013-07-10 日本電信電話株式会社 Leakage current reduction circuit
TWI381274B (en) * 2008-07-10 2013-01-01 Phison Electronics Corp Block management method and storage system and controller thereof
TWI609375B (en) 2016-01-21 2017-12-21 國立成功大學 Asynchronous two word line driving memory cell and memory with the memory cell
WO2017187731A1 (en) * 2016-04-25 2017-11-02 株式会社ソシオネクスト Input circuit
US10340894B1 (en) * 2018-04-26 2019-07-02 Silicon Laboratories Inc. State retention circuit that retains data storage element state during power reduction mode
CN118866041B (en) * 2023-04-20 2025-09-26 长鑫存储技术有限公司 Power control circuit and memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828234A (en) * 1996-08-27 1998-10-27 Intel Corporation Pulsed reset single phase domino logic
US6242948B1 (en) * 1997-11-19 2001-06-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device
US20030012049A1 (en) * 1995-06-02 2003-01-16 Hitachi, Ltd. Static memory cell having independent data holding voltage

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214962A (en) * 1997-11-19 1999-08-06 Mitsubishi Electric Corp Semiconductor integrated circuit device
JP2003168735A (en) * 2001-11-30 2003-06-13 Hitachi Ltd Semiconductor integrated circuit device
KR100542398B1 (en) * 2001-12-04 2006-01-10 주식회사 하이닉스반도체 Voltage supply circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030012049A1 (en) * 1995-06-02 2003-01-16 Hitachi, Ltd. Static memory cell having independent data holding voltage
US5828234A (en) * 1996-08-27 1998-10-27 Intel Corporation Pulsed reset single phase domino logic
US6242948B1 (en) * 1997-11-19 2001-06-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device

Also Published As

Publication number Publication date
TWI290717B (en) 2007-12-01
TW200625310A (en) 2006-07-16
KR20070101243A (en) 2007-10-16
CN101305517A (en) 2008-11-12
JP2008519538A (en) 2008-06-05
EP1828896A2 (en) 2007-09-05
WO2006052992A2 (en) 2006-05-18

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