ϊ29〇7.ΐ7 九、發明說明： 【發明所屬之技彳軒領域】 相關申請之相互參考 本專利申請優先權係來自建檔於11/08/2004之美國暫 用申μ序旒60/626J20案。其整體地配合此處為參考。 關於聯邦贊助的研究或發展之聲明 於碟片上之參考資料 益 被”、 1〇 關於版權保護之資料 本專利文件中之部份材料是受到美國和其他國家之版 權法的版權保護。版權所有人不反對任何人關於本專利文 件或專利揭示之傳真複製，如於美國專利和商標局公開地 可用之檔案或記錄中顯示，但是，除此之外將保留任何版 15權之所有的權利。版權所有人並不因此放棄任何關於秘密 地保持這專利文件之權利，無限制地包含依據37Cfr·各 1.14規定之權利。 發明領域 本發明一般係關於半導體邏輯電路，並且尤其是關於 20低功率靜態隨機存取記憶體電路。 發明背景 靜態隨機存取記憶體(S R A Μ)是一種電子式資料儲存 形式’其只要電源被供應則保留其資料。靜態ram廣泛地 5 1290717 被铋用在所有的電子式裝置方式之内，並且尤其是在便利 於攜帶式或手持應用、以及高性能裝置應用之使用。於攜 贡式或手持叢置應用中，例如，手機，SRAM提供穩定的資 料保持力而不必支援電路，因此保持著其低複雜性而同時 5 &供健全的資料保持力。 但是，隨著處理技術之進步而電晶體被縮小尺度，斷 電時之電晶體的漏損電流顯著地增加。因此，由於漏損電 流之靜態功率消耗代表較大部分之總功率消耗並且成為 VLSI(非常大型之積體電路)設計中之嚴重的議題。在現存 10之用以減少漏損量的技術是使用電源及/或接地源電晶體 以供應電源至部份裝置，例如，一種輸出級，（亦即，驅動 器），如於第1圖和第2圖之展示。功率電晶體被切斷以切斷 至該輸出級之電源及/或接地，以便因此顯著地減低漏損電 流。來源電晶體之使用提供一種抑制漏損電流的實際方 15法。於一操作模式，例如，備妥模式中，當它們以正常操 作模式被導通之時’來源電晶體則被切斷。 然而，當以這方式利用來源電晶體而製作設計時，一 些議題應該小心謹慎地被考慮，以免導致下列問題，例如， 速率退化、超量功率消耗、資料資訊的安全維持、以及其 20 它者。 應該注意刻，當利用來源電晶體製作設計時，當晶片 操作模式由備安模式（其中來源電晶體被切斷)被改變至正 常操作模式時，6亥來源電晶體可能因為不安定之電源和接 地電位而易受故卩早。 6 1290717 藉由來源電晶體之使用的另一設計議題是頻繁地切換 该來源電晶體之結果，因此切斷它們經不充分之時間週期 以提供節省的功率。如充電和放電大的來源電晶體之閘極 電容結果，顯著的功率不必要地被消耗。 這些缺點出現在SRAM電路之内且較小程度地出現在 其他纪憶體電路之内並且一般在許多包含數位邏輯元件的 積體電路之内。 因此需要有減少數位電路，例如，SRAM，中靜態功 率消耗而影響資料或操作之整體性之系統和方法。本發明 〇滿足4些需求和其他者，其克服先前開發漏損量抑制方法 和電路之無效率性。 【明内^^】 發明概要 15Ϊ29〇7.ΐ7 九, Invention Description: [Technology of the invention belongs to the field] Cross-Reference to Related Applications The priority of this patent application is from the US Provisional Application No. 60/626J20 filed on 11/08/2004. case. It is generally incorporated herein by reference. References to the Federally Sponsored Research or Development Statement on the Disc. 1) Information on Copyright Protection Some of the materials in this patent document are protected by copyright laws of the United States and other countries. The person does not object to any person's fax copying of this patent document or patent disclosure, as shown in the publicly available file or record of the U.S. Patent and Trademark Office, but all rights to any of the 15 rights will be retained. The copyright owner does not waive any right to keep this patent document secretly, without limitation, including the rights pursuant to 37 Cfr. 1.14. Field of the Invention The present invention relates generally to semiconductor logic circuits, and more particularly to 20 low power static BACKGROUND OF THE INVENTION Static random access memory (SRA) is an electronic form of data storage that retains its data as long as it is supplied. Static ram is widely used in all electronic applications. In the way of the device, and especially in the convenience of portable or handheld applications, and The use of performance device applications. In portable or handheld cluster applications, such as mobile phones, SRAM provides stable data retention without the need to support circuits, thus maintaining its low complexity while maintaining a robust data retention. However, as the processing technology advances and the transistor is scaled down, the leakage current of the transistor during power-down increases significantly. Therefore, the static power consumption due to the leakage current represents a larger portion of the total power consumption and It has become a serious issue in the design of VLSI (very large integrated circuit). The existing technology for reducing leakage is to use a power supply and/or ground source transistor to supply power to some devices, for example, a The output stage, (ie, the driver), as shown in Figures 1 and 2. The power transistor is turned off to cut off the power and/or ground to the output stage to thereby significantly reduce leakage current The use of source transistors provides a practical method of suppressing leakage currents. In an operational mode, for example, in ready mode, when they are turned on in normal operating mode When the 'source transistor is cut off. However, when designing the source transistor in this way, some issues should be carefully considered to avoid the following problems, such as rate degradation, excessive power consumption, data The security of information, and its other. It should be noted that when using the source transistor to make the design, when the wafer operation mode is changed to the normal operation mode by the standby mode (where the source transistor is cut), 6 The source-derived transistor may be susceptible to premature power and ground potential. 6 1290717 Another design issue with the use of source transistors is the frequent switching of the source crystals, thus cutting them off. Insufficient time periods to provide saved power. As a result of the gate capacitance of the source transistors with large charge and discharge, significant power is unnecessarily consumed. These shortcomings occur within the SRAM circuit and appear to a lesser extent within other memory circuits and are typically within many integrated circuits that include digital logic elements. There is therefore a need for systems and methods that reduce digital circuitry, such as SRAM, in which static power consumption affects the integrity of data or operations. The present invention satisfies four needs and others that overcome the inefficiencies of previously developed leakage suppression methods and circuits. 【明内^^】 Summary of invention 15
20 ’ 1王川八度王问迷和低功率邏輯電路之方 法和裝置，並且尤其是關於記憶體裝置，例如，靜態隨機 存取記憶體(SRAM)。經由範例，-巨集架構被說明，其提 ^在SRAM裝置㈣於任何所給予的存取速率的每胞元之 以及操作功率消耗。該新穎電路是可應用於包 數位邏輯並且可藉由下列各項被組態： 而m 電㈣销騎的電路操作， ==在備細置和正㈣式之間㈣ ㈣之來源電晶體裝置以麵適當的低功率電路摔作= 然視於在正杯備妥/閒置模叙間的切換 不引動之時間週期以減少切換功率_，及/或⑷-t； 7 1290717 向-偏壓機構以減少晶胞電流漏損量。本發明可藉由八別地 採用本發明之元件，或結合此處所說明以及一般習知之技 術地被實施，而不脫離本發明之技術範_。 该等電路和方法提供減少漏損量操作而保持適去的穿 置操作。當本發明論點被應用至SRAM記憶體裳置带路护 記憶體區域可被減少大約20%，記憶體速率被增加大約乃7 並且漏損電流減少大約一級之幅度。 本發明被說明為用以控制在包含一邏輯電路和輸出驅 動器的積體電路之内的漏損量之方法和電路。一每· 10 15 20 、 只％例被 描緣為在記憶體裝置(例如，靜態隨機存取記憶體)各個晶胞 之内被複製的巨集架構。 應已了解，在達成使用來源電晶體以控制所獲得之带 源之本發明時，最好在達到常態操作之前，例如^憶: 存取或邏輯操作，致動該來源電晶體或電晶體= 輯電路之電晶體，例如，第咏2圖中之mpui、mnlii、 MPL12以及MNL12 ’的電源和接地電位應在晶片進入 操作模式之前被穩定。 本發明是可以-些方式被實施，包含，但是不受 於下面的說明。 本發明-個實施例-般可被說明為—種用以控制在一 積體電路裝置内之來源電晶體之電路，其包含：⑻至少一 個來源電晶體’電源或接地或者電源和接地之⑽，盆被 組態以選擇地供應電源至在—積體電路裝置内之邏輯電晶 體；以及⑵裝置，其用以反應於該積體電路裝置操作模式 8 1290717 改變而調變該等來源電晶體之狀態以在導通該邏輯電晶體 之前導通該等來源電晶體。 該等邏輯電晶體可包含一鎖定器（亦即，記憶體之部 份）、一輸出級、以及其它者。該等來源電晶體供應電源至 5 積體電路内之一輸出級、或一鎖定器、或鎖定器和輸出級 之組合。該用以調變該等來源電晶體之狀態的裝置包含： 一組電路，該電路被組態以接收一選擇信號並且在經由一 第二路線延遲通訊該等選擇信號至該邏輯電晶體之前經由 一第一路線延遲通訊該等選擇信號至該等來源電晶體；並 10 且其中該等第一路線延遲是少於該等第二路線延遲以在致 動該邏輯電晶體之前穩定來源電源。該等選擇信號包含一 晶片選擇或區塊選擇信號。 依據一製作，該用以調變該等來源電晶體之狀態的裝 置包含一組電路，該電路被組態以使用在非同步和同步信 15 號之間時序差量而在該裝置之邏輯電晶體之前致動該等來 源電晶體。該非同步信號被組態以反應於一正性裝置安排 時間在該同步信號之前到達。依據一製作，該非同步信號 包含一晶片選擇信號或區塊選擇信號，並且該同步信號包 含一時脈信號或一與該時脈同步之信號。該非同步信號可 20 依據本發明被採用於調變第一邏輯族群來源電晶體狀態， 並且該同步信號是適用於調變第二或任何依序的邏輯族群 之來源電晶體狀態。 依據一製作，該用以調變該等來源電晶體之狀態的裝 置包含一組電路，該電路用以在低功率非作用電壓位準和 9 1290717 充分支援正常裝置動作之電壓位準之間控制該來源電源。 於一製作中，該電路包含一誤差放大器，該誤差放大器輸 出位準是利用一參考電壓所控制，並且其動作狀態是利用 一裝置選擇信號或區塊選擇信號所決定。 5 於一實施例中，一裝置被提供在該電路中，用以在該 邏輯電晶體被切斷之後用以保持該來源電晶體於導通情況 經一時間週期。於一較佳實施例中，該時間週期利用限制 該來源電晶體在導通及切斷之間不必要地頻繁切換而足以 提供另外的電源節省。該用以保持該來源電晶體於導通情 10 況之裝置包含一組電路，該電路被組態以在接收一作用選 擇信號時致動該來源電晶體，並且用以在該選擇信號返回 不作用之後延遲該來源電晶體不致動經一所需的時間週 期。於一實施例中，該選擇信號可包含一晶片選擇或區塊 選擇信號。 15 本發明一實施例可一般被說明為一種用以控制在一積 體電路裝置内之來源電晶體之電路，其包含：（a)至少一個 來源電晶體、電源或接地、或者電源和接地之組合，其被 組態用以選擇地供應電源至具有邏輯電晶體之一積體電路 裝置；以及(b)裝置，其用以反應於該積體電路裝置操作模 20 式改變而調變該等來源電晶體之狀態以導通該等來源電晶 體並且在該邏輯電晶體被切斷之後保持該來源電晶體於導 通狀態經一時間週期（延遲週期）。依據一製作，該延遲週期 被設定為針對應用之充分持續以減少功率消耗並且防止例 如，起因於來源電晶體閘電容太頻繁之充電和放電的不必 10 1290717 要消散。 本發明之一實施例可一般被說明為一種用以控制在一 積體電路裝置之内來源電壓之電路，其包含：（a) —具有至 少二組邏輯電晶體之鎖定器電路，該等至少二組邏輯電晶 5 體被耦合以維持二值化狀態，其可被存取供存取模式中之 讀取或寫入；（b)至少一個來源連接，電源或接地任一者， 一虛擬來源電位可經由該來源連接被保持；以及⑷一裝 置，其用以驅動該等來源連接從一低功率非作用電壓位準 至一正常存取電壓位準，該正常存取電壓位準被組態以支 10 援正常裝置讀取和寫入存取，在存取該邏輯電晶體之前。 於一實施例中，該低功率非作用模式包含一備妥或閒 置模式，其被製作而具有或不具有資料保持力。於一實施 例中，該鎖定器包含：（a)至少二組CMOS反相器，其中該 第一反相器之輸出連接至該第二反相器之輸入；（b)該第二 15 反相器之輸出連接到該第二反相器之輸入；（c)該等第一和 第二反相器之PM0S電晶體源極連接到所給予的第一節 點；以及(d)該等第一和第二反相器之NM0S電晶體源極連 接到所給予的第二節點。於這實施例一模式中該等來源連 接被耦合至該第一或該第二節點，並且其中一另外的節 20 點，第一或第二，被耦合至一功率來源或一功率來源電晶 體，或連接到一接地源或一接地源電晶體。依據一製作， 用以驅動該來源連接之該裝置被組態以反應於積體電路操 作模式而變化該第一節點之電壓電位。依據一製作，用以 驅動該來源連接之該裝置連接包含一放大器（例如，誤差檢 11 1290717 測、差分、比較器、以及其它者），該放大器被組態用以反 應於接收一參考電壓而控制該來源連接之電壓電位。於一 較佳特點中，該參考電壓是動態或靜態地被規劃。 依據上面實施例之一製作，一第一存取路線被連接到 5 該第一反相器之輸出，或一第二存取路線被連接到該第二 反相器之輸出，或第一和第二存取路線分別地被連接至該 第一和第二反相器之輸出。依據上面實施例之一製作，該 存取路線是利用位址選擇電路被控制，當操作於不是正常 存取模式之至少一個模式時（亦即，電源失效，閒置，以及 10其它者）該位址選擇電路切斷該存取路線而無關於該位址 資訊改變。依據一製作，在一所給予的時間週期經過之後 當沒有位址改變時該存取路線被切斷。依據一製作，該等 來源連接依據該存取路線狀態被控制。 於一實施例中，另外的鎖定器電路被包含，其被組態 15而當該存取路線被切斷時用以儲存位址資訊，並且當該存 取路線閘被導通時用以從這鎖定器回復位址資訊。 本發明之一個實施例可一般被說明為一種控制積體電 路裝置中低功率操作之方法，其包含：⑻檢測一第」選擇 L號’（b)致動來源電晶體，用以反應於收到該第—選擇信 2〇號而^電源至該積體電路電路内之-輸出級、鎖定器、 或鎖二為與輸出級組合；⑷在致動該等來源電晶體之後致 動在fw電路之内的邏輯電晶體；以及⑷其中一充分延 遲被提供在致動該來源電晶體和致動該邏輯電晶體之間以 穩定來自該等來源電晶體之電源。一個實施例進一步包含 12 129071720 ’ 1 Wang Chuan octave and methods and devices for low-power logic circuits, and especially with respect to memory devices, such as static random access memory (SRAM). By way of example, a macro architecture is illustrated, which is presented in the SRAM device (4) at each of the given access rates and operating power consumption. The novel circuit is applicable to packet digital logic and can be configured by: m circuit (four) pin circuit operation, == between fine and positive (four) type (four) (four) source transistor device Appropriate low-power circuit fall = 然 然 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 正 正 正 正 正 正 正 正 正 正Reduce the amount of cell current leakage. The invention may be carried out by the use of the elements of the invention, or in combination with the teachings herein and the teachings of the invention, without departing from the scope of the invention. The circuits and methods provide a reduced wear operation while maintaining a proper amount of leakage. When the inventive algorithm is applied to the SRAM memory, the memory area can be reduced by about 20%, the memory rate is increased by about 7 and the leakage current is reduced by about one level. The present invention is described as a method and circuit for controlling the amount of leakage within an integrated circuit including a logic circuit and an output driver. Each of the 10 15 20, only % examples is depicted as a macro architecture that is replicated within each unit cell of a memory device (eg, SRAM). It will be appreciated that in achieving the invention in which the source transistor is used to control the resulting source of the source, it is preferred to actuate the source transistor or transistor prior to normal operation, such as access or logic operation. The transistor of the circuit, for example, the power and ground potentials of mpui, mmnii, MPL12, and MNL12' in Figure 2 should be stabilized before the wafer enters the operational mode. The invention may be embodied in a number of ways, including but not by the following description. The present invention - generally can be described as a circuit for controlling a source transistor in an integrated circuit device, comprising: (8) at least one source transistor 'power or ground or power and ground (10) a basin configured to selectively supply power to the logic transistor in the integrated circuit device; and (2) means for modulating the source transistor in response to the integrated circuit device operating mode 8 1290717 changing The state is to turn on the source transistors before turning on the logic transistor. The logic transistors can include a locker (i.e., a portion of the memory), an output stage, and others. The source transistors supply power to one of the output stages of the integrated circuit, or a lock, or a combination of a lock and an output stage. The means for modulating the state of the source transistors includes: a set of circuits configured to receive a select signal and to delay communication of the select signals to the logic transistor via a second route A first route delays communication of the selection signals to the source transistors; and 10 and wherein the first route delays are less than the second route delays to stabilize the source power prior to actuating the logic transistors. The select signals include a wafer select or block select signal. According to one production, the means for modulating the state of the source transistors comprises a set of circuits configured to use the timing difference between the asynchronous and synchronous signals 15 and the logic of the device The source transistors are actuated before the crystals. The asynchronous signal is configured to react to a positive device scheduling time to arrive before the synchronization signal. According to a production, the asynchronous signal includes a chip select signal or a block select signal, and the sync signal includes a clock signal or a signal synchronized with the clock. The asynchronous signal 20 can be employed in accordance with the present invention to modulate a first logic group-derived transistor state, and the synchronization signal is a source transistor state suitable for modulating a second or any sequential logical group. According to one fabrication, the means for modulating the state of the source transistors includes a set of circuits for controlling between a low power non-active voltage level and a voltage level sufficient to support normal device operation in 9 1290717. The source power. In one fabrication, the circuit includes an error amplifier whose output level is controlled by a reference voltage and whose operational state is determined by a device selection signal or a block selection signal. In one embodiment, a device is provided in the circuit for maintaining the source transistor in a conducting condition for a period of time after the logic transistor is turned off. In a preferred embodiment, the time period is sufficient to provide additional power savings by limiting the source transistor from unnecessarily frequently switching between turn-on and turn-off. The means for maintaining the source transistor in a conducting condition comprises a set of circuitry configured to actuate the source transistor upon receiving an active selection signal and to return no effect on the selection signal The source transistor is then delayed from being actuated for a desired period of time. In one embodiment, the selection signal can include a wafer selection or block selection signal. An embodiment of the invention may be generally described as a circuit for controlling a source transistor in an integrated circuit device comprising: (a) at least one source transistor, power or ground, or power and ground a combination configured to selectively supply power to an integrated circuit device having a logic transistor; and (b) means for modulating the integrated circuit device operating mode change The state of the source transistor is such that the source transistors are turned on and the source transistor is maintained in an on state for a period of time (delay period) after the logic transistor is turned off. According to one fabrication, the delay period is set to be sufficiently continuous for the application to reduce power consumption and prevent, for example, charging and discharging due to the source transistor gate capacitance being too frequent, 10 1290717 to be dissipated. An embodiment of the present invention can be generally described as a circuit for controlling a source voltage within an integrated circuit device, comprising: (a) a locker circuit having at least two sets of logic transistors, at least Two sets of logic cells 5 are coupled to maintain a binarization state, which can be accessed for reading or writing in an access mode; (b) at least one source connection, power or ground, either virtual The source potential can be maintained via the source connection; and (4) a device for driving the source connections from a low power non-active voltage level to a normal access voltage level, the normal access voltage level being grouped The state is supported by a normal device read and write access before accessing the logic transistor. In one embodiment, the low power inactive mode includes a ready or idle mode that is fabricated with or without data retention. In one embodiment, the locker comprises: (a) at least two sets of CMOS inverters, wherein an output of the first inverter is coupled to an input of the second inverter; (b) the second 15 An output of the phase converter is coupled to an input of the second inverter; (c) a source of the PMOS transistor of the first and second inverters is coupled to the first node to be given; and (d) the first The NMOS transistor sources of the first and second inverters are coupled to the given second node. In the first embodiment mode, the source connections are coupled to the first or second node, and wherein an additional node 20 points, first or second, is coupled to a power source or a power source transistor Or connected to a ground source or a ground source transistor. According to a fabrication, the means for driving the source connection is configured to vary the voltage potential of the first node in response to the integrated circuit mode of operation. According to one fabrication, the device connection for driving the source connection includes an amplifier (eg, error detection 11 1290717, differential, comparator, and others) configured to react to receive a reference voltage Control the voltage potential of the source connection. In a preferred feature, the reference voltage is planned dynamically or statically. According to one of the above embodiments, a first access route is connected to the output of the first inverter, or a second access route is connected to the output of the second inverter, or the first sum The second access route is connected to the outputs of the first and second inverters, respectively. According to one of the above embodiments, the access route is controlled by the address selection circuit when operating in at least one mode that is not the normal access mode (ie, power failure, idle, and 10 others). The address selection circuit cuts off the access route without any change in the address information. According to a production, the access route is cut off when there is no address change after a given time period has elapsed. According to a production, the source connections are controlled according to the access route status. In an embodiment, an additional locker circuit is included that is configured 15 to store address information when the access route is severed, and to use from when the access route gate is turned on The locker replies to the address information. One embodiment of the present invention can be generally described as a method of controlling low power operation in an integrated circuit device, comprising: (8) detecting a "select L number" (b) actuating source transistor for reaction to receive Up to the first selection letter 2 而 and ^ power to the integrated circuit circuit - the output stage, the locker, or the lock 2 is combined with the output stage; (4) actuated at fw after actuating the source transistors A logic transistor within the circuit; and (4) a sufficient delay is provided between actuating the source transistor and actuating the logic transistor to stabilize the power source from the source transistors. An embodiment further includes 12 1290717
在不致動該等邏輯電晶體之後不致動在該等積體電路之内 之該等來源電晶體。依據一製作，一充分延遲週期被提供 在不致動该邏輯電晶體和不致動該來源電晶體之間以防止 當該電路作用時失去電源穩定性。依據一製作，—充分延 5遲週期被引介在該邏輯電晶體和該來源電晶體不致動之間 以減少起因於該來源電晶體導通及切斷頻繁切換之操作功 率損失。 ’' 10 15 20 本發明之-實_是—種具有提早·㈣且延後-不引 動來源電晶體控制電路之高速和低功率sram&集架構。依 據-實施例’電路可包含裝置，其用以使來源電晶體失效 有-些延遲以避免由於在備妥模式中頻繁轉變的額外功率 消耗。依據-實施例，電路可包含裝置，其用於在致動模 式藉由-晶片選擇信號使來源電晶體快速和瞬間引動。依 據-實關，該電路包含反向偏壓裝置，其用於在備妥模 式而拉升—虛擬來源節點大約地〇」伏特至〇.2伏特。依據 實施例，該電路包含裝置，其用以在致動週期中以時序豕邊 限使來源電晶體提早-弓丨動。依據—實施例，該電路包含裝 置’其用於在延遲之後使來源電晶體延後_不引動。於巧 施例之-模式，延後動裝置之延遲週期是具有充分二 度以防止反應於雜電容的充電和放電之另外功率消耗。、 本毛月之Λ %例疋-種用以控制來源電晶體之 和低功率SRAM巨集架構，其包含用以使來源電晶體在 給予的延粒後失效㈣免料以備錢叙頻繁電源轉 變之額外功率消耗之裳置；以及—裝置，其用於在致動模 13 1290717 1290717 5 ❿ 10 15 20 式利用-晶片選擇信號使來源電晶體快速和瞬間引動。依 據-實施例’-裝置被提供而用以傷妥模式而拉升擬 來源節點大約地〇·1伏特至0.2伏特。 實施例是—種用以控制—來源電晶體高速 和::率SRAM之巨集架構’其包含—裝置而用於以時序邊 限在作用週期中使來源電晶體提早巧動；以及—裳置而用 於使來源電晶體延後，動。依據-實施例， 大約地(U伏特至〇.2伏特。 升虛㈣源郎點 本發明之-實施例是一種方法， =:作之來_體，其包;:：= =體具有-些㈣之失效明免由於在備妥模式之頻繁轉 交之猶的功率雜；並且在致動模式利用晶片選擇传號 而提供來源電晶體之快速和瞬間引動。依據—實施例= 向偏壓被提供而以備妥模式拉升—虛擬來源節點大約地 〇·1伏特至0.2伏特。 本發明之一實施例是—種用以控制用於高速和低功率 SRAM操作之來源電晶體的方法，其包含以時序邊限於致動 _中使來源電晶體提早弓！動；以及在延遲之後使來源電 阳體延後·不引動。依據-實施例，反向偏壓被提供而以備 女模式而拉升—虛擬來源節點大約地〇.m特至0.2伏特。 在本毛月之内被„兒明的是一些本發明之論點，其包含 下面者，但是不必定地受其限制。 本發明之一論點是反瘫认 周變來源電晶體狀態而提供 14 1290717 低漏損量邏輯電路操作。 本發明另一論點是提供低漏損量控制電路和方法，其 可被採用於數位積體電路上，其包含邏輯、記憶體、靜態 記憶體、動態記憶體以及其它者。 5 本發明另一論點是提供一高速低功率SRAM巨集架 構。 本發明另一論點是關於一SRAM架構，於其中來源電 晶體是反應於一延遲而不引動以防止另外的功率消耗。 本發明另一論點是關於一SRAM架構，於其中來源電 10 晶體或複數電晶體，在電路進入正常操作模式之前被致動。 本發明另一論點是提供虛擬來源節點之反向偏壓的 SRAM架構。 本發明另一論點是一種具有電源及/或接地源電晶體 之邏輯電路，其依據不同操作模式被被控制。 15 本發明另一論點是具有利用相同輸入被控制的電源及 /或接地源電晶體之邏輯電路，但是其遭受不同的路線延 遲。 本發明另一論點是一種具有一輸入信號之邏輯電路， 該輸入信號是一種晶片失效信號或區塊失效信號。 20 本發明另一論點是一種邏輯電路，於其中輸入信號是 晶片失效信號或區塊失效信號。 本發明另一論點是一種邏輯電路，於其中來源電晶體 控制信號遭受較長之路線延遲。 本發明另一論點是一種邏輯電路，於其中來源電晶體 15 1290717 或電晶體藉由使用在非同步和同步信號之間的時序差量而 被切斷。 本發明另一論點是一種邏輯電路，於其中來源電晶體 反應於早先於該同步信號到達（亦即，具有一正性設定時間） 5 之非同步信號而被控制。 本發明另一論點是一種邏輯電路，於其中非同步信號 是一種晶片失效信號或區塊失效信號。 本發明另一論點是一種邏輯電路，於其中同步信號是 一種時脈信號或同步於一時脈信號之信號。 10 本發明另一論點是一種邏輯電路，於其中如果有多於 一個的來源電晶體（或一組來源電晶體），則該來源電晶體被 族聚在一起，以至於該第一族群利用第一非同步信號被控 制且該第二族群利用第一同步信號被控制。 本發明另一論點是一種具有早先於第一同步信號到達 15 之第一非同步信號的邏輯電路。 本發明另一論點是一種邏輯電路，其包含二組CMOS 反相器，於其中第一反相器之輸出被連接到第二反相器之 輸入’且第二反相器之輸出被連接到第二反相器之輸入， 和第一和第二反相器之PM0S電晶體源極被連接到某個第 20 一節點，並且第一和第二反相器之NM0S電晶體源極被連 接到某個第二節點，而一電源或功率來源電晶體被連接到 該第一節點，並且一接地或接地源電晶體被連接到該第二 節點。 本發明另一論點是一種CMOS邏輯電路，於其中第一 16 l29〇7i7 節點電位反應於操作模式而變化。 本發明另一論點是一種CM0S邏輯電路，當在正常操 作模式之外的其他模式時，其中第一節點之電位是較低於 .正常模式。 5 本發明另一論點是一種CMOS邏輯電路，於其中除了 正常存取模式之外的模式，還包含被製作而具有或不具有 貪料保持力之備妥或閒置模式。 • 本發明另一論點是一種CMOS邏輯電路，於其中第二 節點電位反應於操作模式而變化。 1〇 本發明另一論點是一種CMOS邏輯電路，於其中當除 了正常模式之外的其他模式時，第二節點電位是較高於正 常模式。 ' 本發明另一論點是一種CMOS邏輯電路，於其中功率 來源電晶體是PMOS、NMOS、或PMOS和NMOS電晶體之 - 15 組合。 Φ 本發明另一論點是一種CMOS邏輯電路，於其中接地 源電晶體是PMOS、NMOS、或PMOS和NM0S電晶體之组 合。 、、 本發明另一論點是一種CMOS邏輯電路，於其中功率 來源電晶體之閘極電位反應於操作模式而被變化。 本發明另一論點是一種CMOS邏輯電路，其tNM〇s 力率來源電晶體之閘極電位是較高於正常存取模式中之電 位。 本發明之另一論點是一種CMOS邏輯電路，於其中 17 1290717 式 位 nmos功率來源電晶體之閘極電位是相等或少於正常模 之位準或較少於除了正常存取模式之外的模式之某一 準。 〃 • 本發明之另一論點是一種〇^03邏輯電路，於其中爷 5模式除了正常存取模式之外還包含具有或不具有資料保持 \ 力之備妥或閒置模式。 … 本發明之另一論點是一種(:]^05邏輯電路，於其中 Φ ^^^^接地源電晶體之閘極電位是較低於正常存取模式之 接地位準。 、 10 某一位準 本發明另一論點是一種CMOS邏輯電路，於其中 接地源電晶體之閘極電位是⑽或較高於接地位準或較高 於電路是在除了正常存取模式之外的模式時之正常模式= 本發明另一論點是一種(^]^〇3邏輯電路，於其中該模 -15 <除正f存取模式了之外亦包含具有或不具有資料保持^ φ 之備妥或閒置模式。 本發明另-論點是-種CM0S邏輯電路，於其中職〇s 功率來源電晶體之閘極電位藉由一參考電壓和一誤差檢測 放大益被控制。 、 2〇 本發明另一論點是—種具有一參考電壓之CMOS邏輯 電路，其是動態地或靜態地被規劃。 本發明另-論點是-種CM0S邏輯電路，於其 功率來源電晶體之閘極電位被控制，因而當在除了正常存 取模式之外的模式時，第一節點之電位是較低於正常存: 18 1290717 模式。 本發明另一論點是一種CMOS邏輯電路，於其中PMOS 功率來源電晶體之閘極電位是較高於正常存取模式。 本發明另一論點是一種CMOS邏輯電路，於其中PMOS 5 功率來源電晶體之閘極電位藉由一參考電壓和一誤差檢測 放大器被控制。 本發明另一論點是一種CMOS邏輯電路，於其中NM0S 功率來源電晶體之閘極電位藉由一參考電壓和一誤差檢測 放大器被控制。 10 本發明之進一步的論點是，提供減少靜態功率消耗之 方法，其可使用習見的積體電路製造技術被製作。 本發明進一步的論點將於下面的說明中被闡明，其中 詳細的說明是用於完全地揭示本發明之較佳實施例目的， 而不作限制。 15 圖式簡單說明 本發明將藉由參考下面的圖形而更完全地被了解，該 等圖形僅是供用於展示目的： 第1圖是具有用以減少備妥漏損之接地和來源電晶體 之習見MTCM0S電路的分解圖。 20 第2圖是具有用以減少備妥漏損之接地和來源電晶體 之習見自反向偏壓電路的分解圖。 第3圖是具有接地和來源電晶體用以減少備妥漏損之 CMOS鎖定器電路分解圖。 第4圖是依據本發明一論點之使用來源電晶體的電路 19 12907J7 分解圖，其被展示而提供-種來源電晶體之提早·引動和 後-不引動的組合。 ° 圖 第5圖是依據本發明一論點之第3圖展示的電路之時序 . 第6圖是依據本發明論點之使用來源電晶體的電路分 解圖，其被展示使用-種NMOS接地源電晶體。 第7圖是依據本發明論點之使用來源電晶體群集的電 % 路分解圖，其展示被控制之二群組邏輯。 C實方方式】 10較佳實施例之詳細說明 *更明確地參看於圖形，其用以展示藉由一般被展示於 第3圖至第7圖之裝置而被實施之本發明目的。將了解，裝 置之相關組態和相關部件之細節可以變化，並且方法之相 關特定步驟和順序可以變化，而不脫離如此處被揭示之基 • 15 本概念。 • …第3圖展示本發明—論點，於其中來源電晶體被採用於 周支[應至白見CMOS鎖定器的電源。當該來源電晶體作用 ¥，该鎖定H可儲存且保持資料資訊。但是，切斷該來源 電晶體時問題可能出現，因在許多應用中，需求只要電源 2〇被供應至該裝置，則鎖定器保持資料位元。本發明所説明 之方法和電路一般用以控制鎖定器、記憶體和邏輯電路中 之來源電晶體狀態。 本發明之-原理是來源電晶體之提早引動而有益於避 免邏輯電路故障。此處說明之實施例的技術和方法提供來 20 1290717 源電晶體之提早引動和其他的相關方法。於某些實施例 中，例如，於信號和電路路線中，以及不同的控制信號之 使用與其它者，不同的延遲被提供。 第4圖經由範例以展示實施例，於其中位址通道具有不 5 同的信號延遲，而第5圖則揭示該信號時序。 考慮到第4圖電路，其假設反相器INV31是遭受高漏損 電流，因其一般是大量地較大於内接於積體電路之裝置。 一功率電晶體MPS31被添加至INV31之一PMOS來源電晶 體以壓制漏損電流。應該了解，一實施例可藉由該NMOS 10 來源電晶體被產生，如第2圖之展示(MNS12)。當一晶片選 擇信號(CS)被引動（低引動信號，如第5圖所展示）時，節點 A處於低引動信號並且致動（導通）來源電晶體mpS31。 該晶片選擇信號具有另一路線以引動位址緩衝器去接 收位址(ABUF)。該被接收之位址被預解碼並且節點c在一 15些時間延遲之後成為高位。預充電信號(PPRE)在節點C成為 高位之前不被引動以消除靜態電流通路。當所有的閘極信 5虎MNL31、MNL32以及MNL33成為高位日寺，節點以皮放電 並且成為低位。節點D的低電位導通該pM〇s電晶體 並且使得該輸出節點(0UT31)成為高位。 2〇 應注意到，在節點0成為低位並且導通該PMOS電晶體 INV31之前’該電源線1NV31應該被穩定並且因此，功率電 晶體MPS31必須在節點D成為低位之前被導通。於這電路製 作中’因為功率電晶體，MpS3卜使用相同信號被控制且 被引動’但7^卩遭受不同的信號延遲（亦即，短信號延遲）， 21 1290717 MPS31可早先紐導通，因而轉致反㈣電路，廣3i， 之任何故障。如於第5圖之展示，在信號A和信號C之間有 —時序邊限(TMD以適當地控制該來源電晶體。 • Λ處說明用以控制來源電晶體動作之另-方法是利用 .5曰曰曰片上不同形式的信號。例如，一些非同步信號，例如晶 片忠擇仰）以設定之時間邊限之時脈前進人該晶片。因 此，相關於非同步信號之提早到達的資訊，例如，晶片選 _ #，可被使用以導通該來源電晶體，即使其他的輸入，例 如位址，在同步信號上升或下降邊緣⑽如，該時脈灌捕 10獲。 第4圖和第5圖同日寸也展示一種防止不必要的引動和不 弓1動功率來源電晶體之方法。應注意到，當該電路過分頻 繁地引動和不引動該功率電晶體時，過度的功率可被消 15耗’其可此出現於，例如，當該來源電晶體在順序存取之 間不被引動日守。當反應於輸入電容器充電和放電，而反應 _ 玄過度頻繁不致動時，額外的功率被消耗。 為克服這缺點，本發明一論點提供用以在一些延遲之 ，來^晶體的不引動’即使—不引動信號被致動（亦即， 曰曰片選擇成為不作用）。如第實施範例中，即使該晶片 ' ρρ ^ ^ 口唬(CS)成為高位，而節點A電位在所需的信號延遲之 後成為南位’（亦即，100=微秒)例如，反應至一延遲電路(於 第4圖中被標明為“延遲，，)或自該來源電晶體引介一充分信 就延遲以碟保電源穩定之其他方法。於這所給予的實例 中’該充分延遲確保該等來源電晶體在該晶片選擇信號返 22 1290717 回不作用之後保持導通一短週期。僅在一 之期間，如藉由延遲被決定，該來源带曰相對不作用週期 切斷，因此減少相關於電容之充電=曰曰體被切換而返回 應了解，因為該來源電晶體的的功率損失。 5電流至邏輯電路，由於其之閘極電容之疋允。午其供應充分 消耗可以是主要因素。因此，該延^電和放電的功率 實際地於備妥模式中，因為當切斷該來=確保該晶片是 在延遲週狀咖減低位。 μ㈣之情況時 可二:遲的方式被產生，不論是否靜態、 =妹錢疋反應於變量或其他錢的接收，以及盆 痛似者。將了解，該延叙最料 - m 、决於忒电路之應用 η吏用，以便使功率龍最小化。本_之_論點是提供 種允錢时最佳化它們_定製作之可健的延遲週 期。經由_ ’該延遲可斷燒I較置被規劃。 15 於本發明之另—論財，鎖定器電路(例如，習見的 CMOS鎖定贈之漏損電流可被減少，以增加來源電晶體 和控制，而不必引介速率延遲。第3圖說明一種具有一 NM〇S功率來源電晶體和PMOS接地源電晶體之CM〇s鎖定 裔。當被儲存於CMOS鎖定器中之資料不需要被保持時，該 20來源電晶體，例如，範例中之MNS2和MPS2，可被斷電以 消除漏損通路。 但是，於儲存於CM0S鎖定器上之資料應該被保持之 情況中’則該來源電晶體不能被斷電。依據本發明這論點， NMOS和PMOS來源電晶體(MNS2和MPS2)之閘極電位可被 23 1290717 控制以提供不同於那些在正常操作期間呈現的電壓位準。 經由範例，NMOS來源電晶體(MNS2)之閘極電位可自一被 拉升之電壓（其是較大於Vdd(>Vdd))而被改變至電壓 Vdd(=Vdd)，並且該閘極電位PMOS來源電晶體(MPS2)同時 5 也可自一較低於Vss(<Vss)之被拉升電壓被改變至 Vss(=Vss)。因此，（虛擬電壓NNX)之電位位準VVDD2和VVss2 分別地成為 Vdd-Vui(MNS2)和 Vtp(MPS2)，其中 vtn(MNS2) 和Vtp(MPS2)分別地是MNS2和MPS2之臨限電壓。該被改變 之VVdd2和Wss2電位位準可增加CMOS鎖定器電晶體之臨 10 限電壓。例如，MPL21和MPL22之本體•至-源極電壓被降低 Vtn(MNS2)，並且MNL21和MNL22之源極-至-本體電壓分別 地被增加Vtp(MPS2)。利用這些電壓改變之方法可導致供用 於CMOS鎖定器電晶體之增加臨限電壓，並且，因此，經由 CMOS鎖定器流動之漏損電流可被壓制。 15 弟6圖展示在SRAM(靜態隨機存取記憶體）晶胞中具有 NMOS接地源電晶體(MNS51)之另一邏輯電路實施範例。鹿 了解，相關於DRAM(動態隨機存取記憶體)之位元線感靡放 大器的相似電路可被採用。於這製作中，虛擬接地電位 (VVSS5)可以利用一參考電壓（vREF)和一放大器（例如，令吳差 20檢測放大器（AMP5))而任意地被控制。該接地電位接著反應 於裝置模式之改變而在一作用和不作用邏輯電路模式之間 被切換，例如，當藉由一選擇信號(例如，一晶片選擇(cs) 或訊塊選擇信號)被反映時。該參考電壓位準可利用不同的 方法(例如熔絲選擇)被設定。這技術之一優點是虛擬接地位 24 1290717 準(wSS5)之可控制能力。應了解，—相似架構可以額外地、 或另外地，被製作以用於控舰鎖定器之虛擬I電位。 於上述第3圖所說明之CM〇s鎖定器中，該虛擬電源和 接地位準 NMC)S和PM〇s來源電晶體之臨限電塵被決 5定並且是不可控制的。此類位準對於晶片操作條件（如溫 度、#作電壓以及其它者)是敏_，並且同時也是易遭致 製造處理程序變化。例如，當溫度增加時，⑽電晶體之 臨限電壓減少。因此，當溫度增加時，在實際和虛擬的電 源以及接地位準之間的差量減少。因此，即使漏損電流在 H)南的溫度成為更嚴重，漏損抑制則由於臨限電 響而成為較少。 相對地，本發明這論點提供有效的漏損抑制，如第6 圖之表不’因為反應於，㈣虛擬電源和接地位準 可被控制。任何-些技術可被採用而適當地控制且規割夫 15考位準。接地源電晶體細如)之狀_㈣在字組線_ 引動之厨被導通的電路而依序地被控制，以防止存取（亦 P »貝取)速率惡化。此外，接地源電晶體可藉由使用控制 信號(例如，如上述相關第4圖說明之晶片選擇卿在某一 延遲之後被切斷。 20 m準反應於所欲的操作溫度、電壓和電路處理特 性被設定以㈣—所給予的應用。當晶片選擇信號(CS)成 為低位時，節點A51成為高位(或一比VDD較高的電壓以增加 mnS51之錢鶴能力而供用於更快之讀取物並且導 通廳51。當字組線(WL)成為高位時一位元線肌或叫 25 1290717 依據被儲存於CMOS鎖定器中之資料被放電並且一正常的 讀取或另一存取操作可被進行。 反應於在完成一操作之後該晶片被閒置一充分長時間 週期’本發明之被延遲來源電晶體不致動論點可選擇地被 5 施加。當減少不必要切斷該來源電晶體以經將不產生一功 率儲存之一短時間週期，或依據應用和操作以比較於較小 的時間週期而減少功率消耗時，該時間週期長度可被考慮 為充分。 例如’在進行一讀取操作後在記憶體晶胞於一長時間 10不被存取之後，該晶片選擇信號(CS)不變為高位並且該字 組線保持被引動。於這情況中，因為該字組線是高位，通 過的閘電晶體MNL53和MNL54被導通。因此，自一位元線 負載（不在這裡被展示）至該SRAM晶胞之拉降電晶體 (MNL51或MNL52)的漏損電流被添加至該CMOS鎖定器之 15漏損電流。因此，於這情況中，當利用一信號或一信號組 合被決定之某一延遲發生之後，該字組線位準轉變為低位 且用於該字組線之資訊可被儲存在暫存器中，並且該接地 源電晶體（MNS51)被控制以拉升虛擬接地(vVss5)之一電 位。當一新的操作啟動時，節點A52和A53之電位位準可藉 20由導通該字組線和控制該來源電晶體而被更新並且被重新 儲存回至先前的狀態。 第6圖表示之實施例展示一種電路，其包含兩個CMOS 反相器，於其中該第一反相器之輸出被連接到第二反相器 之輸入，並且第二反相器之輸出被連接到第二反相器之輪 26 1290717 入。第一和第二反相器之PMOS電晶體的源極被連接到某個 第一節點，並且第一和第二反相器之NM0S電晶體的源極 被連接到一第二節點。一電源或功率電晶體被連接到該第 一節點，且一接地或接地源電晶體被連接到該第二節點。 5該第一存取路線(例如，讀取或寫入)被連接到該第一反相器 之輸出，及/或該第二存取路線被連接到第二反相器之輸 出。The source transistors within the integrated circuits are not actuated after the logic transistors are actuated. According to one fabrication, a sufficient delay period is provided between not actuating the logic transistor and not actuating the source transistor to prevent loss of power supply stability when the circuit is active. According to one fabrication, a fully extended 5-late period is introduced between the logic transistor and the source transistor being unactuated to reduce operational power loss due to frequent switching of the source transistor and switching off. The present invention is a high speed and low power sram & set architecture with an early (four) and delayed-non-induced source transistor control circuit. The circuit according to the embodiment may comprise means for inactivating the source transistor with some delay to avoid additional power consumption due to frequent transitions in the ready mode. According to an embodiment, the circuit can include means for rapidly and instantaneously priming the source transistor in the actuation mode by the - wafer selection signal. According to the real-time, the circuit includes a reverse biasing device for pulling up in a ready mode - the virtual source node is approximately volts to 〇2 volts. In accordance with an embodiment, the circuit includes means for causing the source transistor to prematurely bow during the actuation cycle with a timing threshold. According to an embodiment, the circuit comprises means 'for delaying the source transistor after the delay_ without urging. In the case of the embodiment, the delay period of the delay device is an additional power consumption with sufficient second degree to prevent charging and discharging in response to the capacitive capacitor.本 毛 Λ Λ % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % An additional power consumption of the transition; and a device for rapidly and instantaneously priming the source transistor in the actuating mode 13 1290717 1290717 5 ❿ 10 15 20 using the wafer select signal. According to the embodiment - the device is provided to use the damage mode to pull up the intended source node from approximately 1 volt to 0.2 volt. Embodiments are a macro-architecture structure for controlling-source transistor high-speed and:-rate SRAM, which includes means for prematurely causing the source transistor to be activated in a duty cycle with a timing margin; It is used to delay the source of the transistor and move it. According to the embodiment, approximately (U volts to 〇. 2 volts. 升虚(四)源郎点的发明的实施例 - The embodiment is a method, =: _ _ body, its package;:: = = body has - The failure of these (4) is due to the power mismatch of the frequent handover in the ready mode; and the fast and instantaneous priming of the source transistor is provided by the wafer selection signal in the actuation mode. Provided in a ready mode pull-up - the virtual source node is approximately 1 volt to 0.2 volt. One embodiment of the present invention is a method for controlling a source transistor for high speed and low power SRAM operation, Including the timing edge is limited to actuation _ in the source transistor early bowing; and after the delay, the source electrical body is postponed and not ignited. According to the embodiment, the reverse bias is provided in preparation for the female mode Pull-up - the virtual source node is approximately 〇.m to 0.2 volts. Within the present month is the argument of the present invention, which includes the following, but is not necessarily limited by it. One argument is to counter-recognize the source of the transistor state. Providing 14 1290717 low leakage amount logic circuit operation. Another object of the present invention is to provide a low leakage amount control circuit and method which can be applied to a digital integrated circuit including logic, memory, static memory, Dynamic memory and others. Another aspect of the present invention is to provide a high speed low power SRAM macro set architecture. Another aspect of the present invention relates to an SRAM architecture in which a source transistor is reacted to a delay without igniting to prevent Additional power consumption. Another aspect of the invention relates to an SRAM architecture in which a source of 10 crystals or a plurality of transistors is actuated before the circuit enters a normal mode of operation. Another object of the invention is to provide a counter of the virtual source node. A biased SRAM architecture. Another aspect of the invention is a logic circuit having a power supply and/or ground source transistor that is controlled according to different modes of operation. 15 Another aspect of the invention is that it is controlled using the same input. A logic circuit of a power supply and/or a ground source transistor, but which suffers from different path delays. Another aspect of the invention is a A logic circuit having an input signal, the input signal being a wafer failure signal or a block failure signal. 20 Another aspect of the invention is a logic circuit in which the input signal is a wafer failure signal or a block failure signal. The argument is a logic circuit in which the source transistor control signal suffers from a longer path delay. Another aspect of the invention is a logic circuit in which the source transistor 15 1290717 or transistor is used by asynchronous and synchronous signals. Another discontinuity of the timing difference is a logic circuit in which the source transistor reacts to an asynchronous signal that arrives earlier (i.e., has a positive settling time) 5 of the synchronization signal. Controlled Another aspect of the invention is a logic circuit in which the asynchronous signal is a wafer fail signal or a block fail signal. Another aspect of the invention is a logic circuit in which the sync signal is a clock signal or a signal synchronized to a clock signal. 10 Another aspect of the invention is a logic circuit in which if there is more than one source transistor (or a group of source transistors), the source transistors are grouped together such that the first group utilizes An asynchronous signal is controlled and the second group is controlled using the first synchronization signal. Another aspect of the invention is a logic circuit having a first asynchronous signal that arrives earlier than the first sync signal. Another aspect of the present invention is a logic circuit comprising two sets of CMOS inverters, wherein an output of a first inverter is coupled to an input of a second inverter and an output of the second inverter is coupled to The input of the second inverter, and the PMOS transistor source of the first and second inverters are connected to a certain 20th node, and the NMOS transistors of the first and second inverters are connected To a second node, a power or power source transistor is connected to the first node and a ground or ground source transistor is connected to the second node. Another aspect of the present invention is a CMOS logic circuit in which the potential of the first 16 l29 〇 7i7 node changes in response to the mode of operation. Another aspect of the present invention is a CMOS logic circuit in which the potential of the first node is lower than the normal mode when in a mode other than the normal operating mode. Another object of the present invention is a CMOS logic circuit in which a mode other than the normal access mode includes a ready or idle mode that is fabricated with or without greedy retention. Another aspect of the invention is a CMOS logic circuit in which the potential of the second node changes in response to the mode of operation. Another object of the present invention is a CMOS logic circuit in which the second node potential is higher than the normal mode when other modes than the normal mode are removed. Another aspect of the invention is a CMOS logic circuit in which the power source transistor is a combination of PMOS, NMOS, or PMOS and NMOS transistors. Φ Another aspect of the invention is a CMOS logic circuit in which the ground source transistor is a combination of PMOS, NMOS, or PMOS and NMOS transistors. Another aspect of the present invention is a CMOS logic circuit in which the gate potential of a power source transistor is varied in response to an operational mode. Another aspect of the present invention is a CMOS logic circuit in which the gate potential of the tNM 〇s force rate source transistor is higher than that in the normal access mode. Another aspect of the present invention is a CMOS logic circuit in which the gate potential of the 17 1290717-type nmos power-source transistor is equal or less than the level of the normal mode or less than the mode other than the normal access mode. Some standard. 〃 • Another aspect of the present invention is a 逻辑03 logic circuit in which the MASTER 5 mode includes a ready or idle mode with or without data retention in addition to the normal access mode. Another argument of the present invention is a (:]^05 logic circuit in which the gate potential of the Φ ^^^^ ground source transistor is lower than the ground level of the normal access mode. Another argument of the present invention is a CMOS logic circuit in which the gate potential of the ground source transistor is (10) or higher than the ground level or higher than when the circuit is in a mode other than the normal access mode. Mode = Another aspect of the present invention is a (^)^3 logic circuit in which the modulo-15 <in addition to the positive f access mode, also includes or is not provided with or without data retention ^ φ Another aspect of the present invention is a CM0S logic circuit in which the gate potential of the power source transistor is controlled by a reference voltage and an error detection amplification. 2, another argument of the present invention is a CMOS logic circuit having a reference voltage, which is planned dynamically or statically. Another aspect of the invention is a CMOS logic circuit in which the gate potential of the power source transistor is controlled, thus When the mode is outside the normal access mode The potential of the first node is lower than normal: 18 1290717 mode. Another aspect of the invention is a CMOS logic circuit in which the gate potential of the PMOS power source transistor is higher than the normal access mode. One argument is a CMOS logic circuit in which the gate potential of a PMOS 5 power source transistor is controlled by a reference voltage and an error detection amplifier. Another aspect of the invention is a CMOS logic circuit in which the NM0S power source is electrically The gate potential of the crystal is controlled by a reference voltage and an error detecting amplifier.10 A further object of the invention is to provide a method of reducing static power consumption that can be fabricated using conventional integrated circuit fabrication techniques. The following is a description of the preferred embodiments of the present invention, and is not intended to be limiting. More fully understood, these graphics are for display purposes only: Figure 1 is intended to reduce readiness See the exploded view of the MTCM0S circuit for the grounding and source transistors. 20 Figure 2 is an exploded view of the self-reverse bias circuit with ground and source transistors to reduce the leakage. An exploded view of a CMOS locker circuit with ground and source transistors to reduce readout leakage. Figure 4 is an exploded view of a circuit 19 12907J7 using a source transistor in accordance with an aspect of the present invention, which is shown to provide a source Combination of early and priming of the transistor and post-no illuminating. Figure 5 is a timing diagram of the circuit shown in Fig. 3 of an argument of the present invention. Fig. 6 is a circuit using a source transistor in accordance with the teachings of the present invention. An exploded view, which is shown using an NMOS grounded source transistor. Figure 7 is an exploded view of an electrical circuit using a source transistor cluster in accordance with the teachings of the present invention showing the controlled two group logic. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 10 Detailed Description of the Preferred Embodiments * More specifically, reference is made to the drawings for the purpose of the present invention which is embodied by the apparatus generally shown in Figures 3 through 7. It will be appreciated that the configuration of the device and the details of the relevant components may vary, and the particular steps and sequences of the method may vary without departing from the concept as disclosed herein. • ... Figure 3 shows the invention - the argument in which the source transistor is used in the peripheral branch [since the white CMOS locker power supply. When the source transistor acts as ¥, the lock H can store and maintain data information. However, problems can arise when the source transistor is turned off, because in many applications, the latch maintains the data bit as long as the power supply is supplied to the device. The methods and circuits described herein are generally used to control the state of the source transistor in the latch, memory, and logic circuitry. The principle of the present invention is the early priming of the source transistor to help avoid logic circuit failure. The techniques and methods of the embodiments described herein provide for the early priming of the source transistor and other related methods. In some embodiments, different delays are provided, for example, in signal and circuit paths, and the use of different control signals, and others. Figure 4 illustrates an embodiment by way of example in which the address channel has a different signal delay, while Figure 5 reveals the signal timing. Considering the circuit of Fig. 4, it is assumed that the inverter INV31 is subjected to a high leakage current because it is generally larger than the device connected to the integrated circuit. A power transistor MPS31 is added to one of the PMOS source PMOS crystals to suppress the leakage current. It will be appreciated that an embodiment can be produced by the NMOS 10 source transistor, as shown in Figure 2 (MNS12). When a wafer select signal (CS) is illuminated (low priming signal, as shown in Figure 5), node A is at a low priming signal and actuates (turns on) the source transistor mpS31. The wafer select signal has another route to illuminate the address buffer to receive the address (ABUF). The received address is pre-decoded and node c becomes high after a delay of some 15 times. The precharge signal (PPRE) is not steered until node C becomes high to eliminate the quiescent current path. When all the gates 5, MNL31, MNL32, and MNL33 become high-level temples, the nodes are discharged by the skin and become low. The low potential of node D turns on the pM〇s transistor and causes the output node (OUT31) to be high. 2〇 It should be noted that the power supply line 1NV31 should be stabilized before the node 0 becomes the low level and the PMOS transistor INV31 is turned on. Therefore, the power transistor MPS31 must be turned on before the node D becomes the low level. In this circuit fabrication, 'because of power transistors, MpS3 Bu is controlled and motivated using the same signal', but 7^卩 suffers from different signal delays (ie, short signal delay), 21 1290717 MPS31 can be turned on earlier, thus turning Inverse (four) circuit, wide 3i, any fault. As shown in Figure 5, there is a timing margin between signal A and signal C (TMD to properly control the source transistor. • The other way to control the action of the source transistor is to utilize it. 5 different types of signals on the chip. For example, some non-synchronous signals, such as wafer singularity, advance the person to the wafer with a set time margin. Thus, information relating to the early arrival of the asynchronous signal, for example, the chip select_#, can be used to turn on the source transistor even if other inputs, such as an address, are at the rising or falling edge of the sync signal (10), for example, The clock was arrested and harvested 10 times. Figures 4 and 5 also show a way to prevent unnecessary priming and non-dynamic power source transistors. It should be noted that when the circuit pulsates and does not illuminate the power transistor too frequently, excessive power can be dissipated. 'This can occur, for example, when the source transistor is not between sequential accesses. Inspire the day. When the reaction is charged and discharged by the input capacitor, and the reaction is too frequent and is not actuated, additional power is consumed. To overcome this shortcoming, an argument of the present invention provides for the use of a non-priming 'even-no illuminating signal' to be actuated (i.e., sputum selection becomes inactive) at some delay. As in the first embodiment, even if the wafer 'ρρ ^ ^ port 唬 (CS) becomes high, and the node A potential becomes south after the desired signal delay ' (ie, 100 = microseconds), for example, reacts to one The delay circuit (labeled as "delay," in Figure 4) or other method of delaying the power supply from the source is introduced from the source transistor. In the example given, 'this sufficient delay ensures that The source transistor remains on for a short period after the wafer select signal returns 22 1290717. In the meantime, the source band is relatively inactive during the period, such as by the delay, so the correlation is reduced. Charging of the capacitor = the body is switched back and should be understood, because of the power loss of the source transistor. 5 Current to the logic circuit, due to its gate capacitance, the full consumption of the supply can be the main factor. Therefore, the power of the extension and discharge is actually in the ready mode, because when the cut is made = the wafer is guaranteed to be delayed in the delay of the coffee. In the case of μ (four), two: a late manner is generated. Whether it is static, = sister money, reaction to the receipt of variables or other money, and pelvic pain. It will be understood that the extension is expected to be - m, depending on the application of the circuit, in order to minimize the power dragon The _ _ _ argument is to provide a kind of robust delay period for the production of the money when it is allowed to make money. The _ 'the delay can be burned I is planned. 15 In the other part of the invention, The locker circuit (for example, the CMOS lock-off leakage current can be reduced to increase the source transistor and control without introducing the rate delay. Figure 3 illustrates a transistor with a NM〇S power source and PMOS ground. The CM〇s of the source transistor is locked. When the data stored in the CMOS lock does not need to be held, the 20-source transistor, for example, MNS2 and MPS2 in the example, can be powered off to eliminate the leakage path. However, in the case where the data stored on the CMOS locker should be maintained, then the source transistor cannot be powered down. According to the present invention, the gate potentials of the NMOS and PMOS source transistors (MNS2 and MPS2) Can be controlled by 23 1290717 Providing a voltage level different from those presented during normal operation. By way of example, the gate potential of the NMOS source transistor (MNS2) can be pulled from a pulled voltage (which is greater than Vdd (> Vdd)). The voltage is changed to the voltage Vdd (= Vdd), and the gate potential PMOS source transistor (MPS2) 5 can also be changed from Vss (= Vss) from a pulled voltage lower than Vss (<Vss). Therefore, the potential levels VVDD2 and VVss2 of (virtual voltage NNX) become Vdd-Vui(MNS2) and Vtp(MPS2), respectively, where vtn(MNS2) and Vtp(MPS2) are the threshold voltages of MNS2 and MPS2, respectively. The changed VVdd2 and Wss2 potential levels increase the threshold voltage of the CMOS latch transistor. For example, the body-to-source voltages of MPL21 and MPL22 are lowered by Vtn (MNS2), and the source-to-body voltages of MNL21 and MNL22 are respectively increased by Vtp (MPS2). The use of these voltage changes can result in an increased threshold voltage for the CMOS locker transistor and, therefore, the leakage current flowing through the CMOS lock can be suppressed. Figure 15 shows another logic circuit implementation example with an NMOS ground source transistor (MNS51) in an SRAM (Static Random Access Memory) cell. Deer understand that a similar circuit related to the bit line sense amplifier of DRAM (Dynamic Random Access Memory) can be used. In this fabrication, the virtual ground potential (VVSS5) can be arbitrarily controlled using a reference voltage (vREF) and an amplifier (e.g., ohms 20 sense amplifier (AMP5)). The ground potential is then switched between an active and inactive logic mode in response to a change in device mode, for example, when reflected by a select signal (eg, a wafer select (cs) or block select signal) Time. This reference voltage level can be set using different methods (e.g., fuse selection). One of the advantages of this technology is the controllability of the virtual ground bit 24 1290717 quasi (wSS5). It will be appreciated that a similar architecture may additionally or alternatively be fabricated for use in controlling the virtual I potential of the lock. In the CM〇s locker illustrated in Figure 3 above, the virtual power and ground level NMC)S and the PM ss source transistor's threshold dust are determined and uncontrollable. Such levels are sensitive to wafer operating conditions (e.g., temperature, voltage, and others) and are also susceptible to manufacturing process variations. For example, as the temperature increases, (10) the threshold voltage of the transistor decreases. Therefore, as the temperature increases, the difference between the actual and virtual power and ground levels decreases. Therefore, even if the leakage current is more severe in the south of H), the leakage suppression becomes less due to the threshold current. In contrast, this aspect of the invention provides for effective leakage suppression, as shown in Figure 6, because the reaction (4) virtual power and ground levels can be controlled. Any of these techniques can be adopted and appropriately controlled and regulated. The grounding source transistor is as thin as _(d) in the word line _ the kitchen that is turned on is sequentially controlled to prevent the access rate (also P) from deteriorating. In addition, the ground source transistor can be switched off after a certain delay by using a control signal (eg, wafer selection as described above in relation to Figure 4). 20 m quasi-reactive to desired operating temperature, voltage, and circuit processing The characteristics are set to (4) - the application given. When the chip select signal (CS) becomes low, node A51 becomes high (or a higher voltage than VDD to increase the mNS51's ability for faster reading) And the conduction hall 51. When the word line (WL) becomes high, a single line muscle or 25 1290717 is discharged according to the data stored in the CMOS locker and a normal reading or another access operation is available. The reaction is performed after the operation of the wafer is idle for a sufficiently long period of time. The delay-source transistor inactivation of the present invention is optionally applied by 5. The reduction of the source transistor is not necessary to cut the source. The length of the time period can be considered sufficient if one of the power storage will not be generated for a short period of time, or when the power consumption is reduced in comparison to the application and operation to compare to a smaller time period. 'After performing a read operation, after the memory cell is not accessed for a long time 10, the wafer select signal (CS) remains unchanged and the word line remains primed. In this case, because The word line is high and the pass gate transistors MNL53 and MNL54 are turned on. Therefore, the leakage from the one-line load (not shown here) to the pull-down transistor (MNL51 or MNL52) of the SRAM cell A current is added to the leakage current of the CMOS latch. Thus, in this case, after a certain delay determined by a signal or a combination of signals occurs, the block line level transitions to a low level and is used for The information of the word line can be stored in the register, and the ground source transistor (MNS51) is controlled to pull up one of the potentials of the virtual ground (vVss5). When a new operation is initiated, nodes A52 and A53 The potential level can be updated by turning on the word line and controlling the source transistor and being re-stored back to the previous state. Figure 6 shows an embodiment showing a circuit that includes two CMOS inversions The first inverter The output is coupled to the input of the second inverter, and the output of the second inverter is coupled to the wheel 26 1290717 of the second inverter. The sources of the PMOS transistors of the first and second inverters are Connected to a certain first node, and the sources of the NMOS transistors of the first and second inverters are connected to a second node. A power or power transistor is connected to the first node, and a ground or A ground source transistor is coupled to the second node. 5 the first access route (eg, read or write) is coupled to the output of the first inverter, and/or the second access route is Connected to the output of the second inverter.
這實施例中之電路存取路線最好是藉由保持該位址資 訊之電路而被控制，而在除了正常存取模式之外的模式之 10時，该存取路線被切斷而無關於該位址資訊改變並且該位 址資訊被保留在別處。於_模式中，當經某一週期沒有位 址改變時，存取路線被切斷。於一模式中，當經某一週期 /又有位址改、交時，存取路線被切斷，並且該位址資訊被儲 存在別處，且於控能存取路狀電財，電職/或來源 15 電晶體被被切斷。 20 於貝知例中，位址資訊被儲存在別處且存取路線閘 可在某輯或反應於一所給予的控制信號之後被切斷。 第一節點之電㈣倾降低至在正常麵模式 的數量，並且第二節點之《電位被提昇 斤二 電 正常存取模式位準。於—模式中，存取路二 ㈣電源及/或接地源電晶體之電路被控制^也 晶體反應於存取路線閉極之狀態而被調變。於 27 1290717 當存取路線閘極被切斷時 斷。 電源及/或接地源電晶體被切The circuit access route in this embodiment is preferably controlled by a circuit that holds the address information, and in the mode 10 other than the normal access mode, the access route is cut off without regard to The address information changes and the address information is kept elsewhere. In the _ mode, when there is no address change in a certain period, the access route is cut. In the first mode, when a certain period/address has been changed and handed over, the access route is cut off, and the address information is stored elsewhere, and the access control road access electricity, electricity service / or source 15 The transistor is cut. 20 In the case of Yube, the address information is stored elsewhere and the access route gate can be cut off after a certain series or reaction to a given control signal. The first node's power (four) tilts down to the number in the normal plane mode, and the second node's "potential is boosted to the normal access mode level. In the - mode, the circuit of the access circuit (4) power supply and/or the ground source transistor is controlled, and the crystal is modulated in response to the closed state of the access path. On 27 1290717 when the access path gate is cut off. Power and / or ground source transistor is cut
二實施例中，電路包含-鎖定器，其當存取路線間 ^撕日存餘m，並且當該存取路線閘被導通 =則該位址資訊自這鎖定器被取回。於—模式中，除了正 常存取模式之外，該存取路線早先於正常模式者被切斷且 及位址被儲存在別處，並且當該存取路㈣湘某一控制 信號或命令被導通時，該被儲存之位址資訊被使用。 第7圖展示一來源電晶體群集之實施範例。反應於電路 守序°亥群木之使用允_電源被施加，因而全部的功率使 用可被減少，而不導致於電路操作中之不穩定性。經由範 例，該具體化電路展示用以控制分別的群組之來源電晶體 之非同步和同步信號的使用。但是，應了解，其他的機構 亦可被採用於控制分別族群之來源電晶體(例如，來自非同 15步及/或同步信號之延遲、延遲抵補，以及其類似者）。一第 一邏輯族群是以來源電晶體MNSG1 (電源）和MPSG1 (接地 源)表示’其反應於非同步資訊及/或控制信號，而利用來源 控制電路1被控制。一第二邏輯族群是以來源電晶體 MNSG2(電源）和MPSG2(接地源）表示，其反應於同步資訊 2〇 及/或控制信號，而利用來源控制電路2被控制。於這簡單 範例中，該第一邏輯族群接收一輸入信號並且產生被傳輸 經由第二邏輯族群之一輸出。 一個由於使用比同步信號較早先到達的非同步信號之 好處是提供用於來源電晶體之迅速的致動並且因此提供對 28 1290717 於邏輯操作之時序邊限。應了解，非同步信號之到達不能 被預估，且進一步地，即使當晶片是在閒置或備妥模式中 時，非同步信號狀態亦可能改變。 對於一邏輯族群（亦即，圖形中之邏輯族群1)，其是在 5 其他邏輯族群（亦即，圖形中之邏輯族群2)之前被引動，來 源電晶體狀態，例如，MNSG1和MPSG1，利用遭受來自非 同步資訊之控制的控制電路（亦即，來源控制電路1)被調變 以供迅速引動。該電路配置提供對於第二邏輯族群的另外 時序邊限，其中該來源電晶體可反應於同步資訊及/或控制 10 ^號之組合而被致動。於這範例中，僅當反應於開始進行 一有效操作的晶片時，該來源電晶體才供應電源至第二級 邏輯。 15 20 應了解’來源電晶體可被群聚成為更多於二個的群組 並且該方法是可修改供使用於如所展示之單_來源電晶體 及雙重電源和接地源電晶體。 雖然上面之說明包含許多細節，應可理解地，這些不 該是對本發明範圍之_，且其僅提供本發明目前一些較 佳實施例之展示。因此，熟習本技術者應明白，本發明範 =將完全地包含其他的實施例，並且因此除了所附力 1之申 請專利範圍之外，本發明範圍是不受任何之限制，於其中 茶考至—單—之元件不是有意地表示為‘‘-個並且僅是— 個”’除非因此明確地聲明，其指示為“―個或多個,，。孰習 本技=射轉，翁料於上述朗1㈣施例的 元件的&構和功能，於此處明確地配合參考並且是有音地 29 1290717 被包含於本申請内。此外，裝置或方法不必定針對本發明 哥求被解決之各個和每個問題，而其是被包含於本申請 内。更進一步地，於本揭示中，沒有元件、構件、或方法 步驟是有意地專用於公眾而無視於該元件、構件、或方法 5步驟是否明確地於申請專利範圍中被提出。於此處將沒有 申請元件可在35U.S.C.112規定第六段之下被理解，除非該 元件使用詞組“意指於，，明確地被提出。 廣義概要中，電路和方法被揭示以減少積體電路裝置 中漏損功率，該積體電路裝置中邏輯電晶體(例如，邏輯電 1〇路、鎖定器、及/或輸出級)是經由一個或多個可控制來源電 曰曰體被供電源。作為範例，該電路具有至少一個來源電晶 體(例如，電源、接地、或電源和接地兩者）用以選擇地供應 電源至在一積體電路裝置内之一級。一裝置用以反應於該 積體電路操作模式改變而調變該來源電晶體操作狀態以在 15導通該邏輯電晶體之前導通該來源電晶體，及/或在切斷該 邏輯電B曰體之後切斷該來源電晶體。於一論點中，在切斷 該邏輯電晶體之前的延遲可充分地被延伸以減少起因於短 週期不必要地導通和切斷該等來源電晶體之功率消耗。 【圖式簡單說明】 20 帛1岐具有用以減少備妥漏損之接地和來源電晶體 之習見MTCMOS電路的分解圖。 第2圖是具有用以減少備妥漏損之接地和來源電晶體 之習見自反向偏壓電路的分解圖。 第3圖是具有接地和來源電晶體用以減少備妥漏損之 30 1290717 CMOS鎖定器電路分解圖。 第4圖是依據本發明一論點之使用來源電晶體的電路 分解圖，其被展示而提供一種來源電晶體之提早-引動和延 後-不引動的組合。 5 第5圖是依據本發明一論點之第3圖展示的電路之時序 圖。 第6圖是依據本發明論點之使用來源電晶體的電路分 解圖，其被展示使用一種NMOS接地源電晶體。 第7圖是依據本發明論點之使用來源電晶體群集的電 10 路分解圖，其展示被控制之二群組邏輯。 【主要元件符號說明】 MNS…NMOS接地源電晶體 MNL···閘極信號 INV…電晶體電源線 OUT31…輸出節點 MPS···功率電晶體 31In the second embodiment, the circuit includes a -locker that retracts the memory m between access routes and when the access gate is turned on = the address information is retrieved from the locker. In the - mode, except for the normal access mode, the access route is cut off earlier than the normal mode and the address is stored elsewhere, and when the access path (4) a certain control signal or command is turned on The stored address information is used. Figure 7 shows an example of implementation of a source transistor cluster. Responsive to the circuit. The use of the power is applied. Therefore, the total power usage can be reduced without causing instability in the operation of the circuit. By way of example, the avatar circuit exhibits the use of non-synchronous and synchronizing signals to control the source transistors of the respective groups. However, it should be understood that other mechanisms may also be employed to control the source transistors of the respective populations (e.g., delays from different steps and/or synchronization signals, delay offsets, and the like). A first logical group is represented by source transistors MNSG1 (power supply) and MPSG1 (ground source), which are reacted to asynchronous information and/or control signals, and are controlled by source control circuit 1. A second logical group is represented by source transistors MNSG2 (power supply) and MPSG2 (ground source), which are controlled by the source control circuit 2 in response to the synchronization information 2 and/or control signals. In this simple example, the first logical group receives an input signal and produces a transmission that is transmitted via one of the second logical group. One benefit of using an asynchronous signal that arrives earlier than the sync signal is to provide rapid actuation for the source transistor and thus provide a timing margin for the logic operation of 28 1290717. It should be appreciated that the arrival of the asynchronous signal cannot be predicted, and further, the asynchronous signal state may change even when the wafer is in the idle or ready mode. For a logical group (ie, logical group 1 in the graph), it is motivated before 5 other logical groups (ie, logical group 2 in the graph), source transistor states, eg, MNSG1 and MPSG1, utilized A control circuit (i.e., source control circuit 1) that is subject to control from asynchronous information is modulated for rapid priming. The circuit configuration provides additional timing margins for the second logic group, wherein the source transistor can be actuated in response to a combination of synchronization information and/or control. In this example, the source transistor supplies power to the second stage logic only when reacting to the wafer that begins an efficient operation. 15 20 It should be understood that 'source transistors can be clustered into more than two groups and the method is modifiable for use with single-source transistors as shown and dual power and ground source transistors. Although the above description contains many specifics, it should be understood that these are not to be construed as limiting the scope of the invention. Therefore, it is to be understood by those skilled in the art that the present invention is to be construed as being limited to the scope of the invention, and the scope of the invention is not limited in any way. The elements of the singular-single are not intentionally expressed as ''- and only--' unless otherwise explicitly stated, the indication is "- or more."本 本 本 本 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射 射In addition, the apparatus or method is not necessarily intended to address the various and various problems that the present invention solves, and is included in the present application. Further, in the present disclosure, no component, component, or method step is deliberately dedicated to the public regardless of whether the component, component, or method 5 step is explicitly presented in the scope of the patent application. No application component is hereunder understood under the sixth paragraph of 35 USC 112 unless the component uses the phrase "meaning, is explicitly presented. In a broad overview, circuits and methods are disclosed to reduce the product. Leakage power in a bulk circuit device in which a logic transistor (eg, a logic circuit, a lock, and/or an output stage) is supplied via one or more controllable sources By way of example, the circuit has at least one source transistor (eg, power, ground, or both power and ground) for selectively supplying power to one of the stages within an integrated circuit device. The integrated circuit operation mode changes to change the source transistor operating state to turn on the source transistor before turning on the logic transistor, and/or to cut the source transistor after cutting the logic B body In one argument, the delay before the logic transistor is turned off can be sufficiently extended to reduce the power consumption of the source transistors that are unnecessarily turned on and off due to short periods. Brief Description: 20 帛1岐 has an exploded view of the MTCMOS circuit used to reduce the grounding and source transistors for proper leakage. Figure 2 is a view of the grounding and source transistors used to reduce the prepared leakage. An exploded view of the self-reverse bias circuit. Figure 3 is an exploded view of the 30 1290717 CMOS locker circuit with ground and source transistors to reduce read-out leakage. Figure 4 is a source of use in accordance with one aspect of the present invention. A circuit exploded view of a transistor that is shown to provide a combination of early-priming and post-latching-non-priming of a source transistor. 5 Figure 5 is a timing diagram of the circuit shown in Figure 3 of an argument of the present invention. Figure 6 is an exploded view of a circuit using a source transistor in accordance with the teachings of the present invention, which is shown using an NMOS grounded source transistor. Figure 7 is an exploded view of an electrical circuit using a source transistor cluster in accordance with the teachings of the present invention. It shows the controlled group logic. [Main component symbol description] MNS...NMOS ground source transistor MNL···gate signal INV...transistor power line OUT31...output node MPS···power transistor Body 31