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WO2004032229A1 - Procede de fabrication d'un module haute frequence - Google Patents

Procede de fabrication d'un module haute frequence Download PDF

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Publication number
WO2004032229A1
WO2004032229A1 PCT/JP2003/011254 JP0311254W WO2004032229A1 WO 2004032229 A1 WO2004032229 A1 WO 2004032229A1 JP 0311254 W JP0311254 W JP 0311254W WO 2004032229 A1 WO2004032229 A1 WO 2004032229A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
layer
wiring layer
module device
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/011254
Other languages
English (en)
Japanese (ja)
Inventor
Tsuyoshi Ogawa
Takahiko Kosemura
Akira Muto
Akihiko Okubora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to US10/496,878 priority Critical patent/US7183135B2/en
Publication of WO2004032229A1 publication Critical patent/WO2004032229A1/fr
Anticipated expiration legal-status Critical
Priority to US11/710,785 priority patent/US7741162B2/en
Ceased legal-status Critical Current

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions

  • the present invention relates to a method for manufacturing a high-frequency module device including a high-frequency circuit unit provided with a passive element, and more particularly to a method for manufacturing a high-frequency module device that is reduced in size and thickness. .
  • data transmission / reception systems are used in various ways by proposing suitable network systems even in small areas such as homes.
  • a network system for example, 5G as proposed in IEEE802.11a
  • next-generation wireless systems such as a wireless LAN system in the GHz band or a short-range wireless communication system called a blue tooth, have attracted attention.
  • the data transmission / reception system enables such a wireless network system.
  • the high-frequency transmission / reception circuit 100 shown in FIG. 1 includes an antenna unit 101 having an antenna and a switching switch for receiving or transmitting an information signal, and a transmission / reception switch 100 for switching between transmission and reception. 2 is provided.
  • the high-frequency transmission / reception circuit 100 is provided with a reception circuit unit 105 including a frequency conversion circuit unit 103, a demodulation circuit unit 104, and the like.
  • the high-frequency transmission / reception circuit 100 includes a transmission circuit unit 109 including a power amplifier 106, a drive amplifier 107, a modulation circuit unit 108, and the like.
  • the high-frequency transmission / reception circuit 100 is provided with a reference frequency generation circuit for supplying a reference frequency to the reception circuit 105 and the transmission circuit 109.
  • the high-frequency transmitting / receiving circuit 100 having the above-described configuration, various filters and local oscillators (VCOs) interposed between the respective stages are used. ), Large functional components such as S AW filters (Surface Acoustic Wave), and passive components such as inductance, resistance, and capacitance that are unique to high-frequency analog circuits such as matching circuits or bias circuits. There are many configurations. Therefore, the high-frequency transmission / reception circuit 100 becomes large in size as a whole, which has been a major obstacle to reducing the size and weight of communication terminal equipment.
  • VCOs local oscillators
  • a high-frequency transmission / reception circuit 110 of a direct conversion system for transmitting / receiving information signals without conversion to an intermediate frequency is also used for the communication terminal equipment.
  • the information signal received by the antenna unit 111 is supplied to the demodulation circuit unit 113 via the transmission / reception switch 112, and the baseband processing is directly performed.
  • High frequency transmission / reception circuit 1 1 0 the information signal generated by the source source is directly modulated into a predetermined frequency band without being converted to an intermediate frequency in the modulation circuit section 114, and the amplifier 115 and the transmission / reception switch 112 are transmitted to the modulation circuit section 114. Sent from the antenna section 111 via
  • the high-frequency transmission / reception circuit 110 configured as described above, since the information signal is transmitted and received by performing direct detection without converting the intermediate frequency, the number of components such as filters is reduced. As a result, the overall configuration is simplified, and a configuration closer to one chip is expected. However, the high-frequency transmission / reception circuit 110 also needs to be compatible with a filter or a matching circuit arranged at a subsequent stage. In addition, since the high-frequency transmission / reception circuit 110 performs amplification once in the high-frequency stage, it is difficult to obtain a sufficient gain, and it is necessary to perform an amplification operation also in the baseband section. Therefore, the high-frequency transmitting / receiving circuit 110 requires a DC offset canceling circuit and an extra low-pass filter, and further has a problem that the overall power consumption increases.
  • a large concave portion 124 is formed corresponding to the inductor forming portion 123 of the Si substrate 121 and the Si02 insulating layer 122.
  • the high frequency circuit board to form a first wiring layer 1 2 5 to face the concave portion 1 2 4, the second wiring layer 1 2 6 is formed on S i 0 2 insulating layer 1 2 2 To form the coil section 127.
  • part of the wiring pattern is raised from the board surface as an alternative, and By adopting a configuration that floats inside, the Indak-Yaku 120 was formed.
  • a high-frequency module apparatus 130 'using a Si substrate shown in FIG. 4 and a high-frequency module apparatus 140 using a glass substrate shown in FIG. Has been proposed.
  • the passive element layer 133 is formed by a thin film forming technique such as a luffy technique.
  • the passive element layer 133 is not described in detail, but the passive element section 135 such as an inductor, a register, or a capacitor is provided together with the wiring layer 134 inside. It is formed in multiple layers with an insulating layer 136 interposed.
  • a terminal portion 1337 connected to the wiring layer 134 via a via (through hole) or the like is formed on the passive element layer 133. It has a configuration in which functional elements 138 such as high-frequency ICs and LSIs are mounted by flip-chip mounting.
  • the high-frequency circuit portion and the baseband circuit portion are separated from each other, and the electrical interference between them is suppressed.
  • the base substrate 131 is a conductive Si substrate. This may hinder the good high-frequency characteristics of the passive element section 135.
  • the high-frequency module device 140 shown in FIG. 5 has a glass substrate on the base substrate 141 in order to solve the problem of the base substrate 131 in the high-frequency module device 130 shown in FIG. Used.
  • High-frequency module device 140 The passive element layer 142 is formed on the base substrate 141 by, for example, a thin film forming technique.
  • the passive element section 144 such as an inductor, a resistor, or a capacitor is formed inside the insulating layer 1 together with the wiring layer 144. It is formed in multiple layers through 45.
  • terminal portions 1 4 6 connected to the wiring layer 1 4 3 via vias or the like are formed on the passive element layer 1 4 2, and these terminal portions 1 4 6 Functional elements 147 such as high-frequency ICs and LSIs are directly mounted by flip-chip mounting.
  • This high-frequency module device 140 uses a non-conductive glass substrate for the base substrate 14 1, so that the degree of capacitive coupling between the base substrate 14 1 and the passive element layer 14 2 is suppressed, and the passive element A passive element portion 144 having good high-frequency characteristics is formed in the layer 144.
  • a terminal pattern is formed on the surface of the passive element layer 142 to be mounted on a mother board or the like, and a connection to the mother board is made by a wire bonding method or the like. Is performed.
  • high-precision passive element layers 13 3 and 14 2 are formed on the base substrates 13 1 and 14 1 as described above.
  • Base substrate 13 1, 14 1 when forming a passive element layer as a thin film, heat resistance against surface temperature rise during sputtering, maintaining depth of focus during lithography, contact alignment during masking Characteristics are required.
  • the base substrates 13 1 and 14 41 are required to have high-precision flatness for this purpose, as well as insulation, heat resistance, chemical resistance, and the like. Since the base substrates 13 1 and 14 41 described above are Si substrates or glass substrates, they have such characteristics, and enable low-cost, low-loss passive elements to be formed by a separate process from LSI. .
  • the base substrate 131, 141 the method of forming a pattern by printing or the like used in the conventional ceramic module technology, or forming a wiring pattern on a printed wiring board Compared to the wet etching method, it is possible to form a passive element with higher precision and to reduce the element size to about 110,000 of its area.
  • the use limit frequency of the passive element can be increased to 20 GHz or more by using a Si substrate or a glass substrate for the base substrates 13 1 and 14 1. is there.
  • the high-frequency signal system is provided via the wiring layers 134 and 144 formed on the base substrates 131 and 141 as described above. Pattern formation, and power supply and ground supply wiring or control system signal wiring.
  • the high-frequency module devices 130 and 140 electric interference occurs between the wirings, and the cost increases due to the formation of the wiring layers in multiple layers, and the wiring increases in size, leading to problems such as an increase in size.
  • the cost increases because relatively expensive Si substrates and glass substrates are used for the base substrates 13 1 and 14 1.
  • these high-frequency module devices 130 and 140 are mounted on a main surface of a mother board 150 as so-called one-chip components.
  • the high-frequency module device 130 will be described with reference to the drawings.
  • the high-frequency module device 130 is mounted on one surface, and a shield cover 151, made of insulating resin or the like, covering the entire high-frequency module device 130 is also mounted. ing.
  • pattern wiring and input / output terminal portions are formed on both sides of the mother substrate 150, and a large number of land portions 1502 are provided around the mounting area of the high-frequency module device 130. Are formed.
  • the wiring layer 134 and the land portion 152 of the high-frequency module device 130 are electrically connected to the land portions 152 by wires 153 by wire bonding. Power supply and signal transmission / reception to the high-frequency module device 130.
  • the high-frequency module device 140 is similarly mounted on the mother board 150.
  • the passive element layer 133 is disposed on the mother substrate 150 via the base substrate 131, so that it is large in the thickness direction. There was also a problem of becoming. Further, in the high-frequency module device 130 mounted on the mother board 150, it is difficult to provide a wiring structure in the base board 131, and the land portion 1 for supplying power to the surroundings is difficult. There is also a problem that the size is increased in the plane direction because many 52 are arranged.
  • a high-frequency module device 160 as shown in FIG. 7 has been proposed (see Japanese Patent Application Laid-Open No. 2002-92447).
  • the device 160 is a device in which the main surface of a base substrate 161 made of an organic wiring substrate or the like is subjected to a planarization process, and the main surface of the highly planarized base substrate 161 is subjected to a passive element by a thin film forming technique or the like.
  • the structure is such that a high-frequency element layer portion 162 having the same is formed.
  • the supply of electricity and signals to the high-frequency element layer section 162 can be performed without using the wires 153 in the high-frequency module apparatus 150 described above. Since it can be performed with the base substrate 161, which is an organic wiring substrate, power supply with high regulation can be performed. Further, in the high-frequency module device 160, since the base substrate 161 is an organic wiring substrate, the cost can be reduced as compared with the case where an Si substrate or a glass substrate is used as the base substrate.
  • the high-frequency element layers 162 are sequentially laminated on one surface of the base substrate 161, and the high-frequency element layers 162, which are expensive to manufacture, are formed. Since it is formed on the entire main surface of the base substrate 161, it is difficult to further reduce the size and cost.
  • An object of the present invention is to provide a manufacturing method capable of manufacturing a novel high-frequency module device that can solve the problems of the conventional technology as described above.
  • Another object of the present invention is to provide a method of manufacturing a high-frequency module device that enables a passive element and a wiring portion to be formed with high accuracy.
  • Still another object of the present invention is to provide a high-frequency module device that is reduced in size and price.
  • An object of the present invention is to provide a manufacturing method that can be manufactured.
  • the method for manufacturing a high-frequency module device is a method for manufacturing a high-frequency module device, comprising: a wiring layer partially provided with a passive element on a flattened surface of a substrate; and a unit wiring layer having an insulating layer.
  • the high-frequency circuit section in which a plurality of unit wiring layers are formed on one flattened surface of the dummy substrate is provided with the wiring layer exposed on the uppermost surface of the unit wiring layer and the base substrate.
  • the dummy substrate is removed from the high-frequency circuit portion to thereby determine a predetermined surface of one surface of the base substrate.
  • a high-frequency module device having a configuration in which a high-frequency circuit portion is mounted in the range of (1) is manufactured.
  • the high-frequency module device since the high-frequency circuit portion is formed on one flattened surface of the dummy substrate, the high-frequency module device on which the wiring layer having the passive element is accurately formed is manufactured. it can.
  • FIG. 1 is a block circuit diagram showing a high-frequency transmitting / receiving circuit based on a superheterodyne method.
  • FIG. 2 is a block circuit diagram showing a high-frequency transmission / reception circuit using the direct comparison method.
  • FIG. 3A and 3B are views showing an inductor provided on a conventional high-frequency circuit board
  • FIG. 3A is a perspective view of a main part thereof
  • FIG. 3B is a longitudinal sectional view of the main part thereof.
  • FIG. 4 is a longitudinal sectional view showing a configuration of a conventional high-frequency module device using a silicon substrate as a base substrate.
  • FIG. 5 is a longitudinal sectional view showing a configuration in which a glass substrate is used as a base substrate of the high-frequency module device.
  • FIG. 6 is a longitudinal sectional view showing a state where the high-frequency module device is mounted on a mother board.
  • FIG. 7 is a longitudinal sectional view showing a configuration in which an organic wiring substrate is used as a base substrate of the high-frequency module device.
  • FIG. 8 is a cross-sectional view showing one example of a high frequency module device manufactured by the method of manufacturing a high frequency module device to which the present invention is applied.
  • FIG. 9 is a view for explaining the method for manufacturing the high-frequency module device according to the present invention, and is a longitudinal sectional view showing a dummy substrate.
  • FIG. 10 is a longitudinal sectional view showing a state where the first insulating layer is formed on the dummy substrate.
  • FIG. 11 is a longitudinal sectional view showing a state in which a first wiring groove is formed in the first insulating layer.
  • FIG. 12 is a longitudinal sectional view showing a state where a metal plating layer is formed on the first insulating layer.
  • FIG. 13 is a longitudinal sectional view showing a state where the first unit wiring layer is formed.
  • FIG. 14 is a vertical cross-sectional view showing a state in which a receiving electrode portion is formed on the first unit wiring layer.
  • FIG. 15 is a longitudinal sectional view showing a state where a passive element portion is formed on the first unit wiring layer.
  • FIG. 16 is a longitudinal sectional view showing a state where the second unit wiring layer is formed on the first unit wiring layer.
  • FIG. 17 is a vertical cross-sectional view showing a state where a passive element portion is formed on the second unit battle layer.
  • FIG. 18 is a longitudinal sectional view showing a state where a high-frequency circuit section is formed on a dummy substrate.
  • FIG. 19 is a longitudinal sectional view showing a state where a pump section is formed on the high-frequency circuit section.
  • FIG. 20 is a longitudinal sectional view showing a state where the high-frequency circuit section is mounted on the base substrate.
  • FIG. 21 is a longitudinal sectional view showing a high-frequency module device manufactured by the method of the present invention.
  • FIG. 22 is a view for explaining a step of mounting a functional element on a high-frequency module device manufactured by the method of the present invention, and is a longitudinal sectional view showing a state where a base portion is formed on a high-frequency circuit portion. .
  • FIG. 23 is a view for explaining a step of mounting the functional element on the high-frequency module device, and is a longitudinal sectional view showing a state where the functional element is mounted on the high-frequency circuit unit.
  • FIG. 24 is a view for explaining a step of mounting the functional element on the high-frequency module device, and is a longitudinal sectional view showing a state where a resin layer covering the functional element is formed.
  • FIG. 25 is a view for explaining a step of mounting the functional element on the high-frequency module device, and is a longitudinal sectional view showing a state in which the functional element and the resin layer are polished.
  • FIG. 26 is a longitudinal sectional view showing a state where the shield cover and the thermally conductive resin material are assembled to the high-frequency module device.
  • FIG. 27 is a longitudinal sectional view showing a state where cooling vias are formed inside the base substrate of the high-frequency module device.
  • FIG. 28 is a longitudinal sectional view showing a state where a metal core is provided inside a base substrate of the high-frequency module device.
  • the high-frequency module device 1 shown in FIG. 8 configures a high-frequency circuit that performs high-frequency signal exchange processing and the like by a superheterodyne method, a direct conversion method, or the like in a transmitting / receiving section provided in a mobile communication terminal device or the like. I have.
  • This high-frequency module device 1 has a configuration in which a high-frequency circuit board on which a high-frequency circuit section 2 is formed is electrically connected to a base substrate 3 by a bump section 4 made of, for example, solder and mounted.
  • a second unit wiring layer 6 is formed below one surface of the first unit wiring layer 5, and a third unit wiring layer is formed below one surface of the second unit wiring layer 6.
  • the wiring layer 7 is formed.
  • Each of the first to third unit wiring layers 5 to 7 includes an insulating layer and a pattern wiring.
  • the first unit wiring layer 5 to the third unit wiring layer 7 are electrically connected to each other by vias 8 penetrating through all layers or through upper and lower layers.
  • one surface of the first unit wiring layer 5 to the third unit wiring layer 7 is subjected to a flattening process by a mechanical polishing method (CMP).
  • CMP mechanical polishing method
  • a via-on-via structure in which the vias 8 of the first unit wiring layer 5 and the vias 8 of the second unit wiring layer 6 overlap each other is possible. It has been.
  • CMP mechanical polishing method
  • the high-frequency circuit section 2 is provided on one surface (hereinafter, referred to as a connection surface) 2 b opposite to the base substrate 3, on the other surface 2 b opposite to 2 a, for example, a semiconductor chip or an LSI (Large-scale Integrated).
  • a functional element 9 such as a chip or a surface-mount component (not shown) is electrically connected to the pattern wiring of the first unit wiring layer 5 by an element bump 10 formed by a flip chip bonding method or the like. It is connected.
  • a resin layer 11 is formed on one surface of the first unit wiring layer 5 so as to fill the periphery of the functional element 9, and the functional element 9 and the resin layer 11 are formed.
  • the overall thickness is reduced by performing the polishing process.
  • the high-frequency circuit section 2 includes patterns in the first unit wiring layer 5 to the third unit wiring layer 7. Passive elements such as capacitors 12, resistors 13, and inductors 14 are formed at predetermined locations on the wiring.
  • the capacitor 12 is, for example, a decoupling capacitor or a DC cutting capacitor, and is formed as a thin film with a tantalum oxide (T a O) film.
  • the resistor 13 is, for example, a resistor for a terminating resistor, and is formed as a thin film with a tantalum nitride (TaN) film.
  • the high-frequency circuit section 2 since the surfaces of the first unit wiring layer 5 to the third unit wiring layer 7 are flattened, such passive elements can be formed with high accuracy. It is. As described above, in the high-frequency circuit section 2, a small-sized and high-performance passive element is used because the capacitors 12 and the like are precisely formed as thin films in each unit wiring layer without using a semiconductor chip or the like. Will be installed.
  • the high-frequency circuit unit 2 is formed by sequentially laminating a first unit wiring layer 5 to a third unit wiring layer 7 on a dummy substrate 30 having a flat surface via a peeling layer 31. This is formed by removing the dummy substrate 30 and the release layer 31. Therefore, in the high-frequency circuit section 2, only necessary portions can be formed on the dummy substrate 30. Since the high-frequency circuit section 2 does not use a base substrate such as a glass substrate or a Si substrate, the cost can be significantly reduced as compared with the related art.
  • a plurality of wiring layers 15 are formed between the respective layers via an insulating layer 16, and the plurality of wiring layers 15 are formed as via holes 17 penetrating through all the layers or through the plurality of layers. It is connected between layers.
  • the base substrate 3 is provided with a plurality of input / output terminal portions 18 on each of the front and rear surfaces. Functions as the base for Part 4.
  • the plurality of wiring layers 15 function as wiring for transmitting power, control signals, high-frequency signals, and the like supplied from the input / output terminal section 18 to the high-frequency circuit section 2, and a ground. (Ground electrode) Also functions as 19.
  • the insulating layer 16 may be made of a material having a low dielectric constant and a low T an ⁇ 5, that is, a material having excellent high frequency characteristics, such as polyphenylene ether (PPE), bismaleide triazine (BT- resin), polytetrafluoroethylene, polyimide, liquid crystal polymer (LCP), polynorpolene (PNB), phenolic resin, organic material such as polyolefin resin, inorganic material such as ceramic, or glass epoxy. A mixture of an organic material such as silicon and an inorganic material is used.
  • PPE polyphenylene ether
  • BT- resin bismaleide triazine
  • LCP liquid crystal polymer
  • PBN polynorpolene
  • phenolic resin organic material such as polyolefin resin
  • inorganic material such as ceramic, or glass epoxy.
  • a mixture of an organic material such as silicon and an inorganic material is used.
  • the base substrate 3 is manufactured through a general multi-layer wiring board manufacturing process.
  • the high-frequency circuit unit 2 is manufactured.
  • a dummy substrate 30 having a release layer 31 formed on one surface 30a is prepared.
  • the dummy substrate 30 for example, a glass substrate, a quartz substrate, a Si substrate, or the like, which has high heat resistance and whose main surface is highly planarized, is used.
  • the release layer 31 has a thickness of about 100 A over the entire main surface 30 a of the dummy substrate 30 by a thin film forming technique such as a sputtering method or a chemical vapor deposition (CVD) method.
  • a metal film 31a such as copper or aluminum formed to a uniform thickness, and a film thickness of about 1 um to 2m is formed on the entire surface of the metal film 31a by spin coating or the like. It is composed of a resin film 31 b of polyimide resin or the like.
  • the first insulating layer 32 is formed on the release layer 31 to have a uniform thickness.
  • the first insulating layer 32 is formed using an insulating dielectric material generally known in a conventional wiring board manufacturing process.
  • the first insulating layer 32 has a low dielectric constant and a low Tan 5, that is, excellent in high frequency characteristics, such as polyphenylene ether (PPE), bismaleid triazine (BT-resin), and liquid crystal polymer (LCP). ), Polynorpolene (PNB), bismaleidotriazine (BT-resin), polyimide, benzocyclobutene (BCB), epoxy resin, acrylic resin, and other insulating dielectric materials.
  • PPE polyphenylene ether
  • BT-resin bismaleid triazine
  • LCP liquid crystal polymer
  • PNB Polynorpolene
  • BT-resin bismaleidotriazine
  • BCB benzocyclobutene
  • epoxy resin acrylic
  • an opening 32a to be the via 8 is formed at a predetermined position by a patterning process.
  • the opening 32 a is formed by subjecting the first insulating layer 32 to a patterning process.
  • the opening 32a is formed by performing a patterning process using a photolithographic technique.
  • the opening 32 a is made of a photoresist or aluminum when a non-photosensitive insulating dielectric material is used for the first insulating layer 32.
  • a patterning process is performed by dry etching, laser processing, or the like using a mask of, for example, nickel.
  • the first insulating layer 32 is subjected to an etching process to form a first wiring groove 33.
  • an etching mask having an opening corresponding to the pattern of the first wiring groove 33 is formed on the first insulating layer 32, and the etching mask of the first insulating layer 32 is formed.
  • the region is formed by removing the etching mask after performing dry etching such as reactive ion etching (RIE) using oxygen plasma in a region other than the region.
  • RIE reactive ion etching
  • a metal plating process is performed on the first insulating layer 32 in which the first wiring groove 33 is formed, so that the metal plating layer 3 4 is formed. Is formed.
  • the metal plating layer 34 is formed of a highly conductive metal such as copper. Either electrolytic plating or electroless plating may be used for the metal plating, and the entire main surface of the first insulating layer 32 where the first wiring groove 33 is provided and the opening 3 2a Is applied so that the thickest part of the metal plating layer 34 is thicker than the thickest part of the first insulating layer 32. In the metal plating process, when the metal plating layer 34 is formed by electrolytic plating, the metal film 31a of the release layer 31 functions as a voltage application electrode.
  • the main surface of the first insulating layer 32 is subjected to a flattening process on the metal plating layer 34 until the first insulating layer 32 is exposed.
  • the first pattern wiring 35 is formed.
  • the first insulating layer 32 and the first pattern wiring 35 are formed, and the first surface having the main surface 5 a which is highly planarized by the planarization process is provided.
  • the unit wiring layer 5 is formed.
  • the first insulating layer 32 and the metal plating layer 34 which are made of different materials, are simultaneously polished, so that a CMP (Chemical Mechanical Polishing) method is used. .
  • This CMP method can selectively polish the material so as to increase the polishing rate of the metal plating layer 34 made of metal such as copper, and flatten the polished surface with high precision. .
  • the first insulating layer 32 is a dummy substrate 3 on which the first insulating layer 32 is flattened with high precision. Since the thickness of the first insulating layer 32 formed on the main surface 30a of the first pattern does not vary, the defocus of the patterning image due to the photolithographic processing is suppressed, and the first pattern wiring is formed. It is possible to form the holes 35 and the vias 8 with high accuracy.
  • the first unit wiring layer 5 thus formed is formed in a state in which the first pattern wiring 35 is embedded in the first insulating layer 32, and the main surface 5a is formed by the CMP method.
  • the via 8 is also formed at a time.
  • the via 8 is formed with a highly accurate flattened end exposed on the main surface 5 a of the first unit wiring layer 5.
  • the electrical connection with the wiring layer 6 can be made vias 8, that is, the via-on-via structure described above. With this via-on-one via structure, electrical connection between the unit wiring layers can be performed in the shortest time, and the area of the high-frequency circuit unit 2 can be reduced.
  • a lower electrode of the capacitor 12 and a receiving electrode serving as a receiving electrode of the resistor 13 are provided on one surface 5 a of the first unit wiring layer 5, as a passive element portion.
  • the electrode part 36 is formed.
  • a first metal film made of a metal such as titanium is formed on the main surface 5 a of the first unit wiring layer 5 having the via 8 over the entire surface.
  • a film is formed to a thickness of about 0 A by a sputtering method, an evaporation method, or the like.
  • a second metal film made of a metal such as Cu, Al, Au, or Pt is formed to a thickness of about 2000 A over the entire surface of the metal film.
  • a mask is formed on the main surface of the second metal film in a region where the electrode receiving portion 36 is to be formed, and an unmasked region is subjected to an etching process.
  • This etching process is performed by, for example, wet etching using a mixed acid obtained by mixing nitric acid, sulfuric acid, acetic acid and the like at a predetermined ratio as an etchant.
  • the etchant made of the mixed acid is less corrosive to titanium metal, the etching is performed until the first metal film is exposed, so that only the unmasked second metal film is corroded. Can be.
  • an etching process is performed on the unmasked first metal film.
  • This etching treatment is performed, for example, by using a mixed acid obtained by mixing ammonium fluoride and ammonium hydrogen difluoride at a predetermined ratio as an etchant, CF etching, or CF etching. 4 This is performed by plasma etching using plasma or the like. In this etching treatment, only the first metal film can be corroded because the corrosiveness in the etchant or CF 4 plasma is lower than metals other than titanium metal. In this way, on the first unit wiring layer 5, the receiving electrode portion 36 composed of the first metal film and the second metal film is formed.
  • a capacitor 12 and a resistor 13 are formed as passive element sections so as to be connected to the receiving electrode section 36.
  • a tantalum nitride (TaN) film is formed on the entire surface 5a of the first unit wiring layer 5 so as to cover the receiving electrode portion 36. I do.
  • This T a N film is a base film of a tantalum oxide (T a O) dielectric film that becomes a capacity 12 by anodic oxidation.
  • a method for forming the T aN film for example, a sputtering method capable of forming a film to a thickness of about 2000 A is preferable.
  • a mask for anodizing only the portion where the capacitor 12 and the resistor 13 are to be formed is formed on the TAN layer.
  • the TAN layer facing outward from the mask opening is anodized.
  • the TAN layer facing outward from the opening a of the mask is anodized.
  • the TaN layer is oxidized by applying a voltage of 50 to 200 V so that TaN becomes an anode in an electrolytic solution such as borated ammonium.
  • a T a O layer is formed.
  • the TaO layer can be formed to a desired thickness by adjusting the voltage applied to the TaN layer.
  • the mask formed on the anodized TaN layer is removed.
  • the TaO layer in which the surface of the TaN layer is selectively oxidized can be used as the dielectric material of the capacitor 12.
  • dry etching or the like is performed on the T aO layer while the formation site of the capacitor 12 and the resist 13 is masked with the resist 1 and the like, and the mask is removed to remove the capacitor 12 and the resist 13.
  • Three dielectric films 37 are formed at the same time.
  • passive element sections such as the capacitor 12 and the register 13 are formed. Since these passive element portions are formed on the main surface 5a of the first unit wiring layer 5, which is flattened with high accuracy, they can be formed with high accuracy and improve high-frequency characteristics. It is possible.
  • the capacity 12 may be formed by using, for example, a BST (Ba, SR, Ti, 0) film or an STO (Sr, Ti, O) film as the dielectric film 37.
  • an upper electrode section 38 is formed on the capacitor 12.
  • the upper electrode portion 38 is formed by, for example, forming a metal film such as Al, Cu, Pt, and Au through an underlayer such as Cr, Ni, and Ti for improving adhesion. ing.
  • the upper electrode section 38 has a thickness of about 2000 A by sputtering or the like so as to cover the passive body section on the first unit wiring layer 5.
  • the film is formed into a predetermined pattern shape by masking, etching and the like.
  • a second unit wiring layer 6 is formed on the first unit wiring layer 5 so as to cover the passive element formed on the one surface 5a. Is done.
  • the second unit wiring layer 6 is formed by using the same material as the first unit wiring layer and performing the same steps.
  • the second unit wiring layer 6 includes a second insulating layer 39 and a second pattern wiring 40.
  • the second insulating layer 39 has a high-precision flattened first insulating layer. Since there is no variation in the thickness of the second insulating layer 39 formed on the unit wiring layer 5, the shift of the focus of the pattern ing image by the photolithographic processing is suppressed, and the second pattern wiring 40 Via 8 can be accurately formed.
  • the second unit wiring layer 6 is formed on one surface 5a of the first unit wiring layer 5 which is flattened with high precision, the second pattern wiring 40 is formed with high precision. Has been done.
  • the one surface 6a of the second unit wiring layer 6 facing the pattern wiring 40 has been subjected to the flattening process by the above-described CMP method, and has one surface 5a of the first unit wiring layer 5. Similarly, it is flattened with high precision.
  • a capacitor 41 is formed as a passive element portion.
  • the capacity 41 is formed through the same forming process as the capacity 12 formed on the one surface 5 a of the first unit wiring layer 5. Since the capacitor 41 is also formed on the main surface 6a of the second unit wiring layer 6, which is flattened with high precision, the capacitor 41 is formed with high accuracy and the high-frequency characteristics are improved.
  • the third insulating layer is formed on the main surface 6a of the second unit wiring layer 6 in the same procedure as the formation of the first unit wiring layer 5.
  • a third unit wiring layer 7 composed of 42 and the third pattern wiring 43 is formed.
  • the third unit wiring layer 7 is formed on one surface 6 a of the second unit wiring layer 6 that has been planarized with high precision, the third pattern wiring 43 and the vias 8 are formed. Is formed with high accuracy. it can. Further, in the third unit wiring layer 7, the inductor 14 is precisely formed in a pattern on a part of the third pattern wiring 43.
  • the high-frequency circuit unit 2 in which the connection surface 2a to the base substrate 3, which is the uppermost layer, is flattened with high precision is manufactured.
  • the thus-prepared frequency circuit section 2 only necessary portions of each unit wiring layer having high-precision pattern wiring can be formed on one surface 30a of the dummy substrate 30. The size and cost can be reduced.
  • the unit wiring layer has a three-layer structure, but is not limited to this, and the unit wiring layer is formed by repeating the process of forming the first unit wiring layer 5. Having three or more layers.
  • the pattern wiring of each unit wiring layer is formed so as to be embedded in the insulating layer.
  • the present invention is not limited to this.
  • a conventional thin film forming method such as a semi-additive method is used. It is also possible to form pattern wiring by technology.
  • a bump section 4 made of, for example, solder is formed at a predetermined position of the third pattern wiring 43 exposed on the connection surface 2a.
  • the bump portion 4 functions as an electrical connection portion when the high-frequency circuit portion 2 is mounted on the base substrate 3, and may be formed as a nickel-copper plating layer by, for example, electrolytic plating or electroless plating. Since the dummy substrate 30 is used as a support substrate in the high-frequency circuit section 2, the state is not bent, and the bump section 4 can be accurately formed on the connection plane 2a that has been flattened with high precision. It becomes.
  • the high-frequency circuit unit 2 is turned over so that the connection surface 2 a and the base substrate 3 are opposed to each other, and on the base substrate 3 together with other semiconductor chips 44.
  • the base substrate 3 has a plurality of wiring layers 15 having a ground portion 19 and the like in the layer, and a resist or the like is mounted on a mounting surface 3a which is one surface on which the high-frequency circuit portion 2 and the like are mounted.
  • a mounting surface 3a which is one surface on which the high-frequency circuit portion 2 and the like are mounted.
  • an input / output terminal portion 18 exposed from the formed protective layer 45 is formed.
  • the high-frequency circuit 2 is electrically connected to the input / output terminal 18 exposed on the mounting surface 3 a of the base substrate 3 via the bump 4 formed on the connection surface 2 a.
  • it is mounted on the base substrate 3.
  • an underfill 46 is filled between the high-frequency circuit section 2 and the base substrate 3 in a state where the bump section 4 and the input / output terminal section 18 face each other.
  • the input / output terminal 18 and the bump 4 are electrically connected to each other, and the high-frequency circuit 2 is mounted on the mounting surface 3 a of the base substrate 3.
  • the dummy substrate 30 is removed together with the release layer 31 from the high-frequency circuit section 2. More specifically, the dummy substrate 30 and the release layer 31 are immersed in an acidic solution such as hydrochloric acid or nitric acid together with the high-frequency circuit section 2 and the base substrate 3 so that the acidic solution forms the release layer 31. While slightly dissolving the metal film 31a, it penetrates between the metal film 31a and the resin film 31b, and the peeling proceeds between the metal film 31a and the resin film 3lb. The dummy substrate 30 is removed with the resin film 31b remaining on the other surface 2b opposite to the connection surface 2a. Further, the dummy substrate 30 may be removed from the high-frequency circuit unit 2 by, for example, a laser ablation process.
  • an acidic solution such as hydrochloric acid or nitric acid
  • the resin film 31b remaining on the other surface 2b of the high-frequency circuit section 2 is removed by, for example, a dry etching method using oxygen plasma.
  • the via 8 is exposed on the other surface 2 b of the high-frequency circuit section 2. Since the main surface 30a of the dummy substrate 30 facing the high-frequency circuit section 2 is highly flattened, the other surface 2a of the dummy substrate 30 facing the one surface 30a b will also be highly flattened. In addition, the dummy substrate 30 is reused as needed.
  • the high-frequency module device 1 including the high-frequency circuit unit 2 and the base substrate 3 is manufactured.
  • the first unit wiring layer 5 to the third unit wiring layer 7 are stacked and formed on the flattened main surface 30 a of the dummy substrate 30.
  • the high-frequency circuit portion 2 is exposed on the mounting surface 3a of the base substrate 3 on the third pattern wiring 43 exposed on the connection surface 2a of the high-frequency circuit portion 2 and on the mounting surface 3a of the base substrate 3.
  • the high-frequency circuit section 2 is mounted in a predetermined range of the mounting surface 3a of the base substrate 3.
  • the high-frequency circuit section 2 is formed on the flattened surface 30a of the dummy substrate 30, the passive elements such as the capacitor 12, the resistor 13 and the inductor 14 are formed. And pattern wiring can be formed with high precision, and the wiring can be arranged with high density to reduce the area and improve the high-frequency characteristics.
  • the high-frequency circuit section 2 having high-precision pattern wiring is formed only on the main surface 30a of the dummy substrate 30 so that the high-frequency circuit section 2 has a necessary portion. Can be mounted on the mounting surface 3 a of the base substrate 3, so that miniaturization and cost reduction can be achieved.
  • a plurality of wiring layers 15 functioning as a ground portion 19 and wires for transmitting power, a control signal, a high-frequency signal, and the like to the high-frequency circuit portion 2 are provided to the high-frequency circuit portion 2. Since it is provided inside the base substrate 3 and does not require a land or a wire for supplying power around the high-frequency circuit section on the mounting surface of the base substrate, for example, it is required to be modified. A smaller area can be achieved.
  • the high-frequency circuit section 2 laminated on the main surface 30a of the dummy substrate 30 is inverted and mounted on the base substrate 3 together with the dummy substrate 30 so that precision components can be used.
  • the handling of a certain high-frequency circuit unit 2 is facilitated, and the yield in manufacturing can be improved.
  • the high-frequency module device 1 is mounted with a functional element 9 such as a semiconductor chip or an LSI chip.
  • a resist layer 47 covering the other surface 2b of the high-frequency circuit unit 2 is formed as shown in FIG.
  • the resist layer 47 includes, for example, a solder resist or an insulating dielectric material. Is used.
  • the resist layer 47 is subjected to photolithographic processing through a mask patterned into a predetermined shape to form an opening 47a in which the via 8 faces a predetermined position.
  • electroless nickel copper plating is applied to form a base 48 of the element bump 10.
  • a functional element 9 such as a semiconductor chip or an LSI chip is mounted above the other surface 2b of the high-frequency circuit unit 2.
  • the functional element 9 is electrically connected to a base section 48 formed on the other surface 2 b of the high-frequency circuit section 2 via a device bump section 10 by a flip chip bonding method.
  • the method of mounting the functional element 9 is not limited to the use of the flip-chip bonding method.
  • a face-down mounting method such as a TAB (Tape Automated Bonding) method or a lead beam bonding method may be used. good.
  • the resin layer 11 is formed so as to cover the mounted functional element 9.
  • the resin layer 11 is formed on the other surface 2 b of the high-frequency circuit portion 2 so that the resin is filled between the functional element 9 and the first unit wiring layer 5 by, for example, transfer molding or printing. It is formed over.
  • a resin having a small shrinkage rate due to thermosetting such as an epoxy resin, is used.
  • the functional element 9 and the resin layer 11 are polished as shown in FIG.
  • This polishing treatment is performed by, for example, a mechanical polishing method using a grinder, a chemical polishing method by wet etching, or a CMP method using these polishing methods in combination. Polish the functional element 9 to the thickness.
  • the base substrate 3 is used as a support substrate for the functional element 9 and the resin layer 11, and the resin layer 11 is embedded around the functional element 9 in the polished surface direction so that the functional element 9 and the resin layer 11 are embedded. Since the polishing is performed so that no step is formed between the functional element 9 and 11, it is possible to prevent edge chipping of the functional element 9. That's all Thus, the functional element 9 is mounted on the high-frequency module device 1.
  • the functional element 9 is mounted on the other surface 2b of the high-frequency circuit section 2, the functional element 9 and the resin layer 11 are polished to form Can be made thinner.
  • the high-frequency module device 1 covers the high-frequency circuit portion 2 and the semiconductor chip 44 mounted on the mounting surface 3 a of the base substrate 3 via the bump portion 4, as shown in FIG. It has a structure with a shield cover 49 to eliminate the effects of electromagnetic noise.
  • the high-frequency circuit portion 2 and the semiconductor chip 44 are covered by the shield cover 49, the high-frequency circuit portion 2 on the mounting surface 3a of the base substrate 3 is Heat generated from the functional element 9 and the semiconductor chip 44 may be trapped in the shield cover 49 and adversely affect high-frequency characteristics. Therefore, it is preferable to provide the high-frequency module device 1 with an appropriate heat dissipation structure.
  • the high-frequency module device 1 is configured such that a heat conductive resin material 50 is filled between the high-frequency circuit section 2 and the shield cover 49 to form a heat dissipation structure.
  • heat generated from the functional element 9 mounted on the high-frequency circuit unit 2 is transmitted to the shield cover 49 via the heat conductive resin material 50, and the shield cover 49 dissipates heat.
  • heat is prevented from being trapped inside the shield cover 49 and adversely affecting high-frequency characteristics.
  • mechanical mounting rigidity can be improved.
  • the high-frequency module device 60 shown in FIG. 27 is configured to more efficiently radiate heat generated from the high-frequency circuit unit 2 and the semiconductor chip 44, and the heat conductive resin material 50 described above is used.
  • a large number of cooling vias 61 communicating with the inside of the base substrate 3 are formed corresponding to the mounting area of the high-frequency circuit section 2. These cooling vias 61 are formed by the same process as that for forming the via hole 17 of the mother substrate portion 3.
  • the functional element 9 of the high-frequency circuit unit 2 The generated heat is radiated from the shield cover 49 via the heat conductive resin material 50 as described above, and is transmitted to the bottom surface of the base substrate 3 via the cooling via 61 to be externally Is dissipated.
  • heat is efficiently radiated by radiating heat from both the high-frequency circuit unit 2 and the base substrate 3.
  • a heat dissipation structure may be configured only by the cooling via 61.
  • the high-frequency module device 60 uses, for example, a wiring layer 15 formed on the base substrate 3 with a thickness of, for example, about 50 nm thick.
  • the cooling vias 61 may be connected to each other to release heat from the wiring layer 15.
  • the high-frequency module device 70 shown in FIG. 28 has a configuration in which a metal core 71 having good conductivity such as copper or alloy is provided inside the base substrate 3.
  • the high-frequency module device 70 is configured such that a large number of the cooling vias 61 described above are connected to the metal core 71, respectively.
  • heat is also radiated from the metal core 71 through the cooling via 61, and the heat conductive resin material 50 for heat radiation and the configuration of the cooling via 61 described above depend on the configuration. Further, heat is more efficiently dissipated and reliability is improved.
  • the present invention forms a high-frequency circuit section on a flattened surface of a dummy substrate, thereby enabling a wiring layer having a passive element to be formed with high precision.
  • a high-frequency module device with improved high-frequency characteristics as well as a small area by turning can be manufactured.
  • the present invention forms only a necessary portion of a high-frequency circuit portion having a high-precision wiring layer on one surface of a semiconductor substrate, thereby mounting only a necessary portion of the high-frequency circuit portion on a base substrate.
  • High-frequency module device that has been reduced in size and cost. Equipment can be manufactured.
  • the present invention it is possible to manufacture a high-frequency module device that is excellent in high-frequency characteristics and can be widely used as a high-frequency circuit that is reduced in size, thickness, and cost.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'un module haute fréquence consistant à former, en couches, une première couche (5) de connexion d'unités à une troisième couche (7) de connexion comprenant en partie un condensateur (12) sur une surface planarisée d'un substrat fictif (30) ; à mettre sous boîtier une partie (2) du circuit haute fréquence exposant une troisième connexion à motif à partir du plan de connexion (2a) supérieur sur le plan d'encapsulation (3a) d'un substrat de base (3) exposant une partie de terminal d'entrée/sortie (18) de manière que la troisième connexion à motif soit connectée à la partie de terminal d'entrée/sortie ; puis à retirer le substrat fictif.
PCT/JP2003/011254 2002-09-30 2003-09-03 Procede de fabrication d'un module haute frequence Ceased WO2004032229A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/496,878 US7183135B2 (en) 2002-09-30 2003-09-03 Method for manufacturing high-frequency module device
US11/710,785 US7741162B2 (en) 2002-09-30 2007-02-26 Method for manufacturing high-frequency module device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002-286837 2002-09-30
JP2002286837A JP3925378B2 (ja) 2002-09-30 2002-09-30 高周波モジュール装置の製造方法。

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US10496878 A-371-Of-International 2003-09-03
US11/710,785 Continuation US7741162B2 (en) 2002-09-30 2007-02-26 Method for manufacturing high-frequency module device

Publications (1)

Publication Number Publication Date
WO2004032229A1 true WO2004032229A1 (fr) 2004-04-15

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PCT/JP2003/011254 Ceased WO2004032229A1 (fr) 2002-09-30 2003-09-03 Procede de fabrication d'un module haute frequence

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US (2) US7183135B2 (fr)
JP (1) JP3925378B2 (fr)
KR (1) KR101010126B1 (fr)
TW (1) TWI227608B (fr)
WO (1) WO2004032229A1 (fr)

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KR102003840B1 (ko) 2018-03-12 2019-07-25 삼성전자주식회사 안테나 모듈
JP2020161645A (ja) * 2019-03-26 2020-10-01 国立大学法人信州大学 電子部品
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Also Published As

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KR101010126B1 (ko) 2011-01-24
US20050037535A1 (en) 2005-02-17
US7741162B2 (en) 2010-06-22
JP3925378B2 (ja) 2007-06-06
US20070155060A1 (en) 2007-07-05
JP2004128029A (ja) 2004-04-22
US7183135B2 (en) 2007-02-27
TWI227608B (en) 2005-02-01
KR20050074895A (ko) 2005-07-19
TW200415865A (en) 2004-08-16

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