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WO2004070826A1 - Procede permettant de former une structure de connexion d'electrodes et ladite structure de connexion d'electrodes - Google Patents

Procede permettant de former une structure de connexion d'electrodes et ladite structure de connexion d'electrodes Download PDF

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Publication number
WO2004070826A1
WO2004070826A1 PCT/JP2003/001275 JP0301275W WO2004070826A1 WO 2004070826 A1 WO2004070826 A1 WO 2004070826A1 JP 0301275 W JP0301275 W JP 0301275W WO 2004070826 A1 WO2004070826 A1 WO 2004070826A1
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WO
WIPO (PCT)
Prior art keywords
electrode
adhesive layer
connection structure
forming
electrode portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/001275
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English (en)
Japanese (ja)
Inventor
Seiki Sakuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2004567882A priority Critical patent/JPWO2004070826A1/ja
Priority to PCT/JP2003/001275 priority patent/WO2004070826A1/fr
Priority to TW092102681A priority patent/TW200415749A/zh
Publication of WO2004070826A1 publication Critical patent/WO2004070826A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive

Definitions

  • the present invention relates to a method for forming an inter-electrode connection structure. More specifically, the inter-electrode connection structure, which can be used for joining semiconductor chips with electrical connection, mounting semiconductor chips on a wiring board, and joining a wiring board to a wiring board, etc. It relates to a forming method. Background art
  • a bare chip mounting method has attracted attention as a method that satisfies such requirements.
  • solder bumps and gold bumps are interposed between the semiconductor chip and the land electrodes of the wiring board instead of the conventional face-up mounting that achieves electrical connection between the semiconductor chip and the board wiring by wire bonding.
  • face-down mounting that is, flip-chip bonding
  • a mounting technique using flip chip bonding is disclosed, for example, in Japanese Patent Application Laid-Open No. H10-229265. 5a to 5e show an example of a conventional method for achieving flip chip bonding.
  • a semiconductor chip 5200 obtained by forming an insulating layer 5200b and an electrode 521 on the surface of a substrate 5200a is formed.
  • a bump 540 is formed on the electrode 521.
  • blacks 5600 is applied on the surface of the wiring board 510 provided with the electrodes 511 and the wiring 512 on the surface.
  • the role of the flux 560 is to remove the oxide film on the surface of the bump 540, prevent re-oxidation of the bump 540 by shutting off the air during solder reflow, and form the semiconductor chip 520 against the wiring board 510. Such as temporary bonding.
  • the semiconductor chip 520 is placed on the wiring board 510 while performing positioning so that the electrode 511 of the wiring board 510 and the bump 540 face each other. Place.
  • the electrode 511 and the electrode 521 are connected via the bump 540 through a heat treatment for reflowing the bump 540.
  • the flux 560 is removed by washing. In this way, the flip chip bonding of the semiconductor chip 520 to the wiring board 510 is achieved.
  • an adhesive or an underfill agent 530 is filled between the wiring substrate 510 and the semiconductor chip 520.
  • the underfill agent 530 is for protecting the conductor portion or the bump 540 connecting the electrode 511 and the electrode 521 to ensure long-term connection reliability.
  • the volume of the bumps necessary to secure sufficient connection stability is not required.
  • the volume of the bumps 540 is reduced in order to avoid contact between the pumps, the separation distance between the wiring board 510 and the semiconductor chip 520 after connection is reduced, and in particular, the separation distance is reduced.
  • Below 50 ⁇ causes the following problems. First, when cleaning and removing the flux 560 applied on the wiring board 510, it is difficult to remove the flux 560 existing in the minute gap, and the remaining flux 560 is removed. This can lead to problems such as corrosion. Second, after mounting the semiconductor chip 52 ° on the wiring board 510, the adhesive or underfill agent 530 filled between the wiring board 510 and the semiconductor chip 5 It is difficult to fill the gap without voids.
  • an adhesive mainly composed of a thermosetting epoxy resin is applied to necessary portions on the wiring board in advance, and then the electrodes of the wiring board and the electrodes of the semiconductor chip are connected to each other.
  • a technique for connecting the wiring board and the semiconductor chip with an adhesive while connecting the wiring board and the semiconductor chip via an Au pump is disclosed, for example, in Japanese Patent Application Laid-Open No. 2000-286297.
  • the adhesive is interposed between the bump and the electrode, and the resistance of the connection portion increases. There is a risk.
  • inorganic fillers such as S io 2 that is added to the adhesive in order to mitigate the thermal expansion and contraction differential between the semiconductor chip and the wiring board causes a connection failure because thus interposed between the bump and the electrode Probability is high.
  • an underfill resin sheet having a through-hole at a position of a bump formed on a terminal of a semiconductor chip and a pad on a multilayer wiring board is used as a semiconductor chip and a multilayer wiring board.
  • Such a technique is disclosed in, for example, JP-A-2001-24029.
  • an opening is formed in the insulating resin covering the conductor circuit on the printed wiring board, and the conductor circuit is exposed from the opening, and then the bump and the conductor circuit of the semiconductor chip having a bump are connected.
  • a technique for joining a semiconductor chip and a printed wiring board while achieving electrical continuity is disclosed in, for example, JP-A-2001-156203. .
  • an object of the present invention is to provide a method for forming an interelectrode connection structure, which can protect the substrate itself and wiring while simultaneously sealing the substrates when electrically connecting the substrates having the electrode portions. To provide.
  • Another object of the present invention is to provide an inter-electrode connection structure formed by such a forming method.
  • a method for forming an inter-electrode connection structure includes forming an adhesive layer having an opening on the first connection object having a first electrode portion on the surface, exposing the first electrode portion from the opening, Almost Forming a second connection target having a second electrode portion with the first connection target while the first electrode portion and the second electrode portion face each other with respect to the first connection target. Arranging the attachment layer so as to be in contact with the second connection target; and electrically connecting the first electrode portion and the second electrode portion via a conductor portion and curing the adhesive layer. And a connecting step of performing a heat treatment to perform the heat treatment.
  • the method for curing the first connection object and the second connection object by curing an adhesive layer covering almost the entire surface of the first connection object In addition to sealing the first connection object, the wiring outside the mounting area of the second connection object and the first connection object itself can be protected. Therefore, there is no need to separately form a protective layer for protecting the wiring and the first connection object itself, so that the working efficiency is improved.
  • the first and second electrode portions are pressed against each other due to shrinkage generated during curing. Therefore, the electrical connection between the first and second electrode portions is further improved, and the connection reliability between the first connection object and the second connection object is further improved.
  • the adhesive layer is formed using a photosensitive material.
  • photolithography for forming the opening.
  • the adhesive layer contains an inorganic filler.
  • an inorganic filler By including an inorganic filler, the coefficient of thermal expansion of the adhesive layer can be appropriately reduced.
  • the conductor portion is a metal bump formed in advance on one of the first electrode portion and the second electrode portion, and an electrical connection between the first electrode portion and the second electrode portion is This is performed via the bump. Thereby, the first electrode portion and the second electrode portion are properly conducted.
  • the pump is preferably a metal or an alloy having a melting point of 80 to 400 ° C.
  • the bump is preferably made of a material selected from the group consisting of Sn, Pb, Ag, Cu, In, A1, Au, Bi, Zn, and Sb. New
  • the method further includes a filling step of filling the opening with a metal paste containing a metal, and the conductor portion is formed by solidifying the metal paste.
  • the first electrode part and the second electrode part are also formed by the conductor part thus formed. Are properly conducted.
  • the metal paste contains a resin component, and in the connecting step, the resin component is cured.
  • a mask that opens corresponding to the opening may be provided on the adhesive layer, and in the filling step, the opening of the adhesive layer may be filled with the metal paste via the mask.
  • the conductor is formed by electroplating and Z or electroless brazing. Thereby, the first electrode portion and the second electrode portion are properly conducted.
  • the conductor portion has a laminated structure including a plurality of layers, and each layer may have a metal composition different from that of an adjacent layer.
  • an object for connection between electrodes includes a first connection object having a first electrode portion on a surface, a second connection object provided with a second electrode portion facing the first electrode portion, and the first connection object.
  • the inter-electrode connection structure having such a structure can be formed by the method according to the first aspect of the present invention. Therefore, in the forming process, the same effects as described above with respect to the first aspect are exerted.
  • FIG. 1a to 1f are schematic cross-sectional views showing a series of steps of flip chip bonding using the method for forming an interelectrode connection structure according to the first embodiment of the present invention.
  • FIGS. 2a to 2f are schematic cross-sectional views showing a series of steps of flip chip bonding using the method for forming an interelectrode connection structure according to the second embodiment of the present invention.
  • 3a to 3f are schematic cross-sectional views showing a series of steps of flip chip bonding using the method for forming an interelectrode connection structure according to the third embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of an inter-electrode connection structure obtained by connecting semiconductor chips.
  • 5a to 5e are schematic cross-sectional views showing a series of steps of flip chip bonding using a conventional method for forming an interelectrode connection structure.
  • FIG. 1a cover the electrodes 1 1 1 and the wirings 1 1 2 on the wiring board 1 1 0 on which the electrodes 1 1 1 and the wirings 1 1 2 are provided on the surface 1 1 0 a
  • the bonding layer 130 is formed by lamination as described above.
  • the film-shaped resin composition was placed so as to cover almost the entire surface 110a of the wiring board 110, and then the temperature was lowered to 50 to 140 ° C. Crimping while heating.
  • the liquid resin composition may be applied by spin coating or the like so as to cover almost the entire surface 110a of the wiring substrate 110, and then dried.
  • the resin composition for forming the adhesive layer 130 is obtained by appropriately adding a curing agent, an inorganic filler, and the like to a thermosetting resin as a main agent.
  • the resin composition may be formed into a film in advance, or may be applied in a liquid state on the wiring substrate 110 in a thin film form.
  • the thickness of the adhesive layer 130 is determined based on the electrode pitch, the electrode size of the semiconductor chip 110, the bonding reliability, and the like.
  • Epoxy resin is preferred as the main agent that is a thermosetting resin.
  • Epoxy resins such as bisphenol A epoxy, bisphenol F epoxy, naphthalene epoxy, brominated epoxy, phenol novolak epoxy, cresol novolac epoxy, and biphenyl epoxy of solid or liquid type Can be used.
  • an imidazole-based curing agent an acid anhydride-based curing agent, an amine-based curing agent, a phenol-based curing agent, and the like can be used.
  • the imidazole-based curing agent include 2-phenyl 4-methinoreimidazole, 2-pandecylimidazole, 2,4-diaminol 6- [2-methylimidazole- (1)]-ethyl-S-triazine, and 1-sia Noethinole 2 2-ethynole 4 1-methylimidazonole, 1-cyanoethinole 2 1-decylimidazole, 2-phenyl-2-methyl 5-hydroxy-5-imidazole, 2-phenylimidazole 4, 5-dihihi For ⁇ such as droxymethylimidazole Can be.
  • Acid anhydride curing agents include phthalic anhydride, maleic anhydride, tetrahydrophthalic anhydride, hexahydrophthalic anhydride, methyltetrahydroanhydride phthalic acid, methylhexahydrophthalic anhydride, hymic anhydride, tetrabromophthalic anhydride Acids, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic anhydride, and the like can be used.
  • diethylenetriamine triethylenetetramine, mensendiamine, isophoronediamine, metaxylenediamine, diaminodiphenylmethane, metaphenylenediamine, diaminodiphenylsulfone and the like can be used.
  • Silica powder or alumina powder can be used as the inorganic filler.
  • the content of the inorganic filler is preferably 30 to 70 wt%.
  • an acrylic monomer and a photopolymerization initiator are added to the resin composition for forming the adhesive layer 130.
  • the attaryl monomer isobutyl acrylate, t-butyl acrylate, 1,6-hexanediole acrylate, lauryl acrylate, alkynole acrylate, cetino acrylate, stearyl acrylate, cyclohexino acrylate Relate, Isopornyl acrylate, Benzyl acrylate, 2-Methoxyxetyl acrylate, 3-Methoxybutyl acrylate, Etethyl carbitol acrylate, Phenoxechyl acrylate, Tetrahydrofur Furyl acrylate, phenoxy polyethylene acrylate, methoxytripropylene glycol acrylate, 2-hydroxyethyl acrylate, 2-hydroxypropyl acrylate, 2-hydroxyacrylate inoleoxy eth
  • the content of the acrylyl monomer is preferably 1 to 3 O wt%.
  • photopolymerization initiator examples include 2,2-dimethoxy-1,2-diphenyl-1-one, 1-hydroxyhexylhexyl / lephenizole ketone, and 2-methyl-1- [4- (methylthio) phenyl.
  • the content of the photopolymerization initiator Is preferably 0.1 to 15 wt%.
  • the resin composition for forming the adhesive layer 130 may further include a thermoplastic resin such as a polyester resin and a acrylic resin.
  • an opening 130a is formed in the adhesive layer 130 at a position corresponding to each electrode 111 as shown in FIG. 1b.
  • the opening 130a can be formed by using a UV-YAG laser, a carbon dioxide gas laser, an excimer laser, or the like.
  • photolithography can be employed to form the opening 130a. From the viewpoint of suppressing damage to the electrodes, it is preferable to employ photolithography.
  • photolithography a predetermined photomask (see (Not shown) through exposure processing and subsequent development processing, each electrode
  • An opening 130a is formed so that 111 is exposed.
  • an opening 130a is formed in a predetermined position in advance before the adhesive layer 130 is placed on the surface 110a of the wiring board 110. You may have.
  • the metal bump 140 is formed on the electrode 121.
  • the semiconductor chip 120 is obtained by forming an insulating layer 12 Ob and an electrode 121 on the surface of a substrate 120 a.
  • the metal bump 140 is formed by using a known method such as a vapor deposition method, a plating method, a paste printing method, and a ball mounting method.
  • the composition of the metal bump 140 may be a single metal selected from Sn, Pb, Ag, Cu, In, A1, Au, Bi, Zn, Sb, or a plurality of metals selected from these.
  • An alloy made of a single metal is used.
  • a metal having a melting point of 80 to 400 ° C such as a Sn—Ag alloy, a 311- ⁇ - ⁇ 11 alloy, or a Sn— Pb alloy, Sn—Zn alloy, Sn—Bi alloy, and the like.
  • the temperature for curing the adhesive layer 130 can be set to a relatively low temperature in a step described later.
  • the metal bumps 140 may be formed on the electrode 111 side, or may be formed on both sides of the electrode 111 and the electrode 121.
  • the metal pump 140 and the electrode 111 of the wiring board 110 are positioned so as to face each other in the opening 130a of the adhesive layer 130, and then the wiring is performed.
  • the semiconductor chip 120 is mounted on the substrate 110.
  • the wiring board 110 and the semiconductor chip 120 are heated instantaneously at a temperature higher than the melting point of the metal bump 140 (for example, 250 ° C.) while applying a load f. And join.
  • “instantaneous” means that heating is performed in a short time to reduce the thermal load on the semiconductor chip 120. In this case, it means about 1 to 30 seconds.
  • the metal bump 140 melts, and the electrode 111 and the electrode 121 are electrically connected.
  • the bonding layer 130 is softened and the metal bumps 140 are melted during the heating process, so that the voids in the openings 130 a are formed by the resin of the bonding layer 130. Filled with Z or molten metal.
  • the heating temperature in this step is, for example, 5 to 5 times higher than the melting point of the metal bump 140. C Increase the temperature.
  • the adhesive layer 130 is heated and cured by performing a heat treatment.
  • the adhesive layer 130 softens once until it reaches the curing start temperature (for example, 170 ° C), so the voids in the opening 130 a are bonded.
  • Layer 130 is filled with resin.
  • the curing reaction proceeds in the adhesive layer 130.
  • the wiring board 110 and the semiconductor chip 120 are cured by curing the adhesive layer 130 covering almost the entire surface 110 a of the wiring board 110. And the wiring 112a located outside the mounting area A of the semiconductor chip 120 (see FIG. 1f) and the wiring board 110 itself can be protected. This eliminates the need to separately form a protective layer for protecting the wirings 112 and the wiring board 110 itself, thereby improving work efficiency.
  • the shrinkage that occurs during curing causes the electrodes 111 and 110 to be fixed. 2 Press 1 against each other. As a result, the electrical connection between the electrode 111 and the electrode 121 via the metal bump 140 becomes better, and the connection reliability between the wiring board 110 and the semiconductor chip 120 is improved.
  • an opening 130a is provided in the adhesive layer 130 to prevent a part of the adhesive layer 130 from intervening between the electrode 111 and the electrode 121, thereby increasing the conduction resistance. Is also suppressed.
  • FIG. 2a cover the electrode 2 11 and the wiring 2 1 2 on the wiring board 2 10 on which the electrode 2 1 1 and the wiring 2 1 2 are provided on the surface 2 10 a
  • the bonding layer 230 is laminated as described above.
  • the method for forming the adhesive layer 230 is the same as that described above with respect to the first embodiment.
  • an opening 230a is formed at a position corresponding to each electrode 211 with respect to the adhesive layer 230.
  • the method of forming the opening 230a is the same as that described above with respect to the first embodiment.
  • the adhesive layer 230 is formed using a resin film that has been formed in advance, as described above with reference to the first embodiment, the adhesive layer 230 is formed on the surface of the wiring board 210.
  • the opening 230a may be formed at a predetermined position before placing on the 210a.
  • the opening 230a is filled with a metal paste 240.
  • the metal paste 240 is filled by a known squeezing method or a printing method after a mask (not shown) having an opening corresponding to the opening 230 a is provided on the adhesive layer 230. It is performed by such as. Note that the filling of the opening 230 with the metal paste 240 is not limited to the above-described method.
  • the metal paste 240 includes a metal powder and a luster to paste the metal powder.
  • the metal powder is a single metal selected from Sn, Pb, Ag, Cu, In, A1, Au, Bi, Zn, Sb, or the like, or It is a powder of an alloy consisting of a plurality of selected single metals.
  • the content ratio of the metal powder in the metal paste 240 is set to 20 to 95 wt%. If it is less than 20 wt%, it tends to be difficult to connect electrodes properly. If the content is more than 95 wt%, the viscosity of the metal paste 240 becomes excessively high, and it becomes difficult to fill the opening 230 a.
  • the composition of the resin component is controlled so that the metal powder is melted and then integrated with the adhesive layer 230 in the subsequent heating step.
  • the main agent and curing agent listed for the adhesive layer 230 may be used.
  • rosin may be added to the metal paste 240 in order to improve the wettability to the electrodes 211 and 221.
  • rosin for example, rosin acid, rosin acid ester, rosin anhydride, fatty acid, abietic acid, isopimaric acid, neoabietic acid, pimaric acid, dihydroabietic acid, dehydroabietic acid and the like can be used.
  • metal paste 240 is used to activate the metal surface.
  • an organic carboxylic acid diamine may be added separately from the curing agent, and a higher alcohol such as gellencricol-tetraethylene glycol may be added for viscosity adjustment.
  • the semiconductor chip 2 After filling with the metal paste 240, as shown in FIG. 2d, the semiconductor chip 2 having a mounting area smaller than the area of the surface 210a of the wiring board 210 with respect to the wiring board 210 is formed. It carries 20.
  • the semiconductor chip 220 has a structure in which an insulating layer 220 b and an electrode 222 are formed on the surface of the substrate 220 a, and the opening 2 of the adhesive layer 230 is formed.
  • the metal paste 240 and the electrode 222 are positioned so as to face each other. It should be noted that the metal bumps formed on the electrodes 22 of the semiconductor chip 220 as described in the first embodiment may be mounted on the wiring board 210.
  • the wiring board 210 and the semiconductor chip are heated by applying a load f and heating to a temperature equal to or higher than the melting point of the metal powder contained in the metal paste 240.
  • the metal powder contained in the metal paste 240 is melted and integrated, and the electrode 211 and the electrode 221 are electrically connected.
  • solder powder is used as the metal powder contained in the metal paste 240, and the heating temperature at the time of joining is set to a temperature higher by 5 to 50 ° C. than the melting point of the solder.
  • the resin component contained in the metal paste 240 is separated from the metal powder.
  • the adhesive layer 230 is heated and cured by heat treatment. At this time, the separated resin component of the metal paste 240 is bonded to the adhesive layer 2
  • 3a to 3f show a series of steps of a method for forming an interelectrode connection structure according to a third embodiment of the present invention.
  • the present embodiment will also be described using flip chip bonding as an example.
  • FIG. 3a cover the electrode 311 and the wiring 312 with respect to the wiring board 310 on which the electrode 311 and the wiring 312 are provided on the surface 310a.
  • the bonding layer 330 is formed in a laminated manner as described above.
  • the method for forming the adhesive layer 330 is the same as that described above with respect to the first embodiment.
  • FIG. 3B an opening 330a is formed in the adhesive layer 330 at a position corresponding to each electrode 311.
  • the method of forming the opening 330a is the same as that described above with respect to the first embodiment.
  • the adhesive layer 330 when the adhesive layer 330 is formed using a resin film formed in advance, the adhesive layer 330 is formed on the surface 310a of the wiring board 310.
  • the opening 330a may be formed at a predetermined position before mounting.
  • a conductor 313 is formed on the electrode 311 in the opening 330a.
  • the conductor portion 3 13 can be formed by an electric plating method or an electroless plating method.
  • Examples of a material for forming the conductor portion 313 include simple metals such as A 1, Au, In, Sn, Cu, Ag, and Pd, and Sn, Pb, Ag, Cu, In, An alloy consisting of a plurality of single metals selected from Bi, Zn, Sb, Al, Au and the like can be used. Among them, it is preferable to use a metal having a melting point of 80 to 400 ° C. in order to reduce the conduction resistance between the electrodes, and the metal includes In Sn—B i, Sn—Pb alloy, Sn—Zn alloy, S n_Ag—Cu alloy and the like. Note that the conductor portion 313 may be formed by sequentially laminating metals having different compositions.
  • the semiconductor chip 320 After forming the conductor portion 313, as shown in FIG. 3D, the semiconductor chip 320 having a mounting area smaller than the area of the surface 310 a of the wiring board 310 is mounted on the wiring board 310.
  • the semiconductor chip 320 has an insulating layer 320 b and an electrode 321 formed on the surface of a substrate 320 a, and the conductor 313 faces the electrode 321 at the opening 330 a of the adhesive layer 330. So that they are aligned.
  • the metal bumps formed on the electrodes 321 of the semiconductor chip 320 as described in the first embodiment may be mounted on the wiring board 310.
  • the wiring substrate 310 and the semiconductor chip 320 are joined by heating while applying a load f.
  • the conductor portion 313 is fused to the electrode 311 and the electrode 321 to electrically connect the electrode 311 and the electrode 321.
  • heat treatment is performed to heat and cure the adhesive layer 330.
  • the wiring board 310 and the semiconductor chip 32 0 is joined.
  • the connection between the semiconductor chip and the wiring board has been described as an example, but the joining object is not limited to this.
  • the semiconductor chip with the semiconductor chip 420 obtained by forming the insulating layer 420b and the electrode 421 on the surface of the mounting area smaller than the area of the mounting area may be used, or one mounting area may be the other surface. May be smaller than each other.
  • the liquid resin composition described above was applied to a PET film (thickness: 20 ⁇ ) to a thickness of 70 m, and then dried at 90 ° C for 3 minutes to remove the solvent, thereby removing the film thickness.
  • a resin film of 0 urn was produced.
  • the resin film prepared as described above was placed at 80 ° using a roll mounter (manufactured by EM “C” K) so as to cover the entire surface of the wiring board (electrode diameter: 90 ⁇ m). C To form an adhesive layer. Next, the adhesive layer was exposed and developed to form an opening having a diameter of 100 ⁇ such that the electrode was exposed. Development was carried out using 2.38% tetramethylammonium hydroxide.
  • This wiring board was mounted on a semiconductor chip with electrodes formed with Sn-3.5% Ag bumps (height 35 ⁇ ). At this time, the positioning was performed so that the Sn-3.5% Ag bump and the electrode of the wiring board faced each other in the opening.
  • Example 2 Instead of the S ⁇ —3.5% Ag bump (height 35 Mm) formed on the electrode of the semiconductor chip in Example 1, a Sn—37% Pb bump (height 35 ⁇ ) was applied to the electrode. Flip chip bonding was performed in the same manner as in Example 1 except that the electrodes were formed and the heating temperature at the time of bonding was 220 ° C., to obtain an interelectrode connection structure of the present example.
  • the opening was directly filled with a solder paste containing epoxy resin (trade name: Underfill Paste # 2000, manufactured by Senju Metal Industry Co., Ltd.) and formed on the electrodes of the semiconductor chip.
  • Flip chip bonding was performed in the same manner as in Example 1 except that the height of the obtained Sn-3.5% Ag bump was set to 15 ⁇ to obtain a connection structure between electrodes of this example.
  • a metal mask (opening diameter: 80 ⁇ , thickness: 30 ⁇ ) that opens corresponding to the opening formed in the adhesive layer was provided on the adhesive layer, and the opening was filled with solder paste. Flip-chip bonding was performed in the same manner as in Example 3 except that the height of the S ⁇ -3.5% Ag bump formed on the electrode of Example 3 was changed to 10 ⁇ m. Obtained.
  • Example 2 Instead of the Sn—3.5% Ag bump (height 35 ⁇ m) formed on the electrode of the semiconductor chip in Example 1, an Au stud bump (height 30 ⁇ ) was formed on the electrode. Flip chip bonding was performed in the same manner as in Example 1 except that the opening formed in the adhesive layer had a diameter of 50 im, to obtain an interelectrode connection structure of the present example.
  • Example 5 except that after the opening was formed, the opening was directly filled with a solder paste containing epoxy resin (trade name: Underfill Paste # 200, manufactured by Senju Metal Industry Co., Ltd.). Flip chip bonding was performed in the same manner as described above to obtain an inter-electrode connection structure of this example.
  • a solder paste containing epoxy resin trade name: Underfill Paste # 200, manufactured by Senju Metal Industry Co., Ltd.
  • a metal mask (opening diameter 30 ⁇ m, thickness 20 m) that opens corresponding to the opening formed in the adhesive layer is provided on the adhesive layer, and then the solder paste is filled in the opening.
  • flip chip bonding was performed to obtain an interelectrode connection structure of the present example.
  • the opening was formed in the same manner as in Example 1 except that the opening was formed by exposing and developing the PET film on the PET film before attaching the resin film to the surface of the wiring board. Then, an inter-electrode connection structure of the present example was obtained.
  • Example 8 Au stud bumps (height 30 ⁇ ) were replaced with Sn-3.5% Ag bumps (height 35 Mm) formed on the electrodes of the semiconductor chip. Flip chip bonding was performed in the same manner as in Example 8, except that the electrode was formed and the diameter of the opening was set to 50, to obtain an inter-electrode connection structure of this example.
  • connection reliability of each of the inter-electrode connection structures of Examples 1 to 9 was examined by a temperature cycle test. Specifically, first, the initial conduction resistance of each inter-electrode connection part in the inter-electrode connection structure was measured. Next, after conducting a temperature cycle test in the range of 150 ° C to 125 ° C, the conduction resistance of the connection portion was measured. The temperature cycle test consists of cooling at -55 ° C for 15 minutes, leaving it at room temperature for 10 minutes, and heating at 125 ° C for 15 minutes. I turned around again. As a result, for all the inter-electrode connection structures of Examples 1 to 9, the resistance rise at each connection was 1%. 0% or less, and it was confirmed that a good connection portion was formed.
  • connection reliability was examined by a moisture resistance test. Specifically, first, the conduction resistance of each inter-electrode connection part in the inter-electrode connection structure was measured at 25 ° C. and 60% humidity. Next, each electrode connection structure was left in an environment of 121 ° C. and a humidity of 85%, and the conduction resistance of each connection portion was measured after 1000 hours. As a result, with respect to all of the inter-electrode connection structures of Examples 1 to 9, the resistance increase in each connection portion was 10% or less, and it was confirmed that a good connection portion was formed.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé permettant de former une structure de connexion d'électrodes qui consiste : à former une couche d'adhérence (130) pourvue de parties d'ouverture (130a) sur une première partie connectée (110) qui comprend des premières parties d'électrode (111) sur sa surface (110a) de façon que les premières parties d'électrode (111) puissent être exposées aux parties d'ouverture (130a) et qu'au moins une partie de la surface (110a) puisse être recouverte par la couche d'adhérence (130) ; à disposer une seconde partie connectée (120) qui comprend des secondes parties d'électrode (121) sur sa surface de façon que la couche d'adhérence (130) vienne en contact avec la seconde partie connectée (120) tandis que les premières parties d'électrode (111) et les secondes parties d'électrode (121) sont situées en face les unes aux autres ; enfin, à connecter électriquement les premières parties d'électrode (111) aux secondes parties d'électrode (121) au moyen de parties conductrices (140) et à procéder à un traitement thermique de façon que la couche d'adhérence (130) puisse être durcie.
PCT/JP2003/001275 2003-02-06 2003-02-06 Procede permettant de former une structure de connexion d'electrodes et ladite structure de connexion d'electrodes Ceased WO2004070826A1 (fr)

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JP2004567882A JPWO2004070826A1 (ja) 2003-02-06 2003-02-06 電極間接続構造体の形成方法および電極間接続構造体
PCT/JP2003/001275 WO2004070826A1 (fr) 2003-02-06 2003-02-06 Procede permettant de former une structure de connexion d'electrodes et ladite structure de connexion d'electrodes
TW092102681A TW200415749A (en) 2003-02-06 2003-02-10 Method of forming electrode-to-electrode connection structure and electrode-to-electrode connection structure formed thereby

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PCT/JP2003/001275 WO2004070826A1 (fr) 2003-02-06 2003-02-06 Procede permettant de former une structure de connexion d'electrodes et ladite structure de connexion d'electrodes

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JP2008153296A (ja) * 2006-12-14 2008-07-03 Fujitsu Ltd 接続構造体とその製造方法および半導体装置とその製造方法
WO2009072493A1 (fr) * 2007-12-04 2009-06-11 Hitachi Chemical Company, Ltd. Adhésif photosensible, dispositif semi-conducteur et procédé de fabrication de dispositif semi-conducteur
JP2010062514A (ja) * 2008-09-03 2010-03-18 Ultratera Corp 粘着性保護層を有する半導体ウェハ
JP2010153521A (ja) * 2008-12-25 2010-07-08 Shinko Electric Ind Co Ltd 半導体素子の樹脂封止方法
JP2011054926A (ja) * 2009-09-01 2011-03-17 Samsung Electro-Mechanics Co Ltd 回路基板、半導体パッケージ及び回路基板の製造方法
US8258017B2 (en) 2007-12-04 2012-09-04 Hitachi Chemical Company, Ltd. Photosensitive adhesive
JP5684958B1 (ja) * 2014-01-14 2015-03-18 株式会社メイコー プリント配線基板

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Cited By (19)

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JP2007128982A (ja) * 2005-11-01 2007-05-24 Nec Corp 半導体バンプ接続構造体及びその製造方法
JP2008153296A (ja) * 2006-12-14 2008-07-03 Fujitsu Ltd 接続構造体とその製造方法および半導体装置とその製造方法
US8507323B2 (en) 2007-12-04 2013-08-13 Hitachi Chemical Company, Ltd. Method of producing semiconductor device with patterned photosensitive adhesive
WO2009072493A1 (fr) * 2007-12-04 2009-06-11 Hitachi Chemical Company, Ltd. Adhésif photosensible, dispositif semi-conducteur et procédé de fabrication de dispositif semi-conducteur
JP5526783B2 (ja) * 2007-12-04 2014-06-18 日立化成株式会社 半導体装置及び半導体装置の製造方法
KR101138742B1 (ko) 2007-12-04 2012-04-24 히다치 가세고교 가부시끼가이샤 감광성 접착제, 반도체 장치 및 반도체 장치의 제조 방법
US8258017B2 (en) 2007-12-04 2012-09-04 Hitachi Chemical Company, Ltd. Photosensitive adhesive
US8349700B2 (en) 2007-12-04 2013-01-08 Hitachi Chemical Company, Ltd. Photosensitive adhesive, semiconductor device and method for manufacturing semiconductor device
CN103021881A (zh) * 2007-12-04 2013-04-03 日立化成工业株式会社 感光性胶粘剂、半导体装置及半导体装置的制造方法
JP2010062514A (ja) * 2008-09-03 2010-03-18 Ultratera Corp 粘着性保護層を有する半導体ウェハ
JP2010153521A (ja) * 2008-12-25 2010-07-08 Shinko Electric Ind Co Ltd 半導体素子の樹脂封止方法
JP2011054926A (ja) * 2009-09-01 2011-03-17 Samsung Electro-Mechanics Co Ltd 回路基板、半導体パッケージ及び回路基板の製造方法
JP5684958B1 (ja) * 2014-01-14 2015-03-18 株式会社メイコー プリント配線基板
WO2015079713A1 (fr) * 2014-01-14 2015-06-04 株式会社メイコー Carte de circuits imprimés
CN104919907A (zh) * 2014-01-14 2015-09-16 名幸电子有限公司 印刷布线基板
KR101569156B1 (ko) 2014-01-14 2015-11-13 메이코 일렉트로닉스 컴파니 리미티드 프린트 배선 기판
US9326376B2 (en) 2014-01-14 2016-04-26 Meiko Electronics Co., Ltd. Printed wiring board
CN109890131A (zh) * 2014-01-14 2019-06-14 名幸电子有限公司 印刷布线基板
CN109890131B (zh) * 2014-01-14 2021-09-14 名幸电子有限公司 印刷布线基板

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