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WO2003095712A3 - Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs - Google Patents

Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs Download PDF

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Publication number
WO2003095712A3
WO2003095712A3 PCT/US2003/014664 US0314664W WO03095712A3 WO 2003095712 A3 WO2003095712 A3 WO 2003095712A3 US 0314664 W US0314664 W US 0314664W WO 03095712 A3 WO03095712 A3 WO 03095712A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor based
based circuitry
forming
dimensional structures
structures integral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/014664
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English (en)
Other versions
WO2003095712A2 (fr
Inventor
Adam L Cohen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Southern California USC
Original Assignee
University of Southern California USC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Southern California USC filed Critical University of Southern California USC
Priority to AU2003228977A priority Critical patent/AU2003228977A1/en
Publication of WO2003095712A2 publication Critical patent/WO2003095712A2/fr
Anticipated expiration legal-status Critical
Publication of WO2003095712A3 publication Critical patent/WO2003095712A3/fr
Ceased legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00126—Static structures not provided for in groups B81C1/00031 - B81C1/00119
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/003—3D structures, e.g. superposed patterned layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/05—Temporary protection of devices or parts of the devices during manufacturing
    • B81C2201/053—Depositing a protective layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Electrochemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Cette invention a trait à des procédés améliorés de fabrication par voie électrochimique de structures multicouche tridimensionnelles, utilisant comme substrat des circuits à semi-conducteurs. Certaine régions électriquement fonctionnelles de cette structure sont faites d'un matériau structural (du nickel, par exemple) adhérant aux plots de contact du circuit. Les plots de contact en aluminium et les structures au silicium sont protégés des dégâts causés par une diffusion du cuivre par application de couches barrière appropriées.
PCT/US2003/014664 2002-05-07 2003-05-07 Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs Ceased WO2003095712A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003228977A AU2003228977A1 (en) 2002-05-07 2003-05-07 Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37918302P 2002-05-07 2002-05-07
US60/379,183 2002-05-07

Publications (2)

Publication Number Publication Date
WO2003095712A2 WO2003095712A2 (fr) 2003-11-20
WO2003095712A3 true WO2003095712A3 (fr) 2005-08-18

Family

ID=29420501

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/014664 Ceased WO2003095712A2 (fr) 2002-05-07 2003-05-07 Procede de fabrication de structures tridimensionnelles solidaires de circuits a semi-conducteurs

Country Status (3)

Country Link
US (2) US20040065554A1 (fr)
AU (1) AU2003228977A1 (fr)
WO (1) WO2003095712A2 (fr)

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WO2003095707A2 (fr) * 2002-05-07 2003-11-20 Memgen Corporation Procede et appareil pour former des structures tridimensionnelles integrees dans des circuits a semiconducteurs
EP1711961A4 (fr) * 2003-12-31 2008-10-22 Microfabrica Inc Procede et dispositif pour maintenir le parallelisme de couches et/ou obtenir des epaisseurs voulues de couches pendant la fabrication electrochimique de structures
US20070238265A1 (en) * 2005-04-05 2007-10-11 Keiichi Kurashina Plating apparatus and plating method
KR100870820B1 (ko) 2005-12-29 2008-11-27 매그나칩 반도체 유한회사 이미지 센서 및 그의 제조방법
CH704572B1 (fr) * 2007-12-31 2012-09-14 Nivarox Sa Procédé de fabrication d'une microstructure métallique et microstructure obtenue selon ce procédé.
AU2013208114B2 (en) * 2012-01-10 2014-10-30 Hzo, Inc. Masks for use in applying protective coatings to electronic assemblies, masked electronic assemblies and associated methods
KR20150020574A (ko) 2012-06-18 2015-02-26 에이치제트오 인코포레이티드 완전히 조립된 전자 디바이스의 내부 표면에 보호 코팅을 제공하는 시스템 및 방법
KR102253463B1 (ko) 2013-01-08 2021-05-18 에이치제트오 인코포레이티드 보호 코팅의 적용을 위한 기판 마스킹
US10449568B2 (en) 2013-01-08 2019-10-22 Hzo, Inc. Masking substrates for application of protective coatings
US9894776B2 (en) 2013-01-08 2018-02-13 Hzo, Inc. System for refurbishing or remanufacturing an electronic device

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WO2000042231A2 (fr) * 1999-01-15 2000-07-20 The Regents Of The University Of California Films de polysilicium-germanium permettant de realiser des systemes micro-electromecaniques

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US20070221505A1 (en) 2007-09-27
US20040065554A1 (en) 2004-04-08

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