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WO2004061952A3 - Procede de realisation d'une structure de semi-conducteur multicouche a interface de liaison sans solution de continuite - Google Patents

Procede de realisation d'une structure de semi-conducteur multicouche a interface de liaison sans solution de continuite Download PDF

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Publication number
WO2004061952A3
WO2004061952A3 PCT/US2003/041557 US0341557W WO2004061952A3 WO 2004061952 A3 WO2004061952 A3 WO 2004061952A3 US 0341557 W US0341557 W US 0341557W WO 2004061952 A3 WO2004061952 A3 WO 2004061952A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor structure
forming
layer
layer semiconductor
bonding interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/041557
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English (en)
Other versions
WO2004061952A2 (fr
Inventor
Rafael Reif
Andy Fan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Massachusetts Institute of Technology
Original Assignee
Massachusetts Institute of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massachusetts Institute of Technology filed Critical Massachusetts Institute of Technology
Priority to AU2003300061A priority Critical patent/AU2003300061A1/en
Publication of WO2004061952A2 publication Critical patent/WO2004061952A2/fr
Publication of WO2004061952A3 publication Critical patent/WO2004061952A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un procédé de formation d'une structure de semi-conducteur multicouche, procédé par lequel on prend une première couche d'un film de liaison en cuivre tracé d'une première épaisseur définie, et on l'applique sur une première surface d'un premier semi-conducteur. On prend ensuite une deuxième couche d'un film de liaison en cuivre tracé d'une deuxième épaisseur définie, et on l'applique sur une première surface d'un deuxième semi-conducteur. La première et la deuxième de ces structures de semi-conducteurs peuvent être alignées, de façon que le premier et le deuxième des films de liaison en cuivre tracé soient à proximité l'un de l'autre. Il est ainsi possible de former une liaison virtuellement sans solution de continuité entre le premier et le deuxième des films de liaison en cuivre tracé de sorte que le premier et le deuxième des semi-conducteurs constituent la structure de semi-conducteur multicouche.
PCT/US2003/041557 2002-12-31 2003-12-30 Procede de realisation d'une structure de semi-conducteur multicouche a interface de liaison sans solution de continuite Ceased WO2004061952A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003300061A AU2003300061A1 (en) 2002-12-31 2003-12-30 Method of forming a multi-layer semiconductor structure having a seamless bonding interface

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US43754902P 2002-12-31 2002-12-31
US60/437,549 2002-12-31
US10/655,670 US7064055B2 (en) 2002-12-31 2003-09-05 Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US10/655,670 2003-09-05

Publications (2)

Publication Number Publication Date
WO2004061952A2 WO2004061952A2 (fr) 2004-07-22
WO2004061952A3 true WO2004061952A3 (fr) 2005-05-19

Family

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PCT/US2003/041557 Ceased WO2004061952A2 (fr) 2002-12-31 2003-12-30 Procede de realisation d'une structure de semi-conducteur multicouche a interface de liaison sans solution de continuite

Country Status (3)

Country Link
US (2) US7064055B2 (fr)
AU (1) AU2003300061A1 (fr)
WO (1) WO2004061952A2 (fr)

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WO2004061961A1 (fr) * 2002-12-31 2004-07-22 Massachusetts Institute Of Technology Structure integree multicouche de semi-conducteur avec partie d'ecran electrique
US7064055B2 (en) * 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
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US7948034B2 (en) * 2006-06-22 2011-05-24 Suss Microtec Lithography, Gmbh Apparatus and method for semiconductor bonding
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US8017451B2 (en) * 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
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US8159060B2 (en) * 2009-10-29 2012-04-17 International Business Machines Corporation Hybrid bonding interface for 3-dimensional chip integration
US8603862B2 (en) 2010-05-14 2013-12-10 International Business Machines Corporation Precise-aligned lock-and-key bonding structures
FR3003087B1 (fr) * 2013-03-05 2015-04-10 Commissariat Energie Atomique Procede de realisation d’un collage direct metallique conducteur
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FR3070550B1 (fr) * 2017-08-24 2020-07-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede d'assemblage de connecteurs electriques

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US20040126994A1 (en) 2004-07-01

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