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WO2003081664A3 - Procede de transfert d'elements de substrat a substrat - Google Patents

Procede de transfert d'elements de substrat a substrat Download PDF

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Publication number
WO2003081664A3
WO2003081664A3 PCT/FR2003/000905 FR0300905W WO03081664A3 WO 2003081664 A3 WO2003081664 A3 WO 2003081664A3 FR 0300905 W FR0300905 W FR 0300905W WO 03081664 A3 WO03081664 A3 WO 03081664A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrates
transferring elements
degradation
bonding layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2003/000905
Other languages
English (en)
Other versions
WO2003081664A2 (fr
Inventor
Bernard Aspar
Olivier Rayssac
Franck Fournel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to US10/508,917 priority Critical patent/US20050178495A1/en
Priority to JP2003579275A priority patent/JP2005532674A/ja
Priority to EP03725311A priority patent/EP1493181A2/fr
Publication of WO2003081664A2 publication Critical patent/WO2003081664A2/fr
Publication of WO2003081664A3 publication Critical patent/WO2003081664A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Particle Formation And Scattering Control In Inkjet Printers (AREA)
  • Dicing (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

La présente invention concerne un procédé de transfert d'au moins un élément depuis un substrat donneur vers un substrat cible (40). Conformément à l'invention, on rend un élément à transférer solidaire d'un substrat-poignée (30) par l'intermédiaire d'une couche de colle (32) susceptible d'être dégradée et dans lequel on procède à une dégradation de la couche de colle lors d'une étape de libération de l'élément à transférer. Application au report de composants.
PCT/FR2003/000905 2002-03-25 2003-03-21 Procede de transfert d'elements de substrat a substrat Ceased WO2003081664A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/508,917 US20050178495A1 (en) 2002-03-25 2003-03-21 Method for transferring elements between substrates
JP2003579275A JP2005532674A (ja) 2002-03-25 2003-03-21 エレメントを基板から基板へ移設する方法
EP03725311A EP1493181A2 (fr) 2002-03-25 2003-03-21 Procede de transfert d'elements de substrat a substrat

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR02/03693 2002-03-25
FR0203693A FR2837620B1 (fr) 2002-03-25 2002-03-25 Procede de transfert d'elements de substrat a substrat

Publications (2)

Publication Number Publication Date
WO2003081664A2 WO2003081664A2 (fr) 2003-10-02
WO2003081664A3 true WO2003081664A3 (fr) 2004-04-01

Family

ID=27799237

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2003/000905 Ceased WO2003081664A2 (fr) 2002-03-25 2003-03-21 Procede de transfert d'elements de substrat a substrat

Country Status (5)

Country Link
US (1) US20050178495A1 (fr)
EP (1) EP1493181A2 (fr)
JP (1) JP2005532674A (fr)
FR (1) FR2837620B1 (fr)
WO (1) WO2003081664A2 (fr)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2842647B1 (fr) * 2002-07-17 2004-09-17 Soitec Silicon On Insulator Procede de transfert de couche
FR2850390B1 (fr) 2003-01-24 2006-07-14 Soitec Silicon On Insulator Procede d'elimination d'une zone peripherique de colle lors de la fabrication d'un substrat composite
US7122095B2 (en) 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
JP4610982B2 (ja) * 2003-11-11 2011-01-12 シャープ株式会社 半導体装置の製造方法
FR2866982B1 (fr) * 2004-02-27 2008-05-09 Soitec Silicon On Insulator Procede de fabrication de composants electroniques
FR2866983B1 (fr) * 2004-03-01 2006-05-26 Soitec Silicon On Insulator Realisation d'une entite en materiau semiconducteur sur substrat
EP1571705A3 (fr) 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Réalisation d'une entité en matériau semiconducteur sur substrat
DE102004048202B4 (de) * 2004-09-30 2008-05-21 Infineon Technologies Ag Verfahren zur Vereinzelung von oberflächenmontierbaren Halbleiterbauteilen und zur Bestückung derselben mit Außenkontakten
FR2877142B1 (fr) * 2004-10-21 2007-05-11 Commissariat Energie Atomique Procede de transfert d'au moins un objet de taille micrometrique ou millimetrique au moyen d'une poignee en polymere.
FR2895562B1 (fr) 2005-12-27 2008-03-28 Commissariat Energie Atomique Procede de relaxation d'une couche mince contrainte
JP2007251080A (ja) * 2006-03-20 2007-09-27 Fujifilm Corp プラスチック基板の固定方法、回路基板およびその製造方法
JP4958287B2 (ja) * 2007-05-30 2012-06-20 東京応化工業株式会社 剥がし装置における剥離方法
US7520951B1 (en) 2008-04-17 2009-04-21 International Business Machines (Ibm) Corporation Method of transferring nanoparticles to a surface
FR2935537B1 (fr) * 2008-08-28 2010-10-22 Soitec Silicon On Insulator Procede d'initiation d'adhesion moleculaire
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2943177B1 (fr) * 2009-03-12 2011-05-06 Soitec Silicon On Insulator Procede de fabrication d'une structure multicouche avec report de couche circuit
FR2947380B1 (fr) 2009-06-26 2012-12-14 Soitec Silicon Insulator Technologies Procede de collage par adhesion moleculaire.
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave
JP5590837B2 (ja) 2009-09-15 2014-09-17 キヤノン株式会社 機能性領域の移設方法
EP2339614A1 (fr) * 2009-12-22 2011-06-29 Imec Procédé pour l'empilage de puces semi-conductrices
JP5943544B2 (ja) * 2010-12-20 2016-07-05 株式会社ディスコ 積層デバイスの製造方法及び積層デバイス
WO2014020387A1 (fr) 2012-07-31 2014-02-06 Soitec Procédés de formation de structures semi-conductrices incluant des dispositifs de microsystème électromécanique et des circuits intégrés sur les côtés opposés de substrats, et structures ainsi que dispositifs connexes
DE102014014422A1 (de) * 2014-09-29 2016-03-31 Siltectra Gmbh Kombiniertes Waferherstellungsverfahren mit einer Löcher aufweisenden Aufnahmeschicht
CN114256120B (zh) * 2020-09-21 2025-05-16 重庆康佳光电科技有限公司 暂存装置、暂存装置的制作方法和微元件的转移方法
FR3137491B1 (fr) * 2022-06-30 2024-10-18 Commissariat Energie Atomique Procédé de fabrication d’une structure pavée
FR3140707A1 (fr) * 2022-10-06 2024-04-12 Soitec Procede de fabrication d’une structure composite comprenant des paves
WO2025073392A1 (fr) * 2023-10-06 2025-04-10 Soitec Procede de fabrication d'une structure composite pour la microelectronique, l'optique ou l'optoelectronique

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0703609A1 (fr) * 1994-09-22 1996-03-27 Commissariat A L'energie Atomique Procédé de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
US5618739A (en) * 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
EP0924769A1 (fr) * 1997-07-03 1999-06-23 Seiko Epson Corporation Procede de transfert de dispositifs a couches minces, dispositif a couches minces, dispositif a circuit integre a couches minces, substrat de matrice active, affichage a cristaux liquides et appareil electronique
EP0977252A1 (fr) * 1998-07-30 2000-02-02 Commissariat A L'energie Atomique Transfert sélectif d'éléments d'un support vers un autre support
EP1041624A1 (fr) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Methode de transfert de substrates ultra-minces et mis en oeuvre de sa methode dans la fabrication de dispositifs de type couches minces
FR2796491A1 (fr) * 1999-07-12 2001-01-19 Commissariat Energie Atomique Procede de decollement de deux elements et dispositif pour sa mise en oeuvre
US6232136B1 (en) * 1990-12-31 2001-05-15 Kopin Corporation Method of transferring semiconductors

Family Cites Families (6)

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US5455202A (en) * 1993-01-19 1995-10-03 Hughes Aircraft Company Method of making a microelectric device using an alternate substrate
US5591678A (en) * 1993-01-19 1997-01-07 He Holdings, Inc. Process of manufacturing a microelectric device using a removable support substrate and etch-stop
US6214733B1 (en) * 1999-11-17 2001-04-10 Elo Technologies, Inc. Process for lift off and handling of thin film materials
JP2002075915A (ja) * 2000-08-25 2002-03-15 Canon Inc 試料の分離装置及び分離方法
US6638835B2 (en) * 2001-12-11 2003-10-28 Intel Corporation Method for bonding and debonding films using a high-temperature polymer
FR2842650B1 (fr) * 2002-07-17 2005-09-02 Soitec Silicon On Insulator Procede de fabrication de substrats notamment pour l'optique, l'electronique ou l'opto-electronique

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618739A (en) * 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
US6232136B1 (en) * 1990-12-31 2001-05-15 Kopin Corporation Method of transferring semiconductors
EP0703609A1 (fr) * 1994-09-22 1996-03-27 Commissariat A L'energie Atomique Procédé de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
EP0924769A1 (fr) * 1997-07-03 1999-06-23 Seiko Epson Corporation Procede de transfert de dispositifs a couches minces, dispositif a couches minces, dispositif a circuit integre a couches minces, substrat de matrice active, affichage a cristaux liquides et appareil electronique
EP0977252A1 (fr) * 1998-07-30 2000-02-02 Commissariat A L'energie Atomique Transfert sélectif d'éléments d'un support vers un autre support
EP1041624A1 (fr) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Methode de transfert de substrates ultra-minces et mis en oeuvre de sa methode dans la fabrication de dispositifs de type couches minces
FR2796491A1 (fr) * 1999-07-12 2001-01-19 Commissariat Energie Atomique Procede de decollement de deux elements et dispositif pour sa mise en oeuvre

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HAMAGUCHI T ET AL: "NOVEL LSI/SOI WAFER FABRICATION USING DEVICE LAYER TRANSFER TECHNIQUE", INTERNATIONAL ELECTRON DEVICES MEETING. WASHINGTON, DEC. 1 - 4, 1985, WASHINGTON, IEEE, US, December 1985 (1985-12-01), pages 688 - 691, XP000842673 *

Also Published As

Publication number Publication date
EP1493181A2 (fr) 2005-01-05
WO2003081664A2 (fr) 2003-10-02
FR2837620B1 (fr) 2005-04-29
FR2837620A1 (fr) 2003-09-26
JP2005532674A (ja) 2005-10-27
US20050178495A1 (en) 2005-08-18

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