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WO2003081655A1 - Procédé d'attaque chimique au plasma - Google Patents

Procédé d'attaque chimique au plasma Download PDF

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Publication number
WO2003081655A1
WO2003081655A1 PCT/JP2003/002749 JP0302749W WO03081655A1 WO 2003081655 A1 WO2003081655 A1 WO 2003081655A1 JP 0302749 W JP0302749 W JP 0302749W WO 03081655 A1 WO03081655 A1 WO 03081655A1
Authority
WO
WIPO (PCT)
Prior art keywords
plasma etching
film
etching method
etching
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/002749
Other languages
English (en)
Japanese (ja)
Inventor
Noriyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to US10/508,006 priority Critical patent/US20050161435A1/en
Publication of WO2003081655A1 publication Critical patent/WO2003081655A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the present invention relates to a plasma etching method performed in a semiconductor device manufacturing process. Background technology
  • a gas mainly composed of fluorocarbon has been used as an etching gas when plasma etching a SiO 2 film in a substrate to be processed through an opening pattern of a photo resist.
  • the present invention has been made in view of the above circumstances, and has as its object to suppress the etching stop, and to reduce the plasma generation in the etching hole. It is to provide a method for etching.
  • Plasma etching method for solving the aforementioned problems is a C x F y gas comprising (x ⁇ 2) and CF 4 was introduced into the processing chamber into a plasma, in the processing vessel to be The film in the processing body is plasma-etched through an opening pattern of a mask of a metal compound on the film.
  • the metal compound may be a metal nitride.
  • the metal nitride may be T i N. Further, the metal nitride may be TaN.
  • C x F y gas comprising (x ⁇ 2) and CF 4 may be as further comprising a N 2. Further, the gas may further include Ar.
  • the film in the object to be processed may be a SiO 2 film. Further, the film in the object to be processed may be a SiC film. Further, the film in the object to be processed may be a Si ⁇ C film.
  • SiOC refers to a so-called organic silicon oxide having a main chain of one Si-0- and having an organic functional group such as a methyl group on at least a part of a side chain.
  • the C x F y (x ⁇ 2) of the gas may be C 4 F 6 .
  • the flow ratio of C 4 F 6 to CF 4 of the gas (the flow rate of C 4 F 6 / the flow rate of CF 4 ) is 0.12 to 0.20. If it exceeds 0.20, it will cause an etching stop. If it is less than 0.12, a small amount of deposition will occur in the hole, or the selectivity of the film to be etched with respect to the mask (film etching rate, mask etching rate ) Is reduced.
  • the C x F y (x ⁇ 2) of the gas may be C 4 F 8 . Further, C x F y ( x ⁇ 2) of the gas may be C 5 F 8 .
  • the gas containing C 4 F 6 and N 2 introduced into the processing container is turned into plasma, and the SiO 2 film in the object to be processed in the processing container is converted into a plasma.
  • Plasma etching is performed through an opening pattern of a mask of a metal compound on the SiO 2 film.
  • the gas containing C 4 F 6 and N 2 introduced into the processing container is turned into plasma, and the S i C film in the object to be processed in the processing container is Through the opening pattern of the metal compound mask on the SiC film, It is characterized by performing plasma etching.
  • the gas containing C 4 F 6 and N 2 introduced into the processing container is turned into plasma, and the S i OC film in the object to be processed in the processing container is Plasma etching is performed through the opening pattern of the mask of the metal compound on the SiO 2 C film.
  • the metal compound may be a metal nitride.
  • the metal nitride may be TiN. Further, the metal nitride may be TaN.
  • FIG. 1 is a schematic sectional view of a plasma etching apparatus to which the present invention can be applied.
  • FIG. 2 is a schematic cross-sectional view of a portion to be etched of the object to be processed.
  • FIG. 1 is a sectional view showing a plasma etching apparatus 1 in which the present invention is implemented.
  • the processing container 2 is made of metal, for example, aluminum whose surface is oxidized, and is grounded for safety.
  • a susceptor 5 functioning as a lower electrode of the parallel plate electrode is provided at the bottom of the processing container 2 via an insulator 3.
  • the high pass fill evening (HPF) 6 is connected to this suscept evening.
  • An electrostatic chuck 11 is provided on the susceptor 5, and a workpiece W such as a semiconductor wafer is mounted thereon.
  • the electrostatic chuck 11 has a configuration in which an electrode 12 is interposed between insulators. By applying a DC voltage from a DC power supply 13 connected to the electrode 12, the workpiece W is processed. Adsorb electrostatically.
  • the focus ring 15 is arranged so as to surround the object W to be processed.
  • the focus ring 1 5 is made of S i and S i 0 2, etc., thereby improving the uniformity of etching
  • An upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5.
  • the upper electrode 21 is supported on an upper portion of the processing chamber 2 via an insulator 22, and has a shower head-shaped electrode plate 24 and a support member for supporting the electrode plate 24. 25.
  • a gas inlet 26 is provided at the center of the support 25, and a gas supply pipe 27, a knob 28, a mass flow controller 29, and an etching gas supply source 30 are connected to the gas inlet 26 in this order.
  • a gas such as CF N 2 or Ar is supplied.
  • C x F y (x ⁇ 2) is a C 4 F 6, C 4 F 8S C 5 F 8 or the like.
  • C 4 flow ratio of F 6 for CF 4 is preferably 0.12 to 0.20.
  • N 2 can be used instead of CF 4 .
  • an exhaust pipe 31 is connected to the bottom of the processing container 2, and an exhaust device 35 is connected to the exhaust pipe 31.
  • a gate valve 32 is provided on a side wall of the processing container 2 so that the target object W is transferred between an adjacent load lock chamber (not shown).
  • the upper electrode 21 is connected to a single-pass filter (LPF) 42 and a first high-frequency power supply 40 via a matching unit 41.
  • a second high-frequency power supply 50 is connected to the susceptor 5 serving as a lower electrode via a matching unit 51.
  • the gate valve 32 is opened, and the object W is carried into the processing container 2 and placed on the electrostatic chuck 11.
  • the gate valve 32 is closed and the inside of the processing chamber 2 is depressurized by the exhaust device 35, and then the valve 28 is opened, and the above etching gases, for example, C 4 F 6 and CF 4 are supplied from the etching gas supply source 30.
  • An etching gas composed of Ar or an etching gas composed of C 4 F 6 , N 2 and Ar is supplied.
  • a predetermined emission intensity is detected by an end point detector (not shown), and the etching is terminated based on this.
  • the gas containing C x F y (x ⁇ 2) and CF 4 as described above, or the gas containing N 2 instead of CF 4 when C 4 F 6 is used as C x F y thus, by etching the SiO 2 film 62 through the TN mask 63, it is possible to form a hole that prevents deposition in the etching hole while suppressing the etching stop. It is.
  • the object to be etched is not limited to the SiO 2 film, and the above-described effect can be effectively exerted particularly when at least one of SiO 2 , SiC, and SiOC is used.
  • TiN was used as a mask, TaN is not limited thereto, and TaN can be suitably used, and other metal nitrides can also be used.
  • the configuration of the etching apparatus is not limited to that shown in FIG. Into I
  • Ar is 0.6 L / min (600 s c cm)
  • the SiO 2 film provided on the silicon wafer as shown in FIG. 2 was etched through the opening pattern of the TiN mask. As a result, no deposition occurred in the etching hole, and no etching stop occurred.
  • a film such as a SiO 2 film patterned with a metal compound such as a metal nitride is treated with a gas containing C x F y (x ⁇ 2) and CF 4.
  • a gas containing C x F y (x ⁇ 2) and CF 4 is treated with a gas containing C 4 F 6 and N 2 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

La présente invention concerne un procédé d'attaque chimique au plasma qui consiste à introduire un gaz contenant du CxFy ≥ (x) et CF4 dans une chambre de traitement et à former un plasma constitué dudit gaz, pour ainsi soumettre un film de revêtement d'un article à traiter (W) présent dans la chambre de traitement à une attaque chimique au plasma à travers un modèle présentant des ouvertures placé sur le film de revêtement. Ledit procédé peut être utilisé pour effectuer une attaque chimique au plasma avec suppression du phénomène d'arrêt d'attaque chimique et sans formation de dépôts dans un trou d'attaque chimique.
PCT/JP2003/002749 2002-03-25 2003-03-07 Procédé d'attaque chimique au plasma Ceased WO2003081655A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/508,006 US20050161435A1 (en) 2002-03-25 2003-03-07 Method of plasma etching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002082716A JP4176365B2 (ja) 2002-03-25 2002-03-25 プラズマエッチング方法
JP2002/82716 2002-03-25

Publications (1)

Publication Number Publication Date
WO2003081655A1 true WO2003081655A1 (fr) 2003-10-02

Family

ID=28449155

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2003/002749 Ceased WO2003081655A1 (fr) 2002-03-25 2003-03-07 Procédé d'attaque chimique au plasma

Country Status (5)

Country Link
US (1) US20050161435A1 (fr)
JP (1) JP4176365B2 (fr)
CN (1) CN100367469C (fr)
TW (1) TW200305944A (fr)
WO (1) WO2003081655A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129282B2 (en) * 2006-07-19 2012-03-06 Tokyo Electron Limited Plasma etching method and computer-readable storage medium
JP4948278B2 (ja) * 2006-08-30 2012-06-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5982223B2 (ja) * 2012-08-27 2016-08-31 東京エレクトロン株式会社 プラズマ処理方法、及びプラズマ処理装置
JP2014220387A (ja) * 2013-05-08 2014-11-20 東京エレクトロン株式会社 プラズマエッチング方法
JP6284786B2 (ja) 2014-02-27 2018-02-28 東京エレクトロン株式会社 プラズマ処理装置のクリーニング方法
KR102224847B1 (ko) 2014-10-10 2021-03-08 삼성전자주식회사 반도체 소자의 제조방법
JP6529357B2 (ja) * 2015-06-23 2019-06-12 東京エレクトロン株式会社 エッチング方法
CN106356297B (zh) * 2015-07-16 2019-02-22 中微半导体设备(上海)有限公司 一种氮化钽TaN薄膜的刻蚀方法
JP7008474B2 (ja) 2016-11-30 2022-01-25 東京エレクトロン株式会社 プラズマエッチング方法
US10854430B2 (en) 2016-11-30 2020-12-01 Tokyo Electron Limited Plasma etching method
JP6833657B2 (ja) 2017-11-07 2021-02-24 東京エレクトロン株式会社 基板をプラズマエッチングする方法
JP7195113B2 (ja) * 2018-11-07 2022-12-23 東京エレクトロン株式会社 処理方法及び基板処理装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150463A (ja) * 1998-11-16 2000-05-30 Canon Inc 有機層間絶縁膜のエッチング処理方法
WO2000079586A1 (fr) * 1999-06-24 2000-12-28 Hitachi, Ltd. Procede de production de dispositif a circuit integre semi-conducteur et dispositif a circuit integre semi-conducteur
JP2001007202A (ja) * 1999-06-22 2001-01-12 Sony Corp 半導体装置の製造方法
WO2001037314A1 (fr) * 1999-11-15 2001-05-25 Lam Research Corporation Matieres et reactions chimiques au gaz pour systemes de traitement

Family Cites Families (10)

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US5300460A (en) * 1989-10-03 1994-04-05 Applied Materials, Inc. UHF/VHF plasma for use in forming integrated circuit structures on semiconductor wafers
US5468339A (en) * 1992-10-09 1995-11-21 Advanced Micro Devices, Inc. Plasma etch process
US5700740A (en) * 1996-03-25 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Prevention of corrosion of aluminum interconnects by removing corrosion-inducing species
US5942446A (en) * 1997-09-12 1999-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer
JPH11340321A (ja) * 1998-05-27 1999-12-10 Sony Corp 半導体装置およびその製造方法
US6007733A (en) * 1998-05-29 1999-12-28 Taiwan Semiconductor Manufacturing Company Hard masking method for forming oxygen containing plasma etchable layer
US6319822B1 (en) * 1998-10-01 2001-11-20 Taiwan Semiconductor Manufacturing Company Process for forming an integrated contact or via
JP3400770B2 (ja) * 1999-11-16 2003-04-28 松下電器産業株式会社 エッチング方法、半導体装置及びその製造方法
JP2001274264A (ja) * 2000-03-24 2001-10-05 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6410424B1 (en) * 2001-04-19 2002-06-25 Taiwan Semiconductor Manufacturing Company Process flow to optimize profile of ultra small size photo resist free contact

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150463A (ja) * 1998-11-16 2000-05-30 Canon Inc 有機層間絶縁膜のエッチング処理方法
JP2001007202A (ja) * 1999-06-22 2001-01-12 Sony Corp 半導体装置の製造方法
WO2000079586A1 (fr) * 1999-06-24 2000-12-28 Hitachi, Ltd. Procede de production de dispositif a circuit integre semi-conducteur et dispositif a circuit integre semi-conducteur
WO2001037314A1 (fr) * 1999-11-15 2001-05-25 Lam Research Corporation Matieres et reactions chimiques au gaz pour systemes de traitement

Also Published As

Publication number Publication date
JP2003282539A (ja) 2003-10-03
US20050161435A1 (en) 2005-07-28
CN1643665A (zh) 2005-07-20
JP4176365B2 (ja) 2008-11-05
CN100367469C (zh) 2008-02-06
TWI293480B (fr) 2008-02-11
TW200305944A (en) 2003-11-01

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