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WO2003050865A1 - Moule utilise dans un procede d'encapsulation en remplissage par le dessous pour puces a bosses multiples - Google Patents

Moule utilise dans un procede d'encapsulation en remplissage par le dessous pour puces a bosses multiples Download PDF

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Publication number
WO2003050865A1
WO2003050865A1 PCT/KR2002/002307 KR0202307W WO03050865A1 WO 2003050865 A1 WO2003050865 A1 WO 2003050865A1 KR 0202307 W KR0202307 W KR 0202307W WO 03050865 A1 WO03050865 A1 WO 03050865A1
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WO
WIPO (PCT)
Prior art keywords
encapsulation process
mold
encapsulant
cavity
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2002/002307
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English (en)
Inventor
Hwa-Il Seo
Kwang-Sun Kim
Se-Jin Han
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Individual
Original Assignee
Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to AU2002366673A priority Critical patent/AU2002366673A1/en
Publication of WO2003050865A1 publication Critical patent/WO2003050865A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/17—Component parts, details or accessories; Auxiliary operations
    • B29C45/26—Moulds
    • B29C45/34—Moulds having venting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the present invention relates to a mold, and more particularly to a mold being used for an encapsulation process of multi flip chip, in which semiconductor chips are directly mounted on a substrate.
  • a flip chip is constituted of directly mounting a semiconductor chip on a substrate, where the inputs/outputs of the semiconductor chip and the substrate are connected to each other by solder ball, conductive bonding agent, and so on.
  • a flip chip can minimize the connecting wires between a semiconductor chip and a substrate, and thereby achieve a high operation speed.
  • a flip chip has a disadvantage that a bumper, which is a bonding-point, is occasionally being cracked during the manufacturing process due to the difference between the thermal expansion coefficients of a substrate and a semiconductor chip.
  • an underfill encapsulation process locating a flip chip in a cavity of a mold and thereafter injecting encapsulant to fill the surroundings of the semiconductor chip as well as the space between the semiconductor chip and the substrate, is being required for providing a mechanical and electrical reinforcement to the flip chip.
  • a method of injecting encapsulant by using the capillarity phenomenon has been used for underfill encapsulation process in the prior art, however, it has problems that the price of encapsulant used therein is expensive and the processing speed is very slow.
  • a couple of new methods for encapsulation process have been recently proposed such as an encapsulation method of using a vacuum, developed by M. K. Schwiebert, W. H. Leong and K. Banerji, and a compressed underfill encapsulation method developed by K. K. Wang and Se-Jin Hahn, the inventor of the present invention.
  • the encapsulation method of using a vacuum mentioned above remarkably reduces the processing time required for injecting the encapsulant into the cavity of a mold, wherein a flip chip is located, however, the maximum driving power is limited to the atmospheric pressure. Consequently, the method of using a vacuum described above can be effectively applicable to an encapsulation process using low-viscosity encapsulant, however, it is not suitable for the process using high-viscosity encapsulant.
  • the compressed underfill encapsulation method mentioned above is a method of injecting the encapsulant with a high-pressure into the cavity of a mold, wherein a flip chip is located. It also remarkably reduces the processing time required for filling the cavity with the encapsulant, however, the encapsulant, remained in the mold after the injecting process, has to be washed-out before carrying out the next encapsulation process, and thus, it requires large amount of processing time for carrying out the process.
  • the distance between the chip and the side-wall of the cavity is arbitrarily set in a mold, used for the vacuum encapsulation process or the compressed underfill encapsulation process described above. And thus, as described in FIG.
  • FIG. 1 is a view illustrating the encapsulation result of encapsulating a chip, whose long-directional and short-directional lengths are 10mm each, apart by about 0.1mm from a substrate, by using a mold in which the distance between the chip and the side-wall of the cavity is 0.8mm. It shows that a void is formed in the upper center portion.
  • a mold for underfill encapsulation process of multi flip chip wherein semiconductor chips are directly mounted on a substrate.
  • the mold for underfill encapsulation process of multi flip chip comprises a multiplicity of cavities, open to the direction of facing said substrate, in each of which each of said semiconductor chips is accommodated during said encapsulation process; a multiplicity of encapsulant inlets, formed at one side of said cavities, for guiding the injected encapsulant into said cavities during said encapsulation process; and a multiplicity of encapsulant outlets, formed at the other side of said cavities, for exhausting the encapsulant and air in said cavities to the outside of said cavities during said encapsulation process.
  • the maximum allowable separation distance(b) between said semiconductor chip and the side- wall of said cavity is limited according to the long-directional distance(J-F) of said semiconductor chip, the short-directional distance(D) of said semiconductor chip, and the spacing(b) between the bottom surface of said semiconductor chip and said substrate.
  • the mold for underfill encapsulation process of multi flip chip comprises a cavity, open to the direction of facing said substrate, in which said semiconductor chips are accommodated during said encapsulation process; an encapsulant inlet, formed at one side of said cavity, for guiding the injected encapsulant into said cavity during said encapsulation process; and an encapsulant outlet, formed at the other side of said cavity, for exhausting the encapsulant and air in said cavity to the outside of said cavity during said encapsulation process.
  • the maximum allowable separation distance(b) between the semiconductor chip located at the side of said cavity, among said semiconductor chips accommodated in said cavity, and the side-wall of said cavity is limited according to the long-directional distance(FF) of said semiconductor chip, the short-directional distance ) of said semiconductor chip, and the spacing(b) between the bottom surface of said semiconductor chip and said substrate.
  • FIG. 1 is a view illustrating the encapsulation result of encapsulating a flip chip in prior art.
  • FIG. 2a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the first embodiment of the present invention.
  • FIG. 2b is a sectional view illustrating the structure of the mold described in FIG. 2a.
  • FIG. 3a and FIG. 3b are views for explaining the maximum allowable separation distance between said semiconductor chip and the side-wall of said cavity, in accordance with the first embodiment of the present invention.
  • FIG. 4 is a view illustrating the encapsulation result of encapsulating a flip chip, in accordance with the first embodiment of the present invention.
  • FIG. 5a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the second embodiment of the present invention.
  • FIG. 5b is a sectional view illustrating the structure of the mold described in FIG. 5a.
  • FIG. 6a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the third embodiment of the present invention.
  • FIG. 6b is a sectional view illustrating the structure of the mold described in FIG.
  • FIG. 7a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the fourth embodiment of the present invention.
  • FIG. 7b is a sectional view illustrating the structure of the mold described in FIG. 7a.
  • FIG. 8a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the fifth embodiment of the present invention.
  • FIG. 8b is a sectional view illustrating the structure of the mold described in FIG. 8a.
  • FIG. 9a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the sixth embodiment of the present invention.
  • FIG. 9b is a sectional view illustrating the structure of the mold described in FIG. 9a.
  • FIG. 10a is a bottom view of a mold for underfill encapsulation process of multi flip chip, in accordance with the seventh embodiment of the present invention.
  • FIG. 10b is a sectional view illustrating the structure of the mold described in FIG. 10a.
  • FIG. 2a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the first embodiment of the present invention
  • FIG. 2b is a sectional view illustrating the structure of the mold described in FIG. 2a.
  • a mold in accordance with the first embodiment of the present invention comprises numbers of cavities(310), encapsulant inlets(320), injection holes(330), encapsulant outlets(340), and exhaustion holes(350).
  • Each cavity(310) is open toward the substrate(2) and has a size to be able to accommodate one semiconductor chip(l) mounted on the substrate(2) during the encapsulation process.
  • a cavity(310) is formed to be bigger than a semiconductor chip(l).
  • it is formed to limit the surrounding areas of the semiconductor chip(l) within a specific value according to the size of the semiconductor chip(l).
  • W is the long-directional length of the semiconductor chip(l) located in the cavity(310)
  • D is the short-directional length of the semiconductor chip(l)
  • h is the spacing between the bottom surface of the semiconductor chip(l) and the substrate(2).
  • 0.1542 is an experimentally obtained constant.
  • the maximum allowable separation distance(b) is about 0.71mm.
  • FIG. 4a shows the case that the width of the surrounding area(i. e., separation distance) is about 0.6mm
  • FIG. 4b shows the case that the width of the surrounding area is about 0.7mm.
  • the cavity(310) is constituted to have a sufficient height with which the mold is separated from the upper surface of a semiconductor chip(l), during the encapsulation process, with a certain distance. And thus, even when numbers of flip chips having different heights are being encapsulated simultaneously, it prevents that comparatively high semiconductor chips are being damaged by being contacted with the mold.
  • the cavity(310) is constituted that the spacing between the mold surface(314) and the semiconductor chip(l) is smaller than the spacing( ⁇ ) between the bottom surface of the semiconductor chip(l) and the upper surface of the substrate(2).
  • An encapsulant inlet(320) is formed at one side of each cavity(310) to be stream-linked to the cavity(310) and guides the injected encapsulant to the inside of the cavity(310) during the encapsulation process.
  • Each injection hole(330) is formed to the direction of mold thickness and stream-linked to each encapsulant inlet(320). Through the injection hole(330), an encapsulant injecting plunger(not described in the figure) of the encapsulation apparatus injects encapsulant into the cavity(310) by compression during the encapsulation process.
  • Each encapsulant outlet(340) is formed at the other side of each cavity(310) to be stream-linked to the cavity(310) and exhausts the surplus encapsulant passing through the cavity(310) and the air inside the cavity(310) during the encapsulation process.
  • Each exhaustion hole(350) is formed to the direction of mold thickness, i. e. parallel to the injection hole(330), and stream-linked to each encapsulant outlet(340).
  • the exhaustion hole(350) guides the encapsulant and air being exhausted through the encapsulant outlet(340) to the outside.
  • a mold in accordance with the present invention can encapsulate numbers of flip chips at the same time with being equipped with numbers of cavities(310), each of which has an optimal size according to the size of a semiconductor chip(l) to be encapsulated therein. And thus, it can prevent the void formation in the space between the semiconductor chip(l) and the substrate(2) and the damage of the semiconductor chip(l) due to the direct contact with the mold.
  • a mold for underfill encapsulation process of multi flip chip in accordance with the present invention is not limited to the first embodiment described above, and it can also be embodied to have various modified structures that will be describes hereinafter.
  • FIG. 5a ⁇ FIG. 10b the second ⁇ the seventh embodiments of a mold for underfill encapsulation process of multi flip chip in accordance with the present invention are now being described in detail.
  • the detail description is mainly fulfilled on the parts different from previous embodiments, and the explanation on identical(or very similar) parts is omitted.
  • FIG. 5a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the second embodiment of the present invention
  • FIG. 5b is a sectional view illustrating the structure of the mold described in FIG. 5a.
  • a mold in accordance with the second embodiment of the present invention comprises numbers of cavities(610), encapsulant inlets(620), injection holes(630), encapsulant outlets(640), exhaustion holes(650), and elastic bumpers(660).
  • the cavities(610), encapsulant inlets(620), injection holes(630), encapsulant outlets(640) and exhaustion holes(650) are formed to be identical to those of the first embodiment and do the same function, and thus detail description on these elements will be omitted.
  • the maximum allowable width of the surrounding area around the semiconductor chip(l) located in the cavity(610) is also limited to the value calculated by the equation[Eqn. (1)] described in the first embodiment.
  • Each elastic bumper(660) is mounted at the upper surface of each cavity(610) facing a semiconductor chip(l) or the bottom surface of the mold facing the upper surface of the substrate(2), and thus it directly contacts with the upper surface of a semiconductor chip(l) or the upper surface of the substrate(2) during the encapsulation process. With this structure of equipping elastic bumpers(660), even when numbers of flip chips having different heights are being encapsulated simultaneously, it can prevent that the semiconductor chip(l) and the substrate(2) are being damaged by being contacted with the mold.
  • FIG. 6a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the third embodiment of the present invention
  • FIG. 6b is a sectional view illustrating the structure of the mold described in FIG. 6a.
  • a mold in accordance with the third embodiment of the present invention comprises numbers of cavities(710), numbers of encapsulant inlets(720), a common injection hole(730), numbers of encapsulant outlets(740), numbers of exhaustion holes(750), and numbers of runners(760).
  • the cavities(710), encapsulant inlets(720) and encapsulant outlets(740) are formed to be identical to those of the first embodiment and do the same function, and thus detail description on these elements will be omitted.
  • the maximum allowable width of the surrounding area around the semiconductor chip(l) located in the cavity(710) is also limited to the value calculated by the equation[Eqn. (1)] described in the first embodiment.
  • the common injection hole(730) is formed to be stream-linked to the encapsulant inlets(720), formed at one side of a certain number of cavities(710) located at one side of the mold, to inject the encapsulant simultaneously to the cavities(710) located at one side of the mold during the encapsulation process.
  • Each exhaustion hole(750) is stream-linked to each of the encapsulant outlets(740), formed at the other side of a certain number of cavities(710) located at the other side of the mold, to guide the encapsulant and air exhausted from the cavities(710) located at the other side of the mold to the outside during the encapsulation process.
  • Each runner(760) is stream-linked to an encapsulant outlet(740) of a cavity(710) and an encapsulant inlet(720) of the adjacent cavity(710) to guide the encapsulant and air exhausted through the encapsulant outlet(740) to the encapsulant inlet(720) connected thereto.
  • adjacent cavities(710) are stream-linked to each other by runners(760).
  • the encapsulant inlets(720) and the encapsulant outlets(740) of the cavities are formed to be the parts of the runners(760).
  • FIG. 7a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the fourth embodiment of the present invention.
  • a mold in accordance with the fourth embodiment of the present invention comprises numbers of cavities(810), numbers of encapsulant inlets(820), a common injection hole(830), numbers of encapsulant outlets(840), numbers of exhaustion holes(850), numbers of runners(860), and numbers of elastic bumpers(870).
  • the cavities(810), encapsulant inlets(820), common injection hole(830), encapsulant outlets(840), exhaustion holes(850) and runners(860) are formed to be identical to those of the third embodiment and do the same function, and thus detail description on these elements will be omitted.
  • the maximum allowable width of the surrounding area around the semiconductor chip(l) located in the cavity(810) is also limited to the value calculated by the equation[Eqn. (1)] described in the first embodiment.
  • the encapsulant inlets(820) and outlets(840) of adjacent cavities(810) are formed to be the parts of the runners(860).
  • Each elastic bumper(870) is mounted at the upper surface of each cavity(810) facing a semiconductor chip(l) or the bottom surface of the mold facing the upper surface of the substrate(2), and thus it directly contacts with the upper surface of a semiconductor chip(l) or the upper surface of the substrate(2) during the encapsulation process.
  • FIG. 8a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the fifth embodiment of the present invention
  • FIG. 8b is a sectional view illustrating the structure of the mold described in FIG. 8a.
  • a mold in accordance with the fifth embodiment of the present invention comprises numbers of cavities(910), numbers of encapsulant inlets(920), a common injection hole(930), numbers of encapsulant outlets(940), and numbers of runners(950).
  • the cavities(910), encapsulant inlets(920), common injection hole(930) and runners(950) are formed to be identical to those of the third embodiment and do the same function, and thus detail description on these elements will be omitted.
  • the maximum allowable width of the surrounding area around the semiconductor chip(l) located in the cavity(910) is also limited to the value calculated by the equation[Eqn. (1)] described in the first embodiment.
  • the encapsulant inlets(920) and outlets(940) of adjacent cavities(910) are formed to be the parts of the runners(950).
  • the outlets(940) formed at the cavities(910) located at the other side of the mold are constituted to be extended to the outside of the mold.
  • the outlets(940) of the cavities(910) located at the other side of the mold guide the encapsulant and air exhausted from the cavities(910) directly to the outside.
  • a mold in accordance with the fifth embodiment of the present invention does not need the exhaustion holes that are required for the molds in accordance with the first ⁇ the fourth embodiments.
  • an external device such as an external vacuum pump(not described in the figure), for vacuuming out the surplus encapsulant and air, can be easily connected thereto.
  • FIG. 9a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the sixth embodiment of the present invention
  • FIG. 9b is a sectional view illustrating the structure of the mold described in FIG. 9a.
  • a mold in accordance with the sixth embodiment of the present invention comprises a cavity(l ⁇ l ⁇ ), an encapsulant inlet(1020), an injection hole(1030), an encapsulant outlet(1040), and an exhaustion hole(1050).
  • the cavity(l ⁇ l ⁇ ) is formed to be the size able to simultaneously accommodate numbers of semiconductor chips(l) mounted on the substrate(2). And, the maximum allowable widths of the surrounding areas around the semiconductor chips(l) located at the sides of the cavity(l ⁇ l ⁇ ) are limited to the values calculated by the equation[Eqn. (1)] described in the first embodiment.
  • the encapsulant inlet(1020), the injection hole(1030), the encapsulant outlet(1040) and the exhaustion hole(1050) are formed to be identical to those of the first embodiment and do the same function, and thus detail description on these elements will be omitted.
  • a mold in accordance with the sixth embodiment of the present invention is able to carry out an encapsulation process of numbers of semiconductor chips(l) with much simpler structure than those of the first ⁇ the fifth embodiments.
  • FIG. 10a is a bottom view of a mold for underfill encapsulation process of multi flip chip in accordance with the seventh embodiment of the present invention
  • FIG. 10b is a sectional view illustrating the structure of the mold described in FIG. 10a.
  • a mold in accordance with the seventh embodiment of the present invention comprises a cavity(l l l ⁇ ), an encapsulant inlet(1120), an injection hole(1130), an encapsulant outlet(1140), an exhaustion hole(1150), and numbers of elastic bumpers( 1160) .
  • the cavity(l l l ⁇ ), the encapsulant inlet(1120), the injection hole(1130), the encapsulant outlet(1140) and the exhaustion hole(1150) are formed to be identical to those of the sixth embodiment and do the same function, and thus detail description on these elements will be omitted. And, just like in the sixth embodiment, the maximum allowable widths of the surrounding areas around the semiconductor chips(l) located at the sides of the cavity(l l l ⁇ ) are limited to the values calculated by the equation[Eqn. (1)] described in the first embodiment.
  • Each elastic bumper(1160) is mounted at the upper surface of the cavity(l l l ⁇ ) facing each semiconductor chip(l) or the bottom surface of the mold facing the upper surface of the substrate(2), and thus it directly contacts with the upper surface of the semiconductor chip(l) or the upper surface of the substrate(2) to prevent the damage of the semiconductor chip(l) and/or the substrate(2) possibly occurred due to the direct contact with the mold during the encapsulation process.
  • a mold for underfill encapsulation process of multi flip chip in accordance with the present invention is able to encapsulate numbers of flip chips at the same time, and thus it reduces the processing time required for encapsulation process and thereby remarkably improves the overall productivity.
  • a mold in accordance with the present invention is equipped with cavities(310, 610, 710, 810, 910) -or, a cavity(1010. 1110)- having the size with which the void formation and the damage of the semiconductor chip(l) due to direct contact can be prevented during the encapsulation process, and thus it can remarkably reduce the defective fraction occurred in the encapsulation process.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)

Abstract

L'invention concerne un moule utilisé dans un procédé d'encapsulation en remplissage par le dessous pour puces à bosses multiples. Le moule présente plusieurs cavités accueillant chacune les puces considérées. Plusieurs entrées d'agent d'enrobage guident l'agent injecté dans les cavités, et plusieurs sorties d'agent d'enrobage évacuent l'agent et l'air à l'extérieur de ces cavités. Le moule décrit permet d'encapsuler plusieurs puces à bosses à la fois, réduisant ainsi le temps de traitement requis par l'encapsulation et améliorant donc remarquablement la productivité globale.
PCT/KR2002/002307 2001-12-13 2002-12-09 Moule utilise dans un procede d'encapsulation en remplissage par le dessous pour puces a bosses multiples Ceased WO2003050865A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002366673A AU2002366673A1 (en) 2001-12-13 2002-12-09 Mold for used in multi flip-chip underfill encapsulation process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2001-0078746A KR100400496B1 (ko) 2001-12-13 2001-12-13 멀티 플립칩의 언더필 인캡슐레이션 공정용 몰드
KR10-2001-0078746 2001-12-13

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WO2003050865A1 true WO2003050865A1 (fr) 2003-06-19

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PCT/KR2002/002307 Ceased WO2003050865A1 (fr) 2001-12-13 2002-12-09 Moule utilise dans un procede d'encapsulation en remplissage par le dessous pour puces a bosses multiples

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AU (1) AU2002366673A1 (fr)
WO (1) WO2003050865A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005006433A3 (fr) * 2003-06-30 2005-03-24 Intel Corp Coiffe de matiere a mouler dans un boitier a matrices multiples d'elements dotees de connexions par billes et procede de fabrication correspondant
WO2005043612A1 (fr) * 2003-09-09 2005-05-12 Fico B.V. Procede et dispositif permettant d'encapsuler des composants electroniques a l'aide d'un element de pression flexible
WO2007007959A1 (fr) 2005-07-13 2007-01-18 Seoul Semiconductor Co., Ltd. Moule pour former un organe de moulage et procédé de fabrication d’un organe de moulage l’utilisant
JP2014036119A (ja) * 2012-08-09 2014-02-24 Apic Yamada Corp 樹脂モールド装置
US10276424B2 (en) 2017-06-30 2019-04-30 Applied Materials, Inc. Method and apparatus for wafer level packaging
CN114156190A (zh) * 2021-11-30 2022-03-08 深圳市德明新微电子有限公司 一种封装用治具及电路元器件的封装方法

Citations (3)

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