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AU2002366673A1 - Mold for used in multi flip-chip underfill encapsulation process - Google Patents

Mold for used in multi flip-chip underfill encapsulation process

Info

Publication number
AU2002366673A1
AU2002366673A1 AU2002366673A AU2002366673A AU2002366673A1 AU 2002366673 A1 AU2002366673 A1 AU 2002366673A1 AU 2002366673 A AU2002366673 A AU 2002366673A AU 2002366673 A AU2002366673 A AU 2002366673A AU 2002366673 A1 AU2002366673 A1 AU 2002366673A1
Authority
AU
Australia
Prior art keywords
mold
encapsulation process
chip underfill
underfill encapsulation
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002366673A
Other languages
English (en)
Inventor
Se-Jin Han
Kwang-Sun Kim
Hwa-Il Seo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU2002366673A1 publication Critical patent/AU2002366673A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29CSHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/17Component parts, details or accessories; Auxiliary operations
    • B29C45/26Moulds
    • B29C45/34Moulds having venting means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
AU2002366673A 2001-12-13 2002-12-09 Mold for used in multi flip-chip underfill encapsulation process Abandoned AU2002366673A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2001-0078746A KR100400496B1 (ko) 2001-12-13 2001-12-13 멀티 플립칩의 언더필 인캡슐레이션 공정용 몰드
KR10-2001-0078746 2001-12-13
PCT/KR2002/002307 WO2003050865A1 (fr) 2001-12-13 2002-12-09 Moule utilise dans un procede d'encapsulation en remplissage par le dessous pour puces a bosses multiples

Publications (1)

Publication Number Publication Date
AU2002366673A1 true AU2002366673A1 (en) 2003-06-23

Family

ID=19716973

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002366673A Abandoned AU2002366673A1 (en) 2001-12-13 2002-12-09 Mold for used in multi flip-chip underfill encapsulation process

Country Status (3)

Country Link
KR (1) KR100400496B1 (fr)
AU (1) AU2002366673A1 (fr)
WO (1) WO2003050865A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7294533B2 (en) 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
NL1024248C2 (nl) * 2003-09-09 2005-03-10 Fico Bv Werkwijze en inrichting voor het met behulp van een flexibel drukelement omhullen van elektronische componenten.
KR100761387B1 (ko) 2005-07-13 2007-09-27 서울반도체 주식회사 몰딩부재를 형성하기 위한 몰드 및 그것을 사용한 몰딩부재형성방법
JP2014036119A (ja) * 2012-08-09 2014-02-24 Apic Yamada Corp 樹脂モールド装置
US10276424B2 (en) 2017-06-30 2019-04-30 Applied Materials, Inc. Method and apparatus for wafer level packaging
CN114156190A (zh) * 2021-11-30 2022-03-08 深圳市德明新微电子有限公司 一种封装用治具及电路元器件的封装方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122136A (ja) * 1985-11-08 1987-06-03 Hitachi Ltd レジンモールド半導体の製造方法および装置
JPH03216309A (ja) * 1990-01-22 1991-09-24 Matsushita Electric Ind Co Ltd Tabチップ樹脂封止方法
US5817545A (en) * 1996-01-24 1998-10-06 Cornell Research Foundation, Inc. Pressurized underfill encapsulation of integrated circuits
JP3352923B2 (ja) * 1997-10-08 2002-12-03 シャープ株式会社 樹脂封止用モールド金型
JPH11121488A (ja) * 1997-10-15 1999-04-30 Toshiba Corp 半導体装置の製造方法及び樹脂封止装置
JP3130868B2 (ja) * 1998-06-30 2001-01-31 山形日本電気株式会社 薄型パッケージの樹脂封止方法
KR100653607B1 (ko) * 1999-11-16 2006-12-05 삼성전자주식회사 복수의 보조-런너를 갖는 반도체 칩 패키지용 수지 성형장치

Also Published As

Publication number Publication date
KR100400496B1 (ko) 2003-10-08
KR20030048743A (ko) 2003-06-25
WO2003050865A1 (fr) 2003-06-19

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase