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WO2002011202A2 - Procede et dispositif de production de substrats de connexion de composants electroniques - Google Patents

Procede et dispositif de production de substrats de connexion de composants electroniques Download PDF

Info

Publication number
WO2002011202A2
WO2002011202A2 PCT/DE2001/002892 DE0102892W WO0211202A2 WO 2002011202 A2 WO2002011202 A2 WO 2002011202A2 DE 0102892 W DE0102892 W DE 0102892W WO 0211202 A2 WO0211202 A2 WO 0211202A2
Authority
WO
WIPO (PCT)
Prior art keywords
embossing
bumps
layer
substrate body
roller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2001/002892
Other languages
German (de)
English (en)
Other versions
WO2002011202A3 (fr
Inventor
Richard Thelen
Jozef Van Puymbroeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens Dematic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Dematic AG filed Critical Siemens Dematic AG
Publication of WO2002011202A2 publication Critical patent/WO2002011202A2/fr
Publication of WO2002011202A3 publication Critical patent/WO2002011202A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
    • B29C43/32—Component parts, details or accessories; Auxiliary operations
    • B29C43/44—Compression means for making articles of indefinite length
    • B29C43/46—Rollers
    • B29C2043/461—Rollers the rollers having specific surface features
    • B29C2043/463—Rollers the rollers having specific surface features corrugated, patterned or embossed surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0143—Using a roller; Specific shape thereof; Providing locally adhesive portions thereon
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0014—Shaping of the substrate, e.g. by moulding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Definitions

  • the invention relates to a method and a device for producing connection substrates for at least one electronic component each with a substrate body made of high-temperature-resistant thermoplastic material, the melting point of which lies above the soldering temperature used for the connection contacting, in each case in one piece at least on one surface bumps and / or depressions be molded on.
  • the invention relates to the production of a so-called polymer stud grid array (PSGA TM), contact bumps being integrally formed on each substrate and provided with a solderable contact surface, each of which in turn is connected to that on the substrate by means of conductor tracks arranged semiconductor device can be connected.
  • PSGA TM polymer stud grid array
  • Integrated circuits but also other electronic components, e.g. Surface wave filters and the like are increasingly miniaturized and at the same time provided with more and more connections.
  • the problems of contacting in a confined space are solved with new housing shapes that are designed as single, Few or multi-chip modules.
  • Substrates with a so-called ball grid array (BGA) are known in which solder bumps arranged flat on the underside of the substrate enable surface mounting on a printed circuit board or assembly.
  • MID Molded Interconnection Devices
  • MID Molded Interconnection Devices
  • the so-called MID technology uses three-dimensional injection molded parts with integrated conductor tracks instead of conventional printed circuits.
  • Several mechanical and electrical functions can be integrated into the three-dimensional injection molded parts with structured metallization.
  • the housing support function takes over guides and snap connections at the same time, while the metallization layer serves not only as a wiring and connection function but also as an electromagnetic shield and ensures good heat dissipation.
  • Injection molded parts of this type with integrated conductor tracks are described, for example, in DE-A-37 32 249 and EP-A-0 361 192.
  • EP-B-782765 has already proposed a so-called polymer stud grid array (PSGA TM) which combines the advantages of a ball grid array (BGA) with the advantages of MID technology.
  • PSGA TM polymer stud grid array
  • This design which is suitable for single, Few or multi-chip modules, essentially comprises an injection-molded, three-dimensional substrate made of an electrically insulating polymer, on one side of which molded polymer bumps are arranged during injection molding, on each of which in turn a solderable end surface has an outer surface.
  • external connection forms. Conductor tracks on the substrate connect these external connections to internal connections, which in turn are electrically conductively connected to the connections of a chip arranged on the substrate or another component.
  • N ⁇ ⁇ iQ ⁇ rt ⁇ 3 J: 0- 3 d 0 d cn PH ⁇ P- rt X ⁇ d « ⁇ P- od iQ P ⁇ ⁇ tr H ⁇ IQ P- cn d ⁇ D: ⁇ P- P ⁇ P- dd ⁇ ⁇ 3 cn P- ⁇ er ⁇ dd. d ⁇ rt ⁇ ⁇ S! rt P- iQ 3 ⁇ d cn tr ⁇ cn P P- p ⁇ od rt cn tr
  • P- P ⁇ ddd P P- ⁇ ⁇ rt o ⁇ X ⁇ ⁇ DJ P PJ and others ⁇ rt P- X 1 Hl h- "P- ⁇ ⁇ ⁇ P- ⁇ P" ⁇ Q s ⁇ P- tr 1 d ⁇ P tr cn ⁇ g ⁇ ⁇ tr hd ⁇ rt ⁇ P dd P dod ⁇ ⁇ ⁇ P 1 rt d P ⁇ H
  • CD d ⁇ ⁇ ⁇ d d d ⁇ d
  • CD P d r- "tr ⁇ >
  • P P P ftj P P Cd ⁇ rt cn w 1 ⁇ cn K rt ⁇ tr ⁇ J ⁇ P- tr p tr ⁇ P. Q 3 rt
  • FIG. 3A is a film similar to Figure 2A, but with some trench draw ⁇ metallization,
  • FIG. 3B shows an embossing stamp and a substrate body embossed from a film according to FIG. 3A, each in a schematic representation
  • FIG. 4 shows the schematic representation of the production of a substrate body provided with bumps from a granulate by means of an embossing-rolling device
  • FIG. 5 shows the production of a substrate body provided with bumps from a film by means of an embossing-rolling device
  • FIG. 6 shows a schematic section through an embossing roller designed according to the invention with an embossing layer covering almost the entire circumferential area
  • FIG. 7 shows an embossing roller in a configuration modified from FIG. 6,
  • FIGS. 9A to 9C show a section of an embossing roller according to FIG. 7 or FIG. 8 in different phases when embossing an uncoated substrate film,
  • FIGS. 10A and 10B show the detail of an embossing roller in two different phases when embossing a substrate film with a standard metallic surface coating
  • FIGS. 11A and 11B show a section of an embossing roller with embossing layers specified as standard, shown in two phases when embossing a substrate film, on the surface of which a metal coating is specified as a mask; external heating and cooling devices are generated,
  • Figure 13 is an embossing roller with a heating device arranged inside and
  • FIG. 14 shows an arrangement with an embossing roller and a narrowly defined melting zone.
  • FIG. 3A in turn shows a film 1 with metal layers 6 and 7 on both sides, but in contrast to FIG. 2A, recesses 8 are now only provided at the locations of the top layer 6, at which a bump 3 is actually to be produced.
  • an embossing stamp 11 can be used, which has embossing recesses 5 in a standard grid, since in this case the metallization layer 6 serves as a mask and only allows embossing of bumps 3 where recesses 8 are provided.
  • films with a thickness of 0.1 to 0.5 mm, preferably of 0.2 to 0.3 mm are suitable for the production of PSGA TM substrates.
  • Solder bumps with a height of 0.02 mm to 0.4 mm and a diameter of 0.04 mm to 0.5 mm are then produced on these foils.
  • a range between 0.2 mm and 1 mm can be used as the grid dimension.
  • the metallization of the film surface described in FIGS. 2 and 3 can be formed, for example, with a copper layer of 25 ⁇ m.
  • the further processing of the substrate bodies 2, 10 or 12 thus produced can be carried out in a manner known per se.
  • the bumps 3 are preferably used as contact bumps and are provided with a solderable contact layer 13 for this purpose. These bumps 13 are connected to the connections of the semiconductor component or other components via conductor tracks 14 (FIG. 1B). If a metal layer 6 is already present according to FIG. 2B, this metal layer can subsequently be structured into conductor tracks 15, which in turn are then connected to the metal layer 13. It is co co rv> IV ) I- 1 - 1 c ⁇ o C ⁇ o cn ⁇ c ⁇
  • ⁇ PJ CD ⁇ d P- P- P- ⁇ ⁇ ⁇ rt P- 0 ⁇ 13 ⁇ DJ 0 P PJ P- d ⁇ ro P- d ⁇ ⁇ P P- 0 P- cn rt P 1 P P. d inter alia d P EP 01 PP tr 3 P- 3 P "P ⁇ P 1 ⁇ P- inter alia 01 dd CD: P 1 inter alia
  • CD tr d rt P ⁇ ⁇ ⁇ P cn - NP 3 13 P- P- 13 es ⁇ P Hl P- d • dd and others 3 among others • DJ Cfl hd P ⁇ o ⁇ ⁇ d tu PJ o tr o O 01 ⁇ P. ⁇ d ⁇ P d PJ P 53 ⁇ dd ⁇ including ESJ P " ⁇ tr ⁇ ⁇ P- 01 PP 1 P
  • P- P CD DJ ⁇ d and others P ⁇ 53 P-. ⁇ P ⁇ d ⁇ cn
  • DJ P P 01 P- ⁇ ⁇ P " ⁇ and others DJ d CD: ⁇ P. P- rt and others Pi ⁇ d d d ⁇ d ⁇ PJ p- P tr ⁇

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Combinations Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

Pour produire des substrats de connexion destinés à des micro-plaquettes semi-conductrices, de préférence des substrats PSGA (polymer stud grid array), on chauffe un corps brut (1) de préférence un film et on produit sur au moins une de ses surfaces des bosses (3) et/ou des creux à l'aide d'un rouleau de gaufrage. On utilise comme matériau du corps substrat des thermoplastiques résistants aux températures élevées, de préférence des polymères à cristaux liquides (LPC). De préférence, leur surface peut être pourvue d'une couche métallique qui, à son tour, est dotée de trous en tant qu'auxiliaires de gaufrage.
PCT/DE2001/002892 2000-07-31 2001-07-31 Procede et dispositif de production de substrats de connexion de composants electroniques Ceased WO2002011202A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10037292.9 2000-07-31
DE10037292A DE10037292A1 (de) 2000-07-31 2000-07-31 Verfahren zur Herstellung von Anschlußsubstraten für Halbleiterkomponenten

Publications (2)

Publication Number Publication Date
WO2002011202A2 true WO2002011202A2 (fr) 2002-02-07
WO2002011202A3 WO2002011202A3 (fr) 2003-01-23

Family

ID=7650849

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/DE2001/002892 Ceased WO2002011202A2 (fr) 2000-07-31 2001-07-31 Procede et dispositif de production de substrats de connexion de composants electroniques
PCT/DE2001/002891 Ceased WO2002011201A2 (fr) 2000-07-31 2001-07-31 Procede et dispositif de production de substrats de connexion de composants electroniques

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/002891 Ceased WO2002011201A2 (fr) 2000-07-31 2001-07-31 Procede et dispositif de production de substrats de connexion de composants electroniques

Country Status (3)

Country Link
DE (1) DE10037292A1 (fr)
TW (1) TW531817B (fr)
WO (2) WO2002011202A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2747132A1 (fr) * 2012-12-18 2014-06-25 Imec Procédé permettant de transférer une feuille de graphène à bosses de contact métallique d'un substrat à utiliser dans un boîtier de dispositif à semi-conducteur

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10225431A1 (de) * 2002-06-07 2004-01-08 Siemens Dematic Ag Verfahren zur Anschlußkontaktierung von elektronischen Bauelementen auf einem isolierenden Substrat und nach dem Verfahren hergestelltes Bauelement-Modul
DE10225685A1 (de) * 2002-06-10 2003-12-24 Siemens Dematic Ag Verfahren zur Erzeugung von Löchern in einem elektrischen Schaltungssubstrat
CN114615789A (zh) * 2020-12-08 2022-06-10 富泰华工业（深圳）有限公司 主板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2558763B1 (fr) * 1984-01-27 1987-11-20 Thomson Csf Procede de fabrication d'un substrat ceramique, avec plots de connexion electriques transversaux
US4814295A (en) * 1986-11-26 1989-03-21 Northern Telecom Limited Mounting of semiconductor chips on a plastic substrate
DE69002372T2 (de) * 1989-04-26 1993-12-09 Canon Kk Stanzwalze zum Giessen von Lagen für optische Datenträger, Verfahren zu deren Herstellung und Verfahren zur Herstellung des damit herzustellenden Trägers.
JP3193198B2 (ja) * 1993-07-30 2001-07-30 京セラ株式会社 半導体素子の実装方法
EP0782765B1 (fr) * 1994-09-23 2000-06-28 Siemens N.V. Emballage de matrice a projections en polymeres
DE19732353A1 (de) * 1996-09-27 1999-02-04 Fraunhofer Ges Forschung Verfahren zur Herstellung kontaktloser Chipkarten und kontaktlose Chipkarte
US5831832A (en) * 1997-08-11 1998-11-03 Motorola, Inc. Molded plastic ball grid array package
US6005198A (en) * 1997-10-07 1999-12-21 Dimensional Circuits Corporation Wiring board constructions and methods of making same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2747132A1 (fr) * 2012-12-18 2014-06-25 Imec Procédé permettant de transférer une feuille de graphène à bosses de contact métallique d'un substrat à utiliser dans un boîtier de dispositif à semi-conducteur
US8974617B2 (en) 2012-12-18 2015-03-10 Imec Method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package

Also Published As

Publication number Publication date
WO2002011202A3 (fr) 2003-01-23
WO2002011201A2 (fr) 2002-02-07
TW531817B (en) 2003-05-11
WO2002011201A3 (fr) 2002-09-19
DE10037292A1 (de) 2002-02-21

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