WO2002011201A3 - Procede et dispositif de production de substrats de connexion de composants electroniques - Google Patents
Procede et dispositif de production de substrats de connexion de composants electroniques Download PDFInfo
- Publication number
- WO2002011201A3 WO2002011201A3 PCT/DE2001/002891 DE0102891W WO0211201A3 WO 2002011201 A3 WO2002011201 A3 WO 2002011201A3 DE 0102891 W DE0102891 W DE 0102891W WO 0211201 A3 WO0211201 A3 WO 0211201A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electronic components
- embossing
- connection substrates
- producing connection
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
- B29C43/32—Component parts, details or accessories; Auxiliary operations
- B29C43/44—Compression means for making articles of indefinite length
- B29C43/46—Rollers
- B29C2043/461—Rollers the rollers having specific surface features
- B29C2043/463—Rollers the rollers having specific surface features corrugated, patterned or embossed surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0143—Using a roller; Specific shape thereof; Providing locally adhesive portions thereon
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0014—Shaping of the substrate, e.g. by moulding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Combinations Of Printed Boards (AREA)
- Structure Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Shaping Of Tube Ends By Bending Or Straightening (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Pour produire des substrats de connexion de mico-plaquettes semiconductrices, de préférence de substrats PSGA (Polymer Stud Grid Array), on chauffe un corps brut (1), de préférence un film et on produit sur au moins une de ses surfaces des bosses (3) et/ou des creux à l'aide d'un outillage de frappe ou d'un rouleau de gaufrage. On utilise comme matériau du corps substrat des thermoplastiques résistants à des températures élevées, de préférence des polymères à cristaux liquides (LCP). De préférence, leur surface peut être pourvue d'une couche métallique qui, à son tour, est dotée de trous en tant qu'auxiliaires de gaufrage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10037292.9 | 2000-07-31 | ||
| DE10037292A DE10037292A1 (de) | 2000-07-31 | 2000-07-31 | Verfahren zur Herstellung von Anschlußsubstraten für Halbleiterkomponenten |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2002011201A2 WO2002011201A2 (fr) | 2002-02-07 |
| WO2002011201A3 true WO2002011201A3 (fr) | 2002-09-19 |
Family
ID=7650849
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE2001/002892 Ceased WO2002011202A2 (fr) | 2000-07-31 | 2001-07-31 | Procede et dispositif de production de substrats de connexion de composants electroniques |
| PCT/DE2001/002891 Ceased WO2002011201A2 (fr) | 2000-07-31 | 2001-07-31 | Procede et dispositif de production de substrats de connexion de composants electroniques |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE2001/002892 Ceased WO2002011202A2 (fr) | 2000-07-31 | 2001-07-31 | Procede et dispositif de production de substrats de connexion de composants electroniques |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE10037292A1 (fr) |
| TW (1) | TW531817B (fr) |
| WO (2) | WO2002011202A2 (fr) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10225431A1 (de) * | 2002-06-07 | 2004-01-08 | Siemens Dematic Ag | Verfahren zur Anschlußkontaktierung von elektronischen Bauelementen auf einem isolierenden Substrat und nach dem Verfahren hergestelltes Bauelement-Modul |
| DE10225685A1 (de) * | 2002-06-10 | 2003-12-24 | Siemens Dematic Ag | Verfahren zur Erzeugung von Löchern in einem elektrischen Schaltungssubstrat |
| EP2747132B1 (fr) | 2012-12-18 | 2018-11-21 | IMEC vzw | Procédé permettant de transférer une feuille de graphène à bosses de contact métallique d'un substrat à utiliser dans un boîtier de dispositif à semi-conducteur |
| CN114615789A (zh) * | 2020-12-08 | 2022-06-10 | 富泰华工业(深圳)有限公司 | 主板 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2558763A1 (fr) * | 1984-01-27 | 1985-08-02 | Thomson Csf | Procede de fabrication d'un substrat ceramique, avec plots de connexion electriques transversaux |
| US4814295A (en) * | 1986-11-26 | 1989-03-21 | Northern Telecom Limited | Mounting of semiconductor chips on a plastic substrate |
| US5310333A (en) * | 1989-04-26 | 1994-05-10 | Canon Kabushiki Kaisha | Roll stamper for molding substrate used for optical recording medium |
| US5831832A (en) * | 1997-08-11 | 1998-11-03 | Motorola, Inc. | Molded plastic ball grid array package |
| US6005198A (en) * | 1997-10-07 | 1999-12-21 | Dimensional Circuits Corporation | Wiring board constructions and methods of making same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3193198B2 (ja) * | 1993-07-30 | 2001-07-30 | 京セラ株式会社 | 半導体素子の実装方法 |
| EP0971405A3 (fr) * | 1994-09-23 | 2000-05-10 | Siemens S.A. | Procédé pour la fabrication d'un substrat por un "stud grid array" en polymère |
| DE19732353A1 (de) * | 1996-09-27 | 1999-02-04 | Fraunhofer Ges Forschung | Verfahren zur Herstellung kontaktloser Chipkarten und kontaktlose Chipkarte |
-
2000
- 2000-07-31 DE DE10037292A patent/DE10037292A1/de not_active Withdrawn
-
2001
- 2001-07-27 TW TW090118392A patent/TW531817B/zh active
- 2001-07-31 WO PCT/DE2001/002892 patent/WO2002011202A2/fr not_active Ceased
- 2001-07-31 WO PCT/DE2001/002891 patent/WO2002011201A2/fr not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2558763A1 (fr) * | 1984-01-27 | 1985-08-02 | Thomson Csf | Procede de fabrication d'un substrat ceramique, avec plots de connexion electriques transversaux |
| US4814295A (en) * | 1986-11-26 | 1989-03-21 | Northern Telecom Limited | Mounting of semiconductor chips on a plastic substrate |
| US5310333A (en) * | 1989-04-26 | 1994-05-10 | Canon Kabushiki Kaisha | Roll stamper for molding substrate used for optical recording medium |
| US5831832A (en) * | 1997-08-11 | 1998-11-03 | Motorola, Inc. | Molded plastic ball grid array package |
| US6005198A (en) * | 1997-10-07 | 1999-12-21 | Dimensional Circuits Corporation | Wiring board constructions and methods of making same |
Non-Patent Citations (4)
| Title |
|---|
| "METHOD TO CONTROL THE GEOMETRY AND VERTICAL PROFILE OF VIA HOLES IN SUBSTRATE MATERIALS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 35, no. 5, 1 October 1992 (1992-10-01), pages 211 - 216, XP000312938, ISSN: 0018-8689 * |
| "USE OF HIGH PRECISION SILICON MOLDS FOR REPLICATING MICROELECTRONIC PACKAGING STRUCTURES", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 30, no. 5, October 1987 (1987-10-01), pages 306 - 311, XP002156789, ISSN: 0018-8689 * |
| BECKER H ET AL: "Hot embossing as a method for the fabrication of polymer high aspect ratio structures", SENSORS AND ACTUATORS A, ELSEVIER SEQUOIA S.A., LAUSANNE, CH, vol. 83, no. 1-3, May 2000 (2000-05-01), pages 130 - 135, XP004198304, ISSN: 0924-4247 * |
| DREUTH H ET AL: "Thermoplastic structuring of thin polymer films", SENSORS AND ACTUATORS A, ELSEVIER SEQUOIA S.A., LAUSANNE, CH, vol. 78, no. 2-3, 14 December 1999 (1999-12-14), pages 198 - 204, XP004252972, ISSN: 0924-4247 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002011202A3 (fr) | 2003-01-23 |
| TW531817B (en) | 2003-05-11 |
| DE10037292A1 (de) | 2002-02-21 |
| WO2002011201A2 (fr) | 2002-02-07 |
| WO2002011202A2 (fr) | 2002-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2478499A1 (fr) | Elements destines a des applications de gaufrage et d'adhesion | |
| WO2003092041A3 (fr) | Procede pour fabriquer un substrat presentant une couche utile sur un support a haute resistivite | |
| WO2003095175A3 (fr) | Procede et appareil de gaufrage | |
| CA2326244A1 (fr) | Element de connexion electrique et methode de production connexe | |
| TW200638567A (en) | Electronic device including a guest material within a layer and a process for forming the same | |
| MXPA04006620A (es) | Mejoras en metodos de fabricacion de sustratos. | |
| ATE447194T1 (de) | Folie und optisches sicherungselement | |
| EP1504877A3 (fr) | Procédé et dispositif pour le gaufrage de la surface d'un film | |
| WO2002084631A1 (fr) | Procede de transfert d'element, procede de disposition d'element mettant en oeuvre ce procede et procede de production d'un appareil d'affichage d'image | |
| CA2302198A1 (fr) | Films polymeres orientes et gaufres | |
| WO1999053319A3 (fr) | Matrices miniaturisees haute densite et leurs procedes de fabrication | |
| WO2005108108A3 (fr) | Element de securite et son procede de production | |
| EP1352922A3 (fr) | Objet moulé à conductivité thermique et procédé pour sa fabrication | |
| EP0989606A3 (fr) | Substrat pour un module de puissance et procédé pour sa fabrication, et dispositif sémiconducteur comprenant le substrat | |
| EP1280101A4 (fr) | Procede de production de boitier cof | |
| WO2002045183A3 (fr) | Substrat dote d'une couche semi-conductrice, composant electronique, circuit electronique, composition pouvant etre imprimee et procedes de fabrication associes | |
| AU8088198A (en) | Process of making absorbent structures and absorbent structures produced thereby | |
| AU4951399A (en) | Mechanical patterning of a device layer | |
| WO2003037589A1 (fr) | Pastille de materiau d'obturation, son procede de fabrication et dispositif a composants electroniques | |
| WO2001099149A3 (fr) | Procede de formation de structures barriere sur un substrat et article produit selon ledit procede | |
| WO2002011201A3 (fr) | Procede et dispositif de production de substrats de connexion de composants electroniques | |
| WO2008129738A1 (fr) | Procédé de formation de motif et procédé pour fabriquer un élément électronique | |
| WO2002066251A3 (fr) | Plaques d"impression | |
| EP1336874A3 (fr) | Procédé de préparation d'un film polymère anisotropique sur un substrat avec une surface structurée | |
| WO2006112815A3 (fr) | Impression par nanocontact |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A2 Designated state(s): CN JP KR SG US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
| AK | Designated states |
Kind code of ref document: A3 Designated state(s): CN JP KR SG US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
| 122 | Ep: pct application non-entry in european phase | ||
| NENP | Non-entry into the national phase |
Ref country code: JP |