[go: up one dir, main page]

WO2002008964A3 - Circuit integre - Google Patents

Circuit integre Download PDF

Info

Publication number
WO2002008964A3
WO2002008964A3 PCT/EP2001/008534 EP0108534W WO0208964A3 WO 2002008964 A3 WO2002008964 A3 WO 2002008964A3 EP 0108534 W EP0108534 W EP 0108534W WO 0208964 A3 WO0208964 A3 WO 0208964A3
Authority
WO
WIPO (PCT)
Prior art keywords
cells
integrated circuit
connections
cell
types
Prior art date
Application number
PCT/EP2001/008534
Other languages
German (de)
English (en)
Other versions
WO2002008964A2 (fr
Inventor
Martin Vorbach
Armin Nueckel
Volker Baumgarte
Gerd Ehlers
Original Assignee
Pact Informationstechnolgie Gm
Martin Vorbach
Armin Nueckel
Volker Baumgarte
Gerd Ehlers
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10036627A external-priority patent/DE10036627A1/de
Priority claimed from PCT/EP2001/006703 external-priority patent/WO2002013000A2/fr
Priority to AU2001289737A priority Critical patent/AU2001289737A1/en
Priority to EP01969493A priority patent/EP1377919A2/fr
Application filed by Pact Informationstechnolgie Gm, Martin Vorbach, Armin Nueckel, Volker Baumgarte, Gerd Ehlers filed Critical Pact Informationstechnolgie Gm
Publication of WO2002008964A2 publication Critical patent/WO2002008964A2/fr
Priority to EP02724198.3A priority patent/EP1386220B1/fr
Priority to PCT/EP2002/002398 priority patent/WO2002071248A2/fr
Priority to JP2002570104A priority patent/JP2004536373A/ja
Priority to AU2002257615A priority patent/AU2002257615A1/en
Priority to JP2002570052A priority patent/JP4011488B2/ja
Priority to PCT/EP2002/002403 priority patent/WO2002071249A2/fr
Priority to EP02712937A priority patent/EP1454258A2/fr
Priority to US10/469,910 priority patent/US20070299993A1/en
Priority to PCT/EP2002/002402 priority patent/WO2002071196A2/fr
Priority to JP2002570103A priority patent/JP2004535613A/ja
Priority to US10/471,061 priority patent/US7581076B2/en
Priority to EP02727358A priority patent/EP1540507B1/fr
Priority to AU2002254921A priority patent/AU2002254921A1/en
Priority claimed from DE10129237A external-priority patent/DE10129237A1/de
Publication of WO2002008964A3 publication Critical patent/WO2002008964A3/fr
Priority to JP2008249106A priority patent/JP2009054170A/ja
Priority to JP2008249115A priority patent/JP2009043275A/ja
Priority to JP2008249112A priority patent/JP2009020909A/ja
Priority to JP2008249099A priority patent/JP2009032281A/ja
Priority to JP2008249116A priority patent/JP2009043276A/ja
Priority to US12/496,012 priority patent/US20090300262A1/en
Priority to US12/944,068 priority patent/US9037807B2/en
Priority to US13/043,102 priority patent/US20110173389A1/en
Priority to US13/653,639 priority patent/US9075605B2/en
Priority to US14/219,945 priority patent/US9552047B2/en
Priority to US14/231,358 priority patent/US9436631B2/en
Priority to US14/318,211 priority patent/US9250908B2/en
Priority to US14/500,618 priority patent/US9141390B2/en
Priority to US15/225,638 priority patent/US10152320B2/en
Priority to US15/408,358 priority patent/US10331194B2/en
Priority to US16/190,931 priority patent/US20190102173A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit intégré comprenant plusieurs cellules voisines, de deux types au moins, qui présentent des connexions. Selon l'invention, les cellules présentent une taille suffisante pour l'intégration d'une multitude d'éléments logiques : au moins un élément logique est programmable sur au moins quelques-unes des cellules et les connexions sont situées à des positions au moins pratiquement concordantes de la cellule pour permettre un mélange des types de cellules pour l'agencement voisin des cellules.
PCT/EP2001/008534 2000-07-24 2001-07-24 Circuit integre WO2002008964A2 (fr)

Priority Applications (31)

Application Number Priority Date Filing Date Title
AU2001289737A AU2001289737A1 (en) 2000-07-24 2001-07-24 Integrated circuit
EP01969493A EP1377919A2 (fr) 2000-07-24 2001-07-24 Circuit integre
US10/471,061 US7581076B2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
AU2002254921A AU2002254921A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
EP02727358A EP1540507B1 (fr) 2001-03-05 2002-03-05 Dispositif pour traiter des données avec un réseau d'élements reconfigurables
JP2002570052A JP4011488B2 (ja) 2001-03-05 2002-03-05 データ加工および／またはデータ処理方法および装置
US10/469,910 US20070299993A1 (en) 2001-03-05 2002-03-05 Method and Device for Treating and Processing Data
JP2002570104A JP2004536373A (ja) 2001-03-05 2002-03-05 データ処理方法およびデータ処理装置
AU2002257615A AU2002257615A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
EP02724198.3A EP1386220B1 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour la mise en forme et/ou le traitement de donnees
PCT/EP2002/002403 WO2002071249A2 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour mettre en forme et/ou traiter des donnees
EP02712937A EP1454258A2 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour mettre en forme et/ou traiter des donnees
PCT/EP2002/002398 WO2002071248A2 (fr) 2001-03-05 2002-03-05 Procedes et dispositifs pour mettre en forme et/ou traiter des donnees
PCT/EP2002/002402 WO2002071196A2 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour la mise en forme et/ou le traitement de donnees
JP2002570103A JP2004535613A (ja) 2001-03-05 2002-03-05 データ処理方法およびデータ処理装置
JP2008249112A JP2009020909A (ja) 2001-03-05 2008-09-26 グラフのパーティショニング方法
JP2008249099A JP2009032281A (ja) 2001-03-05 2008-09-26 データ伝送方法
JP2008249106A JP2009054170A (ja) 2001-03-05 2008-09-26 データ流の管理方法
JP2008249116A JP2009043276A (ja) 2001-03-05 2008-09-26 Ｆｉｆｏ記憶方法
JP2008249115A JP2009043275A (ja) 2001-03-05 2008-09-26 シーケンスの形成方法
US12/496,012 US20090300262A1 (en) 2001-03-05 2009-07-01 Methods and devices for treating and/or processing data
US12/944,068 US9037807B2 (en) 2001-03-05 2010-11-11 Processor arrangement on a chip including data processing, memory, and interface elements
US13/043,102 US20110173389A1 (en) 2001-03-05 2011-03-08 Methods and devices for treating and/or processing data
US13/653,639 US9075605B2 (en) 2001-03-05 2012-10-17 Methods and devices for treating and processing data
US14/219,945 US9552047B2 (en) 2001-03-05 2014-03-19 Multiprocessor having runtime adjustable clock and clock dependent power supply
US14/231,358 US9436631B2 (en) 2001-03-05 2014-03-31 Chip including memory element storing higher level memory data on a page by page basis
US14/318,211 US9250908B2 (en) 2001-03-05 2014-06-27 Multi-processor bus and cache interconnection system
US14/500,618 US9141390B2 (en) 2001-03-05 2014-09-29 Method of processing data with an array of data processors according to application ID
US15/225,638 US10152320B2 (en) 2001-03-05 2016-08-01 Method of transferring data between external devices and an array processor
US15/408,358 US10331194B2 (en) 2001-03-05 2017-01-17 Methods and devices for treating and processing data
US16/190,931 US20190102173A1 (en) 2001-03-05 2018-11-14 Methods and systems for transferring data between a processing device and external devices

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
DE10036221 2000-07-24
DE10036221.4 2000-07-24
DE10036627.9 2000-07-27
DE10036627A DE10036627A1 (de) 2000-07-24 2000-07-27 Integrierter Schaltkreis
EPPCT/EP00/10516 2000-10-09
EPPCT/EP00/10516 2000-10-09
EP01102674.7 2001-02-07
EP01102674 2001-02-07
DE10110530 2001-03-05
DE10111014.6 2001-03-07
DE10111014 2001-03-07
EPPCT/EP01/06703 2001-06-13
DE10110530.4 2001-06-13
PCT/EP2001/006703 WO2002013000A2 (fr) 2000-06-13 2001-06-13 Protocoles et communication d'unites de configuration de pipeline
DE10129237.6 2001-06-20
DE10129237A DE10129237A1 (de) 2000-10-09 2002-06-20 Verfahren zur Bearbeitung von Daten

Publications (2)

Publication Number Publication Date
WO2002008964A2 WO2002008964A2 (fr) 2002-01-31
WO2002008964A3 true WO2002008964A3 (fr) 2003-10-23

Family

ID=56290174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/008534 WO2002008964A2 (fr) 2000-07-24 2001-07-24 Circuit integre

Country Status (3)

Country Link
EP (1) EP1377919A2 (fr)
AU (1) AU2001289737A1 (fr)
WO (1) WO2002008964A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
FR2838208B1 (fr) * 2002-04-03 2005-03-11 Centre Nat Rech Scient Architecture de calcul logique comprenant plusieurs modes de configuration

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (fr) * 1992-12-11 1994-06-23 National Technology, Inc. Dispositif de calcul a circuit integre comprenant des circuits prediffuses configurables dynamiquement a microprocesseur et un systeme d'execution d'instructions reconfigurable
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
EP0858168A1 (fr) * 1997-01-29 1998-08-12 Hewlett-Packard Company Matrice de processeur à réseau de portes programmables
WO1999040522A2 (fr) * 1998-02-05 1999-08-12 Sheng, George, S. Processeur de signal numerique utilisant des ensembles de macrocellules reconfigurables

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0688659A3 (fr) * 1994-06-23 1997-10-08 Illig Maschinenbau Adolf Outil de poinçonnage et de formage pour la fabrication de récipients en matière thermoplastique
US5636368A (en) * 1994-12-23 1997-06-03 Xilinx, Inc. Method for programming complex PLD having more than one function block type
GB9611994D0 (en) * 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (fr) * 1992-12-11 1994-06-23 National Technology, Inc. Dispositif de calcul a circuit integre comprenant des circuits prediffuses configurables dynamiquement a microprocesseur et un systeme d'execution d'instructions reconfigurable
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
EP0858168A1 (fr) * 1997-01-29 1998-08-12 Hewlett-Packard Company Matrice de processeur à réseau de portes programmables
WO1999040522A2 (fr) * 1998-02-05 1999-08-12 Sheng, George, S. Processeur de signal numerique utilisant des ensembles de macrocellules reconfigurables

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1377919A2 *

Also Published As

Publication number Publication date
EP1377919A2 (fr) 2004-01-07
AU2001289737A1 (en) 2002-02-05
WO2002008964A2 (fr) 2002-01-31

Similar Documents

Publication Publication Date Title
EP1137089B8 (fr) Séparateur de gaz pour pile à combustible, méthode de fabrication et pile à combustible
AU2001292539A1 (en) Fuel cell assembly and method for making the same
EP0867945A3 (fr) Architecture d'une cellule de circuit prédiffusé à haute densité
DE69929756D1 (de) Brennstoffzellenstapel
WO2001093075A3 (fr) Procede et systeme de programmation modulaire pour dispositifs logiques programmables
WO2003017427A3 (fr) Memoire remanente empilee verticalement programmable par l'utilisateur et son procede de fabrication
EP0663665A3 (fr) Cellule de mémoire avec technologie antifusible programmable.
DK1332524T3 (da) Fastoxidbrændselscellekomponent og fremgangsmåde til fremstilling af en fastoxidbrændselscellekomponent
HK1043878A1 (zh) 燃料电池和薄膜
AU2002216900A1 (en) Fuel cell stack
AU2001245337A1 (en) Electrical cells, components and methods
DE59912807D1 (de) Brennstoffzellen-modul
GB2342223B (en) Fuel cell and separator for fuel cell
GB2320825B (en) Repair fuse circuit performing complete latch operation using flash memory cell
DE59900872D1 (de) Speicherzellenanordnung und entsprechendes Herstellungsverfahren
EP1501141A4 (fr) Separateur destine a une pile a combustible
AU2003211785A1 (en) Solid oxide type fuel cell and separator
WO2004023582A3 (fr) Cellules et systemes electrochimiques
AU2001277718A1 (en) Method for manufacturing solar cell and solar cell
AU2001292317A1 (en) Fuel cell
GB0304372D0 (en) Separator for fuel cell, process for producing the same, and material therefor
WO2006071570A3 (fr) Configuration de memoire remanente pour circuits programmables a base de memoire non remanente dans un fpga
AU2002360007A1 (en) Fuel cell
WO2002010785A3 (fr) Procede et systeme de conception et d'essai hierarchiques, produit programme faisant appel a ce procede et circuit integre ainsi produit
AU2001284481A1 (en) Separator for low-temperature type fuel cell and production method therefor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2001969493

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 2001969493

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP