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AU2002254921A1 - Methods and devices for treating and processing data - Google Patents

Methods and devices for treating and processing data

Info

Publication number
AU2002254921A1
AU2002254921A1 AU2002254921A AU2002254921A AU2002254921A1 AU 2002254921 A1 AU2002254921 A1 AU 2002254921A1 AU 2002254921 A AU2002254921 A AU 2002254921A AU 2002254921 A AU2002254921 A AU 2002254921A AU 2002254921 A1 AU2002254921 A1 AU 2002254921A1
Authority
AU
Australia
Prior art keywords
treating
methods
devices
processing data
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002254921A
Inventor
Volker Baumgarte
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pact Informationstechnologie GmbH
Original Assignee
Pact Informationstechnologie GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/EP2001/006703 external-priority patent/WO2002013000A2/en
Priority claimed from PCT/EP2001/008534 external-priority patent/WO2002008964A2/en
Priority claimed from US09/967,847 external-priority patent/US7210129B2/en
Priority claimed from PCT/EP2001/011593 external-priority patent/WO2002029600A2/en
Application filed by Pact Informationstechnologie GmbH filed Critical Pact Informationstechnologie GmbH
Priority claimed from DE10129237A external-priority patent/DE10129237A1/en
Publication of AU2002254921A1 publication Critical patent/AU2002254921A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Read Only Memory (AREA)
  • Multi Processors (AREA)
  • Power Sources (AREA)
AU2002254921A 2001-03-05 2002-03-05 Methods and devices for treating and processing data Abandoned AU2002254921A1 (en)

Applications Claiming Priority (73)

Application Number Priority Date Filing Date Title
DE10110530 2001-03-05
DE10110530.4 2001-03-05
DE10111014.6 2001-03-07
DE10111014 2001-03-07
PCT/EP2001/006703 WO2002013000A2 (en) 2000-06-13 2001-06-13 Pipeline configuration unit protocols and communication
EPPCT/EP01/06703 2001-06-13
EP01115021 2001-06-20
DE10129237.6 2001-06-20
EP01115021.6 2001-06-20
DE10135210.7 2001-07-24
DE10135211 2001-07-24
DE10135210 2001-07-24
DE10135211.5 2001-07-24
AU2001289737 2001-07-24
PCT/EP2001/008534 WO2002008964A2 (en) 2000-07-24 2001-07-24 Integrated circuit
DE10139170.6 2001-08-16
DE10139170 2001-08-16
DE10142231.8 2001-08-29
DE10142231 2001-08-29
DE10142904 2001-09-03
DE10142904.5 2001-09-03
DE10142903 2001-09-03
DE10142894 2001-09-03
DE10142894.4 2001-09-03
DE10142903.7 2001-09-03
US31787601P 2001-09-07 2001-09-07
US60/317,876 2001-09-07
DE10144733 2001-09-11
DE10144732.9 2001-09-11
DE10144732 2001-09-11
DE10144733.7 2001-09-11
DE10145792.8 2001-09-17
DE10145795.2 2001-09-17
DE10145792 2001-09-17
DE10145795 2001-09-17
DE10146132 2001-09-19
DE10146132.1 2001-09-19
US09/967,847 US7210129B2 (en) 2001-08-16 2001-09-28 Method for translating programs for reconfigurable architectures
US09/967,847 2001-09-28
AU16952/02 2001-09-30
EP0111299 2001-09-30
AU2002220600 2001-10-08
PCT/EP2001/011593 WO2002029600A2 (en) 2000-10-06 2001-10-08 Cell system with segmented intermediate cell structure
DE10154259 2001-11-05
DE10154260.7 2001-11-05
DE10154259.3 2001-11-05
DE10154260 2001-11-05
EP01129923.7 2001-12-14
EP01129923 2001-12-14
EP02001331.4 2002-01-18
EP02001331 2002-01-18
DE10202044 2002-01-19
DE10202044.2 2002-01-19
DE10202175 2002-01-20
DE10202175.9 2002-01-20
DE10206653 2002-02-15
DE10206653.1 2002-02-15
DE10206856 2002-02-18
DE10206857 2002-02-18
DE10206856.9 2002-02-18
DE10206857.7 2002-02-18
DE10207225.6 2002-02-21
DE10207224 2002-02-21
DE10207224.8 2002-02-21
DE10207226 2002-02-21
DE10207225 2002-02-21
DE10207226.4 2002-02-21
DE10208435 2002-02-27
DE10208434.3 2002-02-27
DE10208434 2002-02-27
DE10208435.1 2002-02-27
PCT/EP2002/002402 WO2002071196A2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
DE10129237A DE10129237A1 (en) 2000-10-09 2002-06-20 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit

Publications (1)

Publication Number Publication Date
AU2002254921A1 true AU2002254921A1 (en) 2002-09-19

Family

ID=56290255

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2002254921A Abandoned AU2002254921A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
AU2002257615A Abandoned AU2002257615A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU2002257615A Abandoned AU2002257615A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data

Country Status (4)

Country Link
EP (2) EP1540507B1 (en)
JP (3) JP2004536373A (en)
AU (2) AU2002254921A1 (en)
WO (2) WO2002071248A2 (en)

Families Citing this family (32)

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Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
DE50115584D1 (en) 2000-06-13 2010-09-16 Krass Maren PIPELINE CT PROTOCOLS AND COMMUNICATION
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
DE10357284A1 (en) * 2003-12-05 2005-07-14 Pact Xpp Technologies Ag Data processor comprises multidimensional array of coarse grained logic elements operating at clock rate greater than that of bus and/or communication line connecting logic elements mutually and with other elements
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
AU2002338729A1 (en) 2001-09-19 2003-04-01 Pact Xpp Technologies Ag Router
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
EP1514193B1 (en) 2002-02-18 2008-07-23 PACT XPP Technologies AG Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
WO2004038599A1 (en) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP4700611B2 (en) * 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト Data processing apparatus and data processing method
US20060126770A1 (en) * 2004-12-15 2006-06-15 Takeshi Yamazaki Methods and apparatus for providing an asynchronous boundary between internal busses in a multi-processor device
JP4909588B2 (en) * 2005-12-28 2012-04-04 日本電気株式会社 Information processing apparatus and method of using reconfigurable device
US7693257B2 (en) 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
FR2922663B1 (en) * 2007-10-23 2010-03-05 Commissariat Energie Atomique STRUCTURE AND METHOD FOR SAVING AND RETRIEVING DATA
WO2010142432A2 (en) 2009-06-09 2010-12-16 Martin Vorbach System and method for a cache in a multi-core processor
CN102281054A (en) * 2011-04-25 2011-12-14 浙江大学 Reconfigurable computing array data coupler for data driving
JP2016178229A (en) 2015-03-20 2016-10-06 株式会社東芝 Reconfigurable circuit

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06101043B2 (en) * 1988-06-30 1994-12-12 三菱電機株式会社 Microcomputer
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh Method for operating a data processing device
IT1260848B (en) * 1993-06-11 1996-04-23 Finmeccanica Spa MULTIPROCESSOR SYSTEM
EP0721157A1 (en) * 1994-12-12 1996-07-10 Advanced Micro Devices, Inc. Microprocessor with selectable clock frequency
US5892370A (en) * 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.)
DE19704044A1 (en) 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
EP1228440B1 (en) 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequence partitioning in cell structures
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit

Also Published As

Publication number Publication date
WO2002071196A3 (en) 2003-12-04
JP2004535613A (en) 2004-11-25
JP2004538675A (en) 2004-12-24
WO2002071196A2 (en) 2002-09-12
EP1540507A2 (en) 2005-06-15
WO2002071248A3 (en) 2005-04-21
WO2002071196A8 (en) 2003-10-30
WO2002071248A2 (en) 2002-09-12
EP1540507B1 (en) 2012-05-23
JP4011488B2 (en) 2007-11-21
WO2002071248A8 (en) 2004-01-29
JP2004536373A (en) 2004-12-02
EP1454258A2 (en) 2004-09-08
AU2002257615A1 (en) 2002-09-19

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase