WO2002003423A2

WO2002003423A2 - Capacitor and capacitor contact process for stack capacitor drams

Info

Publication number: WO2002003423A2
Application number: PCT/US2001/021164
Authority: WO
Inventors: Thomas W. Dyer; Gerhard Kunkel; Louis L. Hsu; Heon Lee; David Kotecki; Young Limb; Carl J. Radens; Young Jin Park
Original assignee: International Business Machines Corp; Infineon Technologies North America Corp
Current assignee: International Business Machines Corp; Infineon Technologies North America Corp
Priority date: 2000-06-30
Filing date: 2001-07-02
Publication date: 2002-01-10
Anticipated expiration: 2002-12-30
Also published as: WO2002003423A8; WO2002003423A3

Abstract

A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Description

MERGED CAPACITOR AND CAPACITOR CONTACT PROCESS FOR CONCAVE

SHAPED STACK CAPACITOR DRAMS

TECHNICAL FIELDTECHNICAL FIELD

The present invention relates generally to concave shaped stacked capacitors in a DRAM cell and, more specifically, to stacked capacitors that are co-planar with bit lines and merge directly with electrical contacts in a DRAM cell.

BACKGROUND OF THE INVENTIONBACKGROUND OF THE INVENTION

Advancement in the state-of-the-art of the semiconductor industry requires increasing the memory density and performance of the semiconductor devices. These goals are often achieved by scaling dynamic random access memory (DRAM) devices to smaller dimensions and operating voltages. The miniaturized devices built in and on a semiconductor substrate are very closely spaced and their packing density has increased significantly.

Individual DRAM storage cells, usually consisting of a single metal-oxide- semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. Metallization in contact with the semiconductor substrate is called contact metallization. In MOS devices, polysilicon film has been the form of metallization used for gate and interconnection of MOS devices. The inability to further miniaturize the contact metallization (i.e., first level interconnections) is a major obstacle in the miniaturization of DRAMs.

As DRAM density has increased (1 MEG and beyond) thin film capacitors, such as stacked capacitors, trenched capacitors, or combinations thereof, have evolved in attempts to meet minimum space requirements. Many of these designs have become elaborate and difficult to fabricate consistently as well as efficiently.

There is a challenge to develop methods of manufacturing capacitors and interconnects that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and to provide maximum process overlay tolerance to maximize product yields. Typically, in DRAM fabrication, two mask/etch steps are performed to form the conductor connection to the bit line and the node contact. Furthermore, contact holes through the thick insulation layers create high aspect ratios (greater than 3) which make the contact etch processes difficult and the resulting etch defects reduce device yields.

There is a need, therefore, for a DRAM cell and fabrication method that reduces the number of critical photolithography steps and reduces the aspect ratio of bit line and capacitor conductive contacts.

SUMMARY OF THE TNVENTIONSUMMARY OF THE INVENTION

To meet these and other needs, and in view of its purposes, the present invention provides a semiconductor memory device comprising a semiconductor substrate which comprises at least one transistor. The transistor comprises a source, a drain and a gate. The device further comprises a first insulating layer which has an upper surface over the array of transistors. At least one electrical contact extends from one of the source and the drain to the upper surface of the first insulating layer. A bit line layer comprises a first and a second approximately parallel bit lines over the first insulating layer, spaced to define an area between said first and second bit lines, and at least one stacked capacitor in the area between the first and second bit lines. The stacked capacitor extends through the bit line layer to the electrical contact.

According to the present invention there is also provided a method for fabricating a semiconductor memory device on a semiconductor substrate, comprising the steps of:

a) providing a semiconductor substrate comprising at least one transistor, said transistor comprising a source, a drain, and a gate.

b) depositing a first insulating layer having an upper surface over said transistor,

c) forming at least one electrical contact extending from one of said source and said drain through said first insulating layer to the upper surface of the first insulating layer,

d) forming a bit line layer comprising a first and a second approximately parallel bit lines over said first insulating layer, the bit lines spaced to define an area between said first and second bit lines, and

e) forming at least one stacked capacitor in said area between said first and second bit lines, the stacked capacitor extending through the bit line layer to said electrical contact.

BRIEF DESCRIPTION OF THE DRAWINGBRIEF DESCRIPTION OF THE DRAWING

The invention is best understood from the following detailed description when read in connection with the accompanying drawing. Included in the drawing are the following figures:

Figure 1 shows an electrical equivalent of a DRAM cell.

Figure 2 shows a top view of a device according to the present invention illustrating the relative position of the active area in which are formed the transistors, the location of the capacitors and the bit and word lines comprising a memory device.

Figure 3 shows a top view of a device according to an alternate embodiment of the present invention illustrating the relative position of the active area in which are formed the transistors, the location of the capacitors and the bit and word lines comprising a memory device.

Figure 4 shows a schematic elevation of a memory storage device according to the present invention showing the substrate comprising the transistor forming the storage device during the process of producing a complete device .

Figure 5 shows the structure of figure 4 after the structure has been completed

Figure 6 shows an alternate embodiment of a DRAM structure in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTIONDETAILED DESCRIPTION OF THE

INVENTION

The fabrication process used to create a high density DRAM cell structure with stacked capacitors formed co-planar to bit lines, and merged electrical contacts will now be presented in detail. The DRAM device described in this invention is comprised of N channel transfer gate transistors. If desired, this invention can be used to create a DRAM cell, comprised of P channel transfer gate transistors. This can be accomplished by creating an N well region, in the P type semiconductor substrate, and creating P type source and drain regions, in the semiconductor substrate, between polycide gate structures.

Figure 1 is a electrical circuit representing the essential elements of a DRAM cell. These are a switching transistor, typically a MOS FET having a drain D, a source S, and a gate G. Associated with the transistor are a storage capacitor C, a word line WL and a bit line BL. A plurality of such structures are arrayed along a pattern on a substrate- interconnected and accessible from outside the substrate through an array of bit and word lines.

Figure 2 is a top view of a substrate 10 comprising an array of such DRAM cells constructed in accordance with this invention, which will be used to illustrate this invention. A plurality of parallel bit lines 36, BL1, BL2, BL3 are shown arrayed in regular intervals spaced from each other. A second array of word lines 16, WL1 through WL4 extending perpendicular to the bit line 36 array, is shown beneath the bit line layer. The word line layer is spaced and insulated from the bit line layer so that there are no electrical contacts between the word lines and the bit lines where they cross over. In the space between the bit lines and word lines are shown a plurality of storage capacitors 42.

In its simplest form, a switching transistor for each DRAM cell is formed in an active area 45 in the substrate 10 roughly bounded by the dark dotted lines. Within the active area are the drain, gate and source of the transistor. Connectors 32 extend from the bit lines 36 to the source of the transistor. The capacitors 42 are connected to the drain of the transistor as will be explained below.

Figure 3 is an alternate embodiment of the invention, wherein two capacitors may be connected alternatively to a same bit line, as is more common in high density DRAM cell structures. In such case the active area 43 shown by the heavy lines extends to a second capacitor. A second transistor having a common source structure is used to connect this second capacitor to the bit line, as will be shown in more detail below.

Referring next to figure 4 there is shown a schematic elevation of a single DRAM cell on a substrate constructed in accordance with the present invention prior to the formation of the storage capacitor. On a substrate 10, which is typically a semiconductor substrate there is formed in accordance with well known techniques a switching transistor having a source area 20, a drain area 12 and a gate structure 15. The gate structure includes a gate electrode 14 connected to word line 16. Silicon nitride sidewall spacers 17 are typically also included as part of the gate structure. A thermal oxide layer 11 and a doped polysilicate layer 13 may also be included as part of the substrate. The transistor is covered by a first insulating layer 22 deposited thereover to a thickness of between 3,000 A and 10,000 A, filling the regions between the gate structures. The first insulating layer 22 may comprise an insulating material such as boron phospho- silicate glass (BPSG). The first insulating layer 22 is planarized by chemical mechanical polishing (CMP) to form a first upper surface 27.

Still referring to FIG. 4, electrical contacts 28 are next formed through photolithographic and anisotropic RIE procedures. A RIE etchant, such as C₂F₈-CF₄-CHF₃, is used to selectively remove BPSG layer 22 and the oxide layer 11 to form electrical contact vias. The vias are approximately 0.1 μm by 0.1 μm in area and spaced about 0.2 μm apart. N-type doped polysilicon is then deposited to fill the contact vias to form electrical contacts 28. The doped polysilicon is planarized by CMP down to the first upper surface 27. These electrical contacts 28 will ultimately connect directly to the storage capacitor electrode. In this structure the storage capacitor is a stacked capacitor structure and the contact connects to its bottom electrode. Alternatively, the contact 28 may connect to a bit line contact 32. The DRAM cell of the present invention thus provides electrical connection from the capacitor to the substrate in a single photolithographic and RIE etch step in the formation of the electrical contacts 28.

Once the electrical contacts have been formed, the first upper surface 27 is capped with a second insulating layer 30, to a thickness of 200 A to 3000 A. The second insulating layer provides a second upper surface 31. The second insulating layer may comprise any insulating material, such as tetraethoxysilane (TEOS) and BPSG. Ion implantation is then performed to heavily dope the source 20 and drain 12 regions.

A bit line contact 32 is formed in the second insulating layer 30. A bit line contact via is formed through photolithographic and anisotropic reactive ion etch. The via etch extends from the second upper surface 31 through the second insulating layer 30 to the first upper surface 27. The via connects to one of the electrical contacts 28 that extends to a source region 20 in the substrate. The bit line contact via is approximately 0.1 μm by 0.1 μm in area and connect to the electrical contacts between the active word lines 16.

In a subsequent photolithographic and anisotropic etch step, a support via 34 is formed outside the array area. The support via 34 ultimately connects a bit line to the sense amplifying region of the DRAM cell. The support via 34 that extends from the second upper surface 31 through the second insulating layer 30, and continues down through the first insulating layer 22. While both the bit line contact 32 and support vias 34 are etched from the second upper surface 31, the vias are etched in separate etching steps as the support via 34 must be etch significantly deeper than the bit line contact via 32.

Still referring to FIG. 4, a conductive material is deposited in the etched bit line contact via 32 and the support via 34. The conductive material fills the vias, and forms a conductive layer 36. The conductive layer 36 may be 1,000 A to 3,000 A thick and may be deposited via a CVD, LPCVD or other deposition process known in the art. The conductive material may be tungsten (W), platinum (Pt), palladium (Pd), lead (Pb), iridium (Ir), gold (Au), rhodium (Rh), ruthenium (Ru), molybdenum (Mo), silver (Ag), copper (Cu), aluminum (Al), or alloys and mixtures thereof. The conductive material is preferably tungsten.

Still referring to FIG. 4, a nitride layer 38 is deposited over the conductive layer 36 to a thickness of 100 A to 1,000 A via CVD, LPCVD or any deposition process known in the art. The nitride layer 38 and the conductive layer are etched through photolithographic and anisotropic RIE to form bit lines. The etched bit lines are approximately parallel and are approximately 0.1 μm wide. The arrangement of the bit lines defines a space between each bit line. The space between each bit line is approximately 0.1 μm. Nitride sidewall spacers (41 shown in figure 2) are formed on the sides of the bit lines through conventional methods.

After the bit lines 36 and the bit line sidewalls are formed, a third insulating layer 40 is deposited as a conformal layer between and above the bit lines. The third insulating layer may be BPSG, TEOS, spin on glass (SOG) or organic polymer. The third insulating layer 40 is planarized using chemical mechanical polishing (CMP) and capacitor cavities are formed in the insulating material between the bit lines through conventional photolithographic and anisotropic RIE processes.

Figure 5 shows in schematic elevation the DRAM structure with the storage capacitor in place according to the present invention. As mentioned earlier, the capacitor is a stacked capacitor. The capacitor cavities may be formed such that their openings are co- planar with the top surface of the bit lines 36. Alternatively, the capacitor cavities maybe formed such that their openings are co-planar with a layer deposited over the bit line layer 40, as shown in figure 5. The capacitor openings are positioned in the area between the bit lines. The spacing between the bit lines determines the area of the insulating material available to form the capacitor cavities. The capacitor cavities 42 are formed such that they extend from the upper surface of the device through the bit line layer and the second insulating layer 30, down to the electrical contacts 28 at the first upper surface 27. The capacitor cavities 42 are substantially aligned with the electrical contacts 28. The dimensions of the capacitor cavity are determined in part by the space between the bit lines. The capacitor cavities are formed such that insulating material is etched leaving the bit lines and the nitride sidewalls intact.

•

The capacitor cavity dimensions may be between 0.02 μm and 0.05 μm in area and 0.1 μm to 1.0 μm in depth Preferably, the capacitor cavity dimensions will be approximately 0.3 μm² in area and 0.2 μm in depth.

A diffusion barrier layer 44 is deposited over the third insulating layer 40 and into the capacitor cavities. The barrier layer is preferably 200 A thick and comprises conductors, such as TiN, TaN, TaSiN, WN, A1N, TiAIN, GaN, AlGaN, RuO₂, IrO₂, and Re₂O₃. A layer of conductive electrode material 46 is conformally deposited over the diffusion barrier layer. The conductive electrode material comprises any noble metal, including Pt, Pd, Ir, Au, Rh, Ru, Mo, alloys and combinations thereof. The conductive material may also comprise metals such as Ag, Cu, Al and alloys and combinations thereof. The conductive layer may consist entirely of the diffusion barrier layer. The layer of conductive electrode material may be about 100 A to 500 A thick, and preferably is about 300 A. The conductive electrode material 46 is coated with photo-resist, and patterned through photolithography. The conductive electrode material 46 and the diffusion barrier layer 44 are etched back to the third insulating layer 40 outside of the capacitor cavities. The photo-resist is removed from the capacitor cavity regions and the remaining conductive electrode material 46 and barrier layer material are etched back to coincide with the surface of the third insulating layer 40. The bottom electrode 46 and barrier layer 44 of the stacked capacitor are recessed inside the "U" shape of the stacked capacitor due to the etching back of the conductive electrode material and diffusion barrier material.

A layer of capacitor dielectric 48 is conformally deposited over the third insulating layer 40 and into the capacitor cavity, covering the bottom electrode 46. The equivalent oxide thickness of the capacitor dielectric layer is between 20 A and 200 A thick and preferably comprises materials with high dielectric constants, such as (Ba, Sr (TiO₃)), BaTiO₃, SrTiO₃, PbZrTiO₃, PbZrO₃, PbLaTiO₃, SrBiTaO₃.

Next, another layer of conductive electrode material 50 is deposited over the capacitor dielectric 48, filling the remaining space in the capacitor cavity. The top electrode 50 is planarized to define the stacked capacitor structure.

The DRAM cell is completed with additional conventional fabrication steps needed to form connections to the sense amplifying region of the cell. These steps are not shown in the drawings.

As mentioned earlier, it is often desirable to provide two storage capacitors alternatively connected to a bit line through two transistors. Figure 6 shows in schematic elevation a DRAM cell structure that provides this feature.

As shown in figure 6, there is a plurality of switching transistors each having a source 20 and a drain 12. However in this structure two adjacent transistors SWl, SW2 share a common source 20', and it is this common source 20' that is connected through electrical contact 28 to bit line 36. This arrangement permits access to either of the two storage capacitors Cl and C2 through activation of SWl or SW2.

The device top view shown in figure 3 may be used to illustrate the organization of bit lines 36, word lines 16, capacitors, 42 and bit line contacts 32. A bit line contact 32 serves to connect the bit line to the source region. Each source region 20 is associated with at least one active word line. The bit line contact allows the signal from the bit line to activate and read the respective storage capacitor. Any regions of the device not formed over isolation regions in the substrate are referred to as an active area of the device. A representative active area 43, comprises two capacitors (Cl and C2), two active word lines (WL2 and WL3), a bit line (BL2) and a bit line contact 32. In the active area 43, charge stored in Cl is gated to BL2 through WL2 and connected by a bit line contact 32. The same bit line contact connects BL2 to the WL3 gate to read the charge stored in C2.

Although illustrated and described above with reference to specific embodiments, the invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention.

Claims

What is claimed is:

1. A semiconductor memory device comprising:

i) a substrate comprising at least one transistor, said transistor comprising a source, a drain and a gate,

ii) a first insulating layer over said transistor said first insulating layer having an upper surface ,

iii) at least one electrical contact extending from one of said source and said drain to the upper surface of the first insulating layer,

iv) a bit line layer comprising a first and a second approximately parallel bit lines over said first insulating layer spaced to define an area between said first and second bit lines,

v) at least one stacked capacitor in said area between said first and second bit lines, the stacked capacitor extending through the bit line layer to said electrical contact.

2. The semiconductor memory device according to claim 1 further comprising a second insulating layer between the bit line layer and the first insulating layer and a bit line plug extending through said second insulating layer to one of said electrical contacts.

3. The semiconductor memory device according to claim 2 wherein the second insulating layer comprises boron-phosphorus silicate glass, tetraethosiloxane, or any combination thereof.

4. The semiconductor memory device according to claim 1 wherein each of said bit lines comprise a sidewall and a silicon nitride spacer on said sidewall.

5. The semiconductor memory device according to claim 1 further comprising a third insulating layer over the bit line layer, and wherein the stacked capacitor extends through the third insulating layer and the bit line layer.

6. The semiconductor memory device according to claim 5 wherein the third insulating layer comprises boron-phosphorus silicate glass.

7.The semiconductor memory device according to claim 1 wherein the source and drain are formed in the substrate.

8. The semiconductor memory device according to claim 1 wherein the first insulating layer comprises boron-phosphorus silicate glass.

9. The semiconductor memory device according to claim 1 wherein the contact comprises doped polysilicon.

10. The semiconductor memory device according to claim 1 wherein the first and second bit lines comprise tungsten.

11. A method for fabricating a semiconductor memory device on a semiconductor substrate, comprising the steps of:

d) forming a bit line layer comprising a first and a second approximately parallel bit lines over said first insulating layer spaced to define an area between said first and second bit lines,

12. A method for fabricating a semiconductor memory device according to claim 11

a) providing at least one transistor on said semiconductor substrate, said transistor comprising a source, a drain, and a gate. b) forming sidewall spacers and caps to encompass said transistor,

c) depositing a first insulating layer over the transistor,

d) forming at least one contact extending from at least one of said source and said drain to the upper surface of the first insulating layer,

e) planarizing said first insulating layer and caps, forming a first upper surface,

f) providing at least one electrical contact in the first insulating layer using photolithography and etching to form a contact via, said contact via extending from the substrate to the first upper surface, and depositing a doped polysilicon layer, filling said contact via with doped polysilicon and planarizing the doped polysilicon layer to the first upper surface;

g) depositing a second insulating layer over the first upper surface, forming a second upper surface;

h) forming at least one bit line contact and a support contact using photolithography and etching to form a bit line contact via, said bit line contact via extending from the contact to the second upper surface, and to form a support via, said support via extending from the substrate to the second upper surface, and depositing a first metal layer, filling said bit line contact and support vias with a metal material;

i) forming at least one bit line by depositing a first nitride layer on the first metal layer, using photolithography, and etching the nitride layer and the first metal layer to define the bit line, and forming a nitride sidewall spacer on at least one side of the bit line;

j) depositing a third insulating layer, to form a third upper surface,

k) forming a set of concave stacked capacitors using photolithography and etching a capacitor cavity, wherein the cavity extends from the third upper surface to the first upper surface, through the second and third insulating layers, and wherein the cavity is formed between the bit lines; depositing a diffusion barrier layer, depositing a first electrode layer and etching said barrier layer and first electrode layer to remove the barrier layer and the first electrode layer from the third upper surface, defining a node electrode; depositing a capacitor dielectric layer, and depositing a second electrode layer and etching the second electrode layer, defining a ground electrode.