JP2000260957A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] First electrode of information storage capacitive element and first electrode thereof
And a planar misalignment with the electrode connection hole is prevented. SOLUTION: A connection hole 43 for a lower electrode 45 of a capacitor C for information storage constituting a memory cell of a DRAM is formed in a self-aligned manner with respect to a hole for forming a lower electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device technology, and more particularly to a method of manufacturing a semiconductor device having a capacitor for storing information and a technology effective when applied to the semiconductor device technology. It is.

[0002]

2. Description of the Related Art The technology studied by the present inventors for a semiconductor device having a capacitor for storing information is as follows, for example. First, after forming an element for selecting a memory cell on a semiconductor substrate, a first interlayer insulating film is formed so as to cover the element. Subsequently, a connection hole for connecting to a memory cell selection element is formed in the interlayer insulating film, and a conductor film for leading an electrode is buried in the connection hole. Subsequently, a second interlayer insulating film, a first insulating film, a second insulating film, and a lower electrode for forming the above-mentioned capacitive element are formed on the first interlayer insulating film so as to cover the upper surface of the conductive film. A first conductor film is deposited in order from the lower layer. The first insulating film is made of a material having a high etching selectivity with respect to the second interlayer insulating film and the second insulating film. Thereafter, a photoresist pattern having an opening region such that the upper surface of the conductor film for leading out the electrode is planarly formed on the first conductor film for forming the lower electrode is formed, and then this is etched with an etching mask. And, using the first insulating film as an etching stopper, an opening is formed by etching away a part of the first conductor film and the second insulating film for forming the lower electrode. Next, after depositing a second conductor film for forming the lower electrode, this is etched back to form a sidewall conductor portion formed of the second conductor film for forming the lower electrode on the side surface of the opening. I do. Subsequently, the upper surface of the electrode drawing conductor film is exposed to the first insulating film and the first interlayer insulating film using the side wall conductor portion and the first conductor film for forming the lower electrode as an etching mask. Drill connection holes. afterwards,
A third conductor film for forming a lower electrode is deposited on the first conductor film and the side wall conductor film so as to be embedded in the connection hole, and thereafter, a bottom portion of the lower electrode in the capacitor is formed thereon. Is patterned.
Next, after patterning the first and third conductive films for forming the lower electrode using the third insulating film as a mask, a fourth conductive film for forming the lower electrode is deposited so as to cover the third insulating film. I do. Subsequently, after the fourth conductive film is etched back so that the fourth conductive film remains only on the side surfaces of the third insulating film, the third insulating film and the second insulating film are removed. A cylindrical lower electrode is formed.

[0003]

However, the present inventors have found that the semiconductor device technology studied by the present inventors has the following problems.

First, it is necessary to secure a planar alignment margin between the lower electrode and the connection hole, but it is difficult to secure a sufficient margin from a layout due to miniaturization. .

Second, as the miniaturization progresses, when the lower electrode and the connection hole are misaligned in a plane and an aperture is formed, the connection hole is formed when patterning the conductor film for forming the lower electrode. The conductive film for forming the lower electrode embedded therein is also removed by etching. As a result, the contact area between the bottom of the lower electrode and the conductor film in the connection hole decreases, and as a result, the contact resistance between the lower electrode and the element increases. In addition, various problems occur, such as formation of unnecessary micro holes (micro trenches) in the conductor film in the connection holes.

Third, regarding the first and second problems,
Attempting to solve the problem within the range of the existing technology without thinking would complicate the process and make it difficult to ensure the reliability of the semiconductor device.

Further, based on the results of the present invention, the present inventors have investigated known examples from the viewpoint of a semiconductor device having a capacitor for storing information. According to the survey results, for example,
No. 240389 (first known example) discloses that a groove is formed in an interlayer insulating film, a first conductor film for forming a lower electrode is formed on a side surface of the groove, and then a first conductor film for forming the lower electrode is formed. A technique is disclosed in which a connection hole is formed in an interlayer insulating film using a conductor film as an etching mask, and a second conductor film for forming a lower electrode is formed inside the connection hole and on a side surface of the first conductor film. I have. However, information on the plane of the lower electrode is not disclosed. In addition, the bottom area of the lower electrode is larger than the plane area of the groove that is first formed by photolithography. Further, a first electrode for forming a lower electrode is formed.
There is a risk that the conductive film of the above will collapse when the connection hole is formed.

[0008] For example, in Japanese Patent Application Laid-Open No. Hei 9-116114 (second known example), after forming a groove in an interlayer insulating film and forming a first insulating film on the upper surface of the interlayer insulating film and the side surface of the groove, A connection hole is formed in the interlayer insulation film using the first insulation film as an etching mask, and a first conductor film for forming a lower electrode is buried in the connection hole and on the first insulation film, and is processed. To form a lower electrode in the groove,
Further, there is disclosed a technique in which, after the first insulating film is removed by a wet etching process, a capacitive insulating film and a conductive film for an upper electrode are sequentially deposited on the surface of the first conductive film in the groove. However, the configuration is different from the present invention.

[0009] For example, in Japanese Patent Application Laid-Open No. 7-14932 (third known example), similarly to the first known example, a first conductive film for forming a lower electrode formed on a side surface of a groove is etched with an etching mask. A technique is disclosed in which a connection hole is formed in an interlayer insulating film, and a second conductor film for forming a lower electrode is formed inside the connection hole and on the upper surface of the first conductor film.
However, also in the case of this technique, similar to the first known example,
First, the bottom area of the lower electrode is larger than the plane area of the groove formed by photolithography. In addition, the first conductive film for forming the lower electrode may collapse when the connection hole is formed.

In addition, for example, Japanese Patent Application Laid-Open No. 8-274273 (fourth known example) discloses that a first conductive film for forming a lower electrode formed on a side surface of the above-mentioned groove is used as an etching mask to form a connection hole in an interlayer insulating film. And the like are disclosed.
However, also in the case of this technique, similar to the first known example,
First, the bottom area of the lower electrode is larger than the plane area of the groove formed by photolithography. Further, it is difficult to align the connection hole with the bottom of the lower electrode.

Further, for example, Japanese Patent Application Laid-Open No. Hei 8-88329 (fifth known example) discloses that an interlayer insulating film is formed of two layers having different etching rates, and then wet etching and C etching are performed.
A contact hole and a lower electrode are formed by an MP (Chemical Mechanical Polishing) method or the like. However, this technique is difficult to cope with miniaturization. Further, the configuration is different from that of the present invention, for example, the planar shape of the lower electrode is circular.

An object of the present invention is to provide a technique capable of preventing a planar misalignment between a first electrode of an information storage capacitor and a connection hole for the first electrode. .

It is another object of the present invention to provide a technique capable of improving the reliability of connection between a first electrode of an information storage capacitor and a connection hole for the first electrode. is there.

A further object of the present invention is to improve the reliability of connection between the first electrode of the information storage capacitor and the connection hole for the first electrode without complicating the process. It is to provide the technology that can do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a memory cell in which an information storage capacitor and a memory cell selecting field effect transistor are connected in series. (A) forming the memory cell selecting field effect transistor on a semiconductor substrate; and (b) forming a first insulating film on the semiconductor substrate so as to cover the memory cell selecting field effect transistor. And (c) forming a connection hole in the first insulating film at a position where the semiconductor region of the memory cell selection field effect transistor is formed, and then, in the connection hole, forming the memory cell selection field effect transistor. Forming a first conductive film electrically connected to the semiconductor region of
(D) a step of sequentially forming a second insulating film and a sacrificial film on the semiconductor substrate after the step (c); and (e) forming a first electrode of the information storage capacitor on the sacrificial film. Forming a first opening for exposing the second insulating film in the sacrificial film using the first resist film for determining a plane pattern as an etching mask; (f)
By removing the second insulating film exposed from the first opening, the second opening where the first conductor film is exposed in the second insulating film is changed to the first opening. (G) forming a second conductor film electrically connected to the first conductor film in the first opening and the second opening. Thereby, the first of the information storage capacitance elements formed by the second conductor film
And (h) removing the sacrifice film to project a part of the first electrode.

(2) In the method of manufacturing a semiconductor device according to the present invention, in the above (1), after the step (h), a step of forming a capacitive insulating film so as to cover a protruding surface of the first electrode. When,
Forming a second electrode of the information storage capacitive element so as to cover the capacitive insulating film.

(3) In the method of manufacturing a semiconductor device according to the present invention, in the above (2), the second conductor film may be a single film of platinum, ruthenium, ruthenium oxide, iridium or iridium oxide or a single film of these single films. The first conductive film and the second conductive film
Forming a barrier conductive film for suppressing diffusion of oxygen between the conductive film and the conductive film.

(4) The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a memory cell in which an information storage capacitor and a memory cell selecting field effect transistor are connected in series. (A) forming the memory cell selecting field effect transistor on a semiconductor substrate; and (b) forming a first insulating film on the semiconductor substrate so as to cover the memory cell selecting field effect transistor. And (c) forming a connection hole in the first insulating film at a position where the semiconductor region of the memory cell selection field effect transistor is formed, and then forming the connection hole in the connection hole. Forming a first conductive film electrically connected to the semiconductor region of
(D) a step of sequentially forming a second insulating film and a third insulating film on the semiconductor substrate after the step (c); and (e) forming the information storage capacitor on the third insulating film. After forming a first resist film for determining the plane pattern of the first electrode, the first opening for exposing the second insulating film is formed in the third insulating film by using the first resist film as an etching mask. Forming, and (f) removing the second insulating film exposed from the first opening, the second opening exposing the first conductive film in the second insulating film. Forming a portion in a self-aligned manner with respect to the first opening;
(G) forming a second conductor film electrically connected to the first conductor film in the first opening and the second opening to form the second conductor film; Forming a first electrode of the information storage capacitor element.

(5) The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a memory cell in which an information storage capacitor and a memory cell selecting field effect transistor are connected in series. (A) forming the memory cell selecting field effect transistor on a semiconductor substrate; and (b) forming a first insulating film on the semiconductor substrate so as to cover the memory cell selecting field effect transistor. (C) sequentially forming a second insulating film and a third insulating film on the first insulating film; and (d) forming the information storage capacitor on the third insulating film. After forming a first resist film for determining the plane pattern of the first electrode, the first opening for exposing the second insulating film is formed in the third insulating film by using the first resist film as an etching mask. Forming and before (e) By removing the second insulating film and the first insulating film exposed from the first opening, a pair of the memory cell selecting field effect transistors is formed in the second insulating film and the first insulating film. Forming a second opening exposing one of the semiconductor regions in a self-aligned manner with respect to the first opening; and (f) forming a second opening in the first opening and the second opening. By forming a second conductive film electrically connected to one of the pair of semiconductor regions of the memory cell selecting field effect transistor, the information storage capacitor element formed by the second conductive film is formed. Forming a single electrode.

(6) The method of manufacturing a semiconductor device according to the present invention, wherein in the above (4) or (5), a second conductive film is buried in the first opening and the second opening. Forming a first electrode of the information storage capacitor; and forming a portion of the first electrode by removing the third insulating film after forming the first electrode; Forming a capacitive insulating film so as to cover the protruding surface of the first electrode; and forming a second electrode of the information storage capacitive element on the capacitive insulating film.

(7) In the method of manufacturing a semiconductor device according to the present invention, in the above (4) or (5), a second conductor film may be formed in the first opening and the second opening in a sectional shape. Forming a first electrode of the information storage capacitor element having a concave cross section by forming the first electrode of the first electrode having a concave cross section; and forming the first electrode having a concave cross section by removing the third insulating film. A step of projecting a portion, a step of forming a capacitive insulating film so as to cover a projecting surface of the first electrode having a concave cross section, and a step of forming a second electrode of the information storage capacitive element on the capacitive insulating film. Forming step.

(8) In the method of manufacturing a semiconductor device according to the present invention, in the above (4) or (5), a second conductor film is formed in the first opening and the second opening in a sectional shape. Forming a first electrode of the information storage capacitor element having a concave cross section by forming the capacitor into a concave shape, and forming a capacitance insulating film so as to cover an exposed surface of the first electrode having a concave cross section. And forming a second electrode of the information storage capacitive element on the capacitive insulating film.

(9) The method according to (4), (5), (6), (7) or (8), wherein the third insulating film is formed after forming the third insulating film. A step of forming a first mask film thereon, a step of forming the first opening in the third insulating film and the first mask film, and a step of forming a second opening on a side surface of the first opening. Forming a first mask film;
The second opening is formed in the second insulating film using the first mask film and the second mask film as an etching mask.
Forming in a self-aligned manner with respect to the opening.

(10). The method of manufacturing a semiconductor device according to the present invention comprises:
In the above (9), after the second mask film is formed of a conductive material and the second opening is formed, the first opening and the second opening are formed while leaving the second mask film. Forming a first electrode of the information storage capacitor element formed by a second conductor film including the conductor film and a second mask film by forming a conductor film in the opening of the storage device. Things.

(11). The method of manufacturing a semiconductor device according to the present invention comprises:
(9) In the above (9), a step of removing the second mask film after forming the second opening, and a step of removing the first opening and the second opening after the step of removing the second mask film. Forming a second conductive film in the opening to form a first electrode of the information storage capacitor formed by the second conductive film.

(12). The method of manufacturing a semiconductor device according to the present invention comprises:
In the method for manufacturing a semiconductor device according to the above (4), (5), (6) or (7), the second insulating film and the third insulating film may be disposed between the second insulating film and the third insulating film. Forming a fourth insulating film having a relatively large etching selectivity with respect to the third insulating film; and forming the fourth insulating film after the first electrode forming step.
Removing the third insulating film using the insulating film as an etching stopper.

(13). The method of manufacturing a semiconductor device according to the present invention comprises:
In the above (1), (2) or (4), the second conductor film is a single film of platinum, ruthenium, ruthenium oxide, iridium or iridium oxide, or a laminate formed by stacking any two or more of these single films. It consists of a film.

(14). The method of manufacturing a semiconductor device according to the present invention comprises:
In the above (1), (2), (4) or (13), a step of forming a barrier conductor film for suppressing diffusion of oxygen between the first conductor film and the second conductor film is provided. Things.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

In this embodiment, a p-channel MISFET (Metal Insulator Semiconductor) is used.
Field Effect Transistor) is abbreviated as pMIS, and an n-channel MISFET is abbreviated as nMIS.

(Embodiment 1) In Embodiment 1, for example, a DRAM (Dynamic Random Access Memory)
Or ferroelectric memory (FeRAM; Ferro-electric R)
The case where the present invention is applied to AM) will be described with reference to FIGS.

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate (a substantially flat circular thin plate called a semiconductor wafer in a semiconductor device manufacturing process) 1 in the semiconductor device of the first embodiment. The semiconductor substrate 1 is made of, for example, p ^- type single crystal silicon. On the main surface of the semiconductor substrate 1 in the memory region M, a p-well 2a is formed. This p
Well 2 a is surrounded by semiconductor region 3 and is electrically separated from semiconductor substrate 1. Thus, it is possible to prevent noise from entering the memory area M from an input / output circuit or the like formed in another area of the semiconductor substrate 1. The p-well 2a is formed by introducing, for example, boron. The semiconductor region 3 is set to an n-type by introducing, for example, phosphorus or arsenic. A p-well 2b and an n-well 4 are formed on the main surface of the semiconductor substrate 1 in the peripheral circuit region P. p well 2b
, For example, boron is introduced. Further, for example, phosphorus or arsenic is introduced into the n-well 4.

In the isolation region of the semiconductor substrate 1, for example, a trench-type isolation portion (trench isolation) 5 is formed. The separation portion 5 is formed by burying a separation film such as silicon oxide in a separation groove 6 dug in the thickness direction of the semiconductor substrate 1. This separation groove 6
The silicon oxide film embedded in the substrate is flattened so that the main surface thereof is substantially the same as the main surface of the semiconductor substrate 1 in the active region. The separating portion 5 is not limited to the groove type, and can be variously changed. For example, the separating portion 5 can be formed by a field oxide film formed by a LOCOS (selective oxidation) method.

On the main surface of the semiconductor substrate 1, the separating portion 5
An active region is formed in a region surrounded by. The active region formed in the memory region M is formed, for example, in an elongated island-like pattern extending straight in the horizontal direction in FIG. Each active region has a memory cell selecting MISF.
Two ETQs are formed adjacent to each other in the horizontal direction in FIG. Each memory cell selecting MISFET Qs has a gate insulating film 7, a gate electrode 8A, and a pair of n-type semiconductor regions 9a and 9b forming a source and a drain.
MISFE for selecting two memory cells in one active region
TQs are arranged in a state where one of the semiconductor regions 9b is shared with each other.

The gate insulating film 7 is made of, for example, silicon oxide. After forming the gate insulating film 7, for example, NO (nitrogen oxide) or N
By performing a heat treatment in an atmosphere such as ₂ O (nitrous oxide), nitrogen can also be segregated at the interface between the gate insulating film and the semiconductor substrate 1 (oxynitriding treatment). When the thickness of the gate insulating film 7 is reduced to about 8 nm, the distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to the difference in thermal expansion coefficient becomes apparent.
Induces hot carriers. Since the nitrogen segregated at the interface with the semiconductor substrate 1 relaxes the distortion, the oxynitridation improves the reliability of the ultra-thin gate insulating film 7 and suppresses hot carriers. The reliability of the memory cell selecting MISFET Qs can be improved.

The gate electrode 8A is connected to the word line WL.
And extends linearly along the Y direction with the same width and the same space. Gate electrode 8A
The (word line WL) includes, for example, a low-resistance polycrystalline silicon film doped with an impurity such as phosphorus (P), a barrier metal layer formed of a tungsten nitride (WN) film or the like formed thereon, and a And a high melting point metal film such as a tungsten (W) film formed on the substrate. Gate electrode 8 of polymetal structure
Since A (word line WL) has a lower electric resistance than a gate electrode formed of a polycrystalline silicon film or a polycide film, the signal delay of the word line can be reduced. The gate electrode 8A may have, for example, a single-layer structure of low-resistance polycrystalline silicon, or may have a so-called polycide structure in which, for example, a silicide layer such as tungsten silicide is provided on the low-resistance polycrystalline silicon film. You can also. The source and drain semiconductor regions 9a and 9b are doped with, for example, phosphorus or arsenic to form n
Set to type.

In the peripheral circuit region P of the DRAM, nMISQn and pMISQp during the forming process are provided. NMISQn and pMISQ constituting peripheral circuits
p is formed by a looser design rule than the memory cell. The nMISQn is formed in the p well 2b. At this stage, the gate insulating film 7, the gate electrode 8
It has B and n ⁻ type semiconductor regions 10a. The pMISQp is formed in the n-well 4, and at this stage has the gate insulating film 7, the gate electrode 8C, and the p ⁻ type semiconductor region 11a. Gate insulating film 7 and gate electrode 8 of nMISQn and pMISQp
The structure of B, 8C is the same as that of the memory cell selecting MISF described above.
Since they are the same as the gate insulating film 7 and the gate electrode 8A (word line WL) of ETQs, the description is omitted. Further, the n ⁻ type semiconductor region 10a and the p ⁻ type semiconductor region 11a
Is a region for suppressing the hot electron effect. For example, phosphorus or arsenic is introduced into the n ⁻ type semiconductor region 10a, and boron is introduced into the p ⁻ type semiconductor region 11a, for example. Gate electrodes 8A, 8B, 8
A cap insulating film 12 is formed on C. The cap insulating film 12 is made of, for example, silicon nitride, and is patterned in the same step as the gate electrodes 8A, 8B, 8C.

First, on such a semiconductor substrate 1, FIG.
As shown in FIG. 5, after depositing the silicon nitride film 13 by the CVD method, the silicon nitride film 13 in the memory region M is covered with a photoresist film (not shown), and the silicon nitride film 13 of the peripheral circuit is anisotropically etched. Thereby, the sidewall spacers 13s are formed on the side walls of the gate electrodes 8B and 8C of the peripheral circuit. This etching is performed using a gas for etching the silicon nitride film 13 with a high selectivity in order to minimize the amount of shaving of the silicon oxide film and the gate insulating film 7 buried in the isolation trench 6.

Subsequently, for example, arsenic (As) is ion-implanted into the p-type well 2b of the peripheral circuit to form an n ⁺ -type semiconductor region 10b (source, drain) of nMISQn. Then, for example, boron (B) is ion-implanted to form ap ⁺ type semiconductor region 11 (source, drain) of pMISQp. Through the steps so far, pMISQp and nMISQn are substantially completed.

Thereafter, as shown in FIG.
SOG (Spin On Glass) film 16 is spin-coated on top,
After performing a bake treatment in an oxygen atmosphere containing steam at about 400 ° C., heat treatment is further performed at 800 ° C. for about 1 minute to densify (densify) the SOG film 16. S
The OG film 16 uses, for example, a polysilazane-based inorganic SOG. The SOG film 16 has a higher reflow property than a glass flow film such as a BPSG film, and is superior in gap fill property of a fine space. Therefore, the gate electrode 8A ( Voids do not occur even when embedded in the space of the word line WL). In addition, since the SOG film 16 can achieve high reflow properties without performing high-temperature and long-time heat treatment required for a BPSG film or the like, the memory cell selecting MISF
ETFETs for ETQs source / drain and peripheral circuits
(NMISQn, pMISQp) suppresses thermal diffusion of impurities implanted into the source and the drain, and can achieve a shallow junction. In addition, oxidation of the metal (tungsten film) forming the gate electrode 8A (word line WL) and the gate electrodes 8B and 8C during the heat treatment can be suppressed.
MISFET Qs for memory cell selection and M of peripheral circuit
High performance of the ISFET (nMISQn, pMISQp) can be realized.

Next, a silicon oxide film 17 is deposited on the SOG film 16, and the silicon oxide film 17 is polished by the CMP method to flatten the surface, and then a silicon oxide film 18 is deposited thereon. Silicon oxide films 17, 18
Is deposited by a plasma CVD method using oxygen (or ozone) and tetraethoxysilane (TEOS) as a source gas. In addition, the upper silicon oxide film 18 is deposited to repair fine scratches on the surface of the lower silicon oxide film 17 generated when the upper silicon oxide film 18 is polished by the CMP method.

Subsequently, after forming a photoresist film R 1 on the silicon oxide film 18, the n ^{− of the} MISFET Qs for memory cell selection is subjected to dry etching using this as a mask.
The silicon oxide films 18 and 17 above the mold semiconductor regions (source and drain) 9a and 9b are removed. This etching is performed on the silicon nitride film 13 under the silicon oxide film 17.
Is performed using a gas for etching the silicon oxide film 17 with a high selectivity in order to prevent the removal.

Thereafter, as shown in FIG. 4, the silicon nitride film 13 on the n ⁻ type semiconductor region (source, drain) 9a is removed by dry etching using the photoresist film R1 as a mask. By removing the lower thin gate insulating film 7, a contact hole 19 is formed in one upper portion of the n ⁻ type semiconductor region (source, drain) 9a, and a contact hole 20 is formed in the other upper portion. The etching of the silicon nitride film 13 is performed using a gas for etching the silicon nitride film 13 with a high selectivity in order to minimize the amount of the silicon oxide film shaved in the semiconductor substrate 1 and the isolation trench 6. Further, this etching is performed under such a condition that the silicon nitride film 13 is anisotropically etched so that the silicon nitride film 13 is left on the side wall of the gate electrode 8A (word line WL). Thereby, fine contact holes 19 and 20 whose diameter in the horizontal direction in FIG. 4 is equal to or less than the resolution limit of photolithography can be formed in a self-aligned manner with respect to the gate electrode 8A (word line WL). FIG. 5 is a plan view of the memory region M after this step.
Shown in FIG. 6 is a sectional view taken along line BB of FIG.
Contact hole 19 (MIS for selecting two memory cells)
N ⁻ type semiconductor region 9b shared by FETs Qs
The upper contact hole has a vertical diameter of FIG.
Is formed in an elongated pattern that is about twice as large as the diameter in the left-right direction. L in FIG. 5 indicates the active area of the memory area M. The cross section of the memory area M in FIGS. 1 to 4 corresponds to the line AA in FIG.

After the contact holes 19 and 20 are formed, for example, phosphorus is ion-implanted into the p-well 2 through the contact holes 19 and 20 so that the p-well in a region deeper than the source and drain of the memory cell selecting MISFET Qs is formed. An n-type semiconductor region may be formed in the well 2. Since the n-type semiconductor region has an effect of alleviating an electric field concentrated at the ends of the source and the drain, the leak current at the ends of the source and the drain can be reduced and the refresh characteristics of the memory cell can be improved. .

Next, as shown in FIG. 7, a conductor film 21 made of, for example, low-resistance polycrystalline silicon doped with arsenic (As) is deposited on the silicon oxide film 18 and buried in the contact holes 19 and 20. . Subsequently, the conductor film 21 is polished by a CMP (Chemical Mechanical Polishing) method or the like so as to be left only in the contact holes 19 and 20, so that the plug (FIG. 8) formed of the conductor film 21 is formed. (A first conductive film). Thereafter, the silicon nitride film 2 is formed on the silicon oxide film 18.
2 and a silicon oxide film 23 are sequentially deposited from the lower layer by a CVD method or the like.
Is heat treated. The silicon oxide film 23 is deposited by, for example, a plasma CVD method using oxygen (or ozone) and tetraethoxysilane as a source gas. By the heat treatment, impurities in the polycrystalline silicon film forming the conductor film 21 are removed from the bottoms of the contact holes 19 and 20 from the n ⁻ -type semiconductor region 9 of the memory cell selecting MISFET Qs.
A low-resistance n-type semiconductor region (source, drain) 9 is formed by diffusing into a and 9b.

Next, as shown in FIG. 9, through holes 24 are formed by removing the silicon nitride film 22 and the silicon oxide film 23 above the contact holes 19 by dry etching using the photoresist film R2 as a mask. . The through hole 24 is arranged above the separation part 5 deviating from the active region L. Subsequently, after removing the photoresist film R2, as shown in FIG. 10, the silicon oxide films 23, 22, 18, 17, the SOG film 16 of the peripheral circuit, the SOG film 16 and the gate insulating film are dry-etched using the photoresist film R3 as a mask. By removing the film 7, n
Contact holes 25 and 26 are formed above the n ⁺ type semiconductor region 10b (source, drain) of MISQn,
Contact holes 27 and 28 are formed above the p ⁺ type semiconductor region 11b (source and drain) of pMISQp. At the same time, the gate electrode 8 of pMISQp
A contact hole 29 is formed in the upper part of C, and nMISQ
A contact hole (not shown) is formed above n gate electrode 8B. As described above, the etching for forming the through holes 24 and the etching for forming the contact holes 25 to 29 are performed in separate steps, so that when forming the deep contact holes 25 to 29 in the peripheral circuit, the shallow portion of the memory region M is formed. The problem that the conductive film 21 exposed at the bottom of the through hole 24 is deeply cut can be prevented. The formation of the through holes 24 and the formation of the contact holes 25 to 29 may be performed in the reverse order.

Then, as shown in FIG. 11, a titanium (Ti) film 30 is deposited on the silicon oxide film 23 including the insides of the contact holes 25 to 29 and the through holes 24. The titanium film 30 is deposited by using a highly directional sputtering method such as collimation sputtering or ionization sputtering so that the titanium film 30 is deposited with a certain thickness on the bottoms of the contact holes 25 to 29 having a large aspect ratio.

Subsequently, a heat treatment is performed in an atmosphere of an inert gas such as argon (Ar) without exposing the titanium film 30 to the atmosphere. By this heat treatment, contact holes 25 to 2 are formed.
9 react with the titanium film 30 at the bottom of
The surface of the n ⁺ type semiconductor region 10b (source, drain) of MISQn and the p ⁺ type semiconductor region 11 of pMISQp
A titanium silicide (TiSi ₂ ) layer 31 is formed on the surface of b (source, drain). At this time,
The titanium silicide layer 31 is also formed on the surface of the conductor film 21 at the bottom of the through hole 24 by the reaction between the polycrystalline silicon film constituting the conductor film 21 and the titanium film 30. By forming the titanium silicide layer 31 as described above at the bottom of the contact holes 25 to 29, a plug formed inside the contact holes 25 to 29 in the next step;
Since the contact resistance of the portion where the source and drain (the n ⁺ type semiconductor region 10b and the p ⁺ type semiconductor region 11b) of the MISFET of the peripheral circuit are in contact can be reduced, the peripheral circuit such as a sense amplifier or a word driver can be used. High speed operation is promoted. The contact holes 25 to 29
Is formed of a refractory metal silicide other than titanium silicide, for example, cobalt silicide (CoS).
i ₂ ), tantalum silicide (TaSi ₂ ), molybdenum silicide (MoSi ₂ ), or the like.

Next, a titanium nitride (TiN) film 32 is deposited on the titanium film 30 by the CVD method. The CVD method is
Since the step coverage is better than the sputtering method, the contact holes 25 to 29 having a large aspect ratio
A titanium nitride film 32 having a thickness similar to that of the flat portion can be deposited on the bottom of the substrate. Subsequently, a tungsten film 33 is deposited on the titanium nitride film 32 by a CVD method using tungsten hexafluoride (WF ₆ ), hydrogen and monosilane (SiH ₄ ) as a source gas, and the contact holes 25 to 2 are formed.
9 and the inside of the through hole 24 are covered with a tungsten film 33.
Embed completely with. Subsequently, by removing (polishing back) the tungsten film 33, the titanium nitride film 32, and the titanium film 30 on the silicon oxide film 23 by using the CMP method, as shown in FIG. A plug 34 composed of the tungsten film 33, the titanium nitride film 32, and the titanium film 30 is formed inside the through hole 24. The plug 3
4 is a tungsten film 3 on the silicon oxide film 23
3. It may be formed by removing (etching back) the titanium nitride film 32 and the titanium film 30 by dry etching. Further, the plug 34 may be constituted mainly of the titanium nitride film 32 without using the tungsten film 33. That is, the plug 34 may be formed by burying the titanium nitride film 32 having a large thickness in the contact holes 25 to 29 and the through hole 24. In this case, the plug 34 is compared with the case where the tungsten film 33 is mainly used.
The resistance of the silicon oxide film 2 is slightly increased in the next step.
Since the titanium nitride film 30 serves as an etching stopper when the bit line BL and the first-layer wiring of the peripheral circuit are formed by dry-etching the tungsten film 33 deposited on the upper part of Wiring and contact holes 25
29, the misalignment margin is significantly improved.
The degree of freedom in the layout of the wiring in the layer is greatly improved.

Next, as shown in FIG. 13, after a tungsten film is deposited on the silicon oxide film 23 by a sputtering method, the photoresist film (not shown) formed on the tungsten film is used as a mask. By dry etching, a bit line BL is formed in the memory area M, and a first-layer wiring 35 is formed in the peripheral circuit. Since the tungsten film has high light reflectance, the photoresist film may cause halation at the time of exposure, and the dimensional accuracy of the pattern (width and space) may be reduced. To prevent this, a thin anti-reflection film may be deposited on the tungsten film, and then a photoresist film may be applied. As the antireflection film, an organic material or a metal material having a low light reflectance (for example, a titanium nitride film) is used. Subsequently, a silicon oxide film 36 is deposited so as to cover the bit line BL and the first-layer wiring 35,
After depositing a silicon oxide film (second insulating film) 37 thereon, the surface of the silicon oxide film 37 is flattened by the CMP method. The silicon oxide films 36 and 37 are deposited by a plasma CVD method using, for example, oxygen (or ozone) and tetraethoxysilane as a source gas. Thereafter, as shown in FIG. 14, a silicon nitride film (a fourth insulating film) 38, a silicon oxide film (a third insulating film) 39, and a polycrystalline silicon film (a first mask film) are formed on the silicon oxide film 37. ) 4
Thereafter, a photoresist film R4 is formed in such a manner that a region for forming a capacitor, which is a capacitor for storing information of a DRAM, is opened.

Then, as shown in FIG. 15, the polycrystalline silicon film 40 and the silicon oxide film 39 are dry-etched using the photoresist film R4 as a mask, thereby forming a lower electrode of a capacitor which is a capacitor for storing information of a DRAM. A forming hole (first opening) 41 is formed.
At this time, the etching rate of the silicon oxide film 39 is higher than that of the silicon nitride film 38 by performing the etching process under the condition that the silicon oxide is more easily etched and removed than the silicon nitride. The silicon film 38 functions as an etching stopper. Thereafter, as shown in FIGS. 16 and 17, the silicon nitride film 38 is removed by etching using the photoresist film R4 as a mask, thereby forming holes 41 for forming a lower electrode.
The silicon oxide film 37 is exposed from the bottom surface of the substrate. On this occasion,
The etching process is performed under the condition that silicon nitride is more easily removed by etching than silicon oxide. Such 2
By performing the selective etching process in stages, the uniformity of the depth of the hole 41 for forming the lower electrode can be favorably controlled. However, as a method of forming the hole 41 for forming the lower electrode, for example, the following method may be used. That is, after an opening pattern is formed in the polycrystalline silicon film 40 using the photoresist film R4 as a mask, the photoresist film R4 is removed, and the remaining polycrystalline silicon film 40 is used as a hard mask to form the silicon oxide film 39 and the silicon nitride film. 38 may be sequentially removed under the above selective etching conditions. As a result, it is possible to reduce the adhesion rate of foreign substances due to the photoresist film R4 and to improve the reliability of the semiconductor device. FIG. 17 shows a hole 4 for forming a lower electrode.
FIG. 6 is a cross-sectional view taken along line CC of FIG. 5 after forming No. 1. The plane area of the hole 41 for forming the lower electrode is formed in, for example, a rectangular shape (actually, an elliptical shape). It is formed so as to be longer than the dimension in the direction.

Next, as shown in FIG. 18, a low-resistance polycrystalline silicon film 42 is deposited on the polycrystalline silicon film 40 on the inner side surface and the bottom surface of the hole 41 for forming a lower electrode by a CVD method or the like. 19 and 20 by etching back by the anisotropic dry etching method.
As shown in (1), a sidewall spacer (second mask film) 42s formed of a low-resistance polycrystalline silicon film is formed on the inner side surface of the hole 41 for forming a lower electrode. This allows
The planar dimension of the lower electrode forming hole 41 can be reduced by twice the thickness of the low-resistance polycrystalline silicon film 42. That is, the planar dimension of the hole 41 for forming the lower electrode can be made smaller than the dimension that can be transferred by photolithography. FIG. 20 is a sectional view taken along line CC of FIG. 5 after the formation of the sidewall spacer 42s.

Subsequently, as shown in FIGS. 21 and 22, using the polycrystalline silicon film 40 and the sidewall spacers 42s as a mask, the silicon oxide films 37, 36,
23 is removed by the same selective etching process as described above, thereby forming a connection hole (second opening) 43 for the lower electrode.
Are formed in a self-aligned manner with respect to the hole 41 for forming the lower electrode. At this time, the silicon nitride film 22 is used as an etching stopper. FIG. 22 is a cross-sectional view taken along line CC of FIG. 5 after forming the connection hole 43 for the lower electrode.

Thereafter, as shown in FIGS. 23 and 24, the silicon nitride film 22 is removed by the same selective etching treatment as described above, so that the conductive film 21 for the plug is removed from the bottom surface of the connection hole 43 for forming the lower electrode. To expose the upper surface of the Also in this case, by performing the selective etching process using the silicon nitride film 22 as an etching stopper, the uniformity of the depth of the connection hole 43 for the lower electrode can be favorably controlled. The plane area of the lower electrode connection hole 43 is formed, for example, in a rectangular shape (actually, an elliptical shape).
One planar area is included. That is, in the second embodiment, the processing is not performed in the direction in which the planar region of the lower electrode forming hole 41 initially formed as the lower electrode forming region expands in a plane, but is formed first. The processing (processing of the connection hole 43 for the lower electrode) is performed in a direction in which the planar area of the formed hole 41 for the lower electrode is contracted in a plane. Therefore, the planar dimension of the finally formed lower electrode does not become larger than the planar dimension of the lower electrode forming hole 41 that is initially determined.

Next, a conductive film (second conductive film) 44a is deposited on the polycrystalline silicon film 40 in the hole 41 for forming the lower electrode and the connection hole 43 for the lower electrode by a CVD method or the like. Polycrystalline silicon film 40 and conductor film 44
a until the upper surface of the silicon oxide film 39 is exposed.
Etchback is performed by the MP method or anisotropic dry etching. Thereby, as shown in FIGS. 25, 26 and 27, the conductor film 44a is separated for each bit, and the lower electrode 45 of the capacitor is formed. The lower electrode 45 includes a conductor film 44a and sidewall spacers 42s formed on the upper side surface thereof.
This lower electrode 45 is electrically connected to the conductor film 21 through the polycrystalline silicon film 44 in the connection hole 43 for the lower electrode. FIG. 26 is a plan view of a main portion of the memory region M after the lower electrode 45 is formed. FIG.
It is sectional drawing of the C line. Note that the cross-sectional view of the memory region M in FIG. 25 is a cross-sectional view taken along the line AA in FIG.

Subsequently, by removing the silicon oxide film 39 by, for example, wet etching, the upper side surface of the lower electrode 45 (ie, the surface of the side wall spacer 42s) as shown in FIGS. 28 and 29.
To expose. At this time, by using the silicon nitride film 38 as an etching stopper, it is possible to prevent the underlying silicon oxide film 37 and the like from being removed by etching. Further, since the lower portion of the lower electrode 45 is embedded in the insulating film and the lower electrode 45 is firmly fixed, the lower electrode 45 can be prevented from collapsing. The constituent material of the lower electrode 45 is a conductive material other than polycrystalline silicon, for example, a refractory metal such as tungsten or ruthenium (Ru), or a conductive metal oxide such as ruthenium oxide (RuO ₂ ) or iridium oxide (IrO ₂ ). It can also be configured. FIG. 29 is a cross-sectional view taken along the line CC of FIG. 26 after this step.
It is sectional drawing corresponding to a line position.

Next, as shown in FIG.
5 is directly nitrided in, for example, 800 ° C. in an NH ₃ atmosphere to obtain amorphous tantalum pentoxide (Ta ₂ O).
₅ ) Deposit the film 46. Since tantalum pentoxide has a large leak current in the amorphous state, heat treatment is performed, for example, at 800 ° C. in an oxygen atmosphere to crystallize it. Thereafter, a titanium nitride film (not shown) is deposited on the tantalum pentoxide film 46 by a CVD method or the like, and the titanium nitride film and the tantalum pentoxide film 46 are patterned by dry etching using the photoresist film R5 as a mask. . Thereby, the upper electrode 47 made of the titanium nitride film, the capacitance insulating film made of the tantalum pentoxide film 46,
An information storage capacitor C composed of the lower electrode 45 made of a low-resistance polycrystalline silicon film is formed. During this patterning process, the silicon nitride film 38 may be removed by etching. This makes it possible to reduce the parasitic capacitance between the upper and lower wiring layers. Tantalum pentoxide film 46
Is, for example, pentaethoxy tantalum (Ta (OC
₂ H _{5) 5)} was deposited by the CVD method using a source gas,
The titanium nitride film is deposited by using, for example, a CVD method and a sputtering method in combination.

Through the steps so far, a memory cell composed of the memory cell selecting MISFET Qs and the capacitor C connected in series thereto is completed. Capacitor C
Is formed of, for example, (Ba, Sr) TiO3.
(Hereinafter referred to as BST), STO, BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT
(PbZr _X Ti _1-X O ₃ ), PLT (PbLa _X Ti
_1-X O ₃ ) and a high (ferro) dielectric film made of a metal oxide such as PLZT. Further, the upper electrode 47 may be formed of a conductive film other than the titanium nitride film, for example, a tungsten film.

Next, as shown in FIG. 31, a silicon oxide film 48 is deposited so as to cover the capacitor C, and then this silicon oxide film 48 is polished by the CMP method, as shown in FIGS. 32 and 33. After the surface is flattened, a silicon oxide film is deposited on the surface. FIG.
FIG. 3 is a cross-sectional view corresponding to the position of line CC in FIG. 26 after this step. The silicon oxide film 48 is deposited by, for example, a plasma CVD method using oxygen (or ozone) and tetraethoxysilane as a source gas. In addition, CMP
Silicon oxide film 48 formed when polished by the GaN method
Silicon oxide may be deposited thereon to repair fine scratches on the surface. Thereafter, the silicon oxide film 48, the silicon nitride film 38, and the silicon oxide films 37 and 36 are formed by photolithography and dry etching.
, Through holes 49a and 49b are formed. A part of the upper electrode 47 of the capacitor C is exposed from the bottom of the through hole 49a. Further, a part of the first layer wiring 35 is exposed from the bottom surface of the through hole 49b. Since the through hole 49b is formed through a plurality of insulating films including a silicon oxide film having a large thickness, the through hole 49b is formed.
The aspect ratio becomes extremely large. Subsequently, the plug 50 is formed inside the through holes 49a and 49b.
The plug 50 is formed, for example, by depositing a titanium film on the silicon oxide film 48 by a sputtering method, and further depositing a titanium nitride film and a tungsten film on the silicon oxide film 48 by a CVD method. , 49b
It is formed by leaving inside.

Next, a second-layer wiring 51 is formed on the silicon oxide film 48. Among the second-layer wirings 51, the wirings 51 formed in the peripheral circuit region are electrically connected to the first-layer wirings 35 through the through holes 49b. The second-layer wiring 51 is, for example, a silicon oxide film 48.
For example, a titanium nitride film, an aluminum (Al) alloy film, a titanium film, and a titanium nitride film are sequentially deposited thereon by a sputtering method, and are then formed by patterning these films by dry etching using a photoresist film as a mask. . Subsequently, a silicon oxide film 52 is formed on the silicon oxide film 48 by CV so as to cover the wiring 51 of the second layer.
It is deposited by the D method or the like. The wiring 51 of the second layer is
Since it is formed with a film thickness (for example, 400 nm or more) thicker than the wiring 35 of the layer, when deposited by the plasma CVD method as described above, for example, a region where the wiring of the second layer is dense (not shown) In this case, it is difficult to bury the space between the wirings. Therefore, in the first embodiment, the silicon oxide film 52 is deposited using a high-density plasma CVD method using monosilane, oxygen, and argon (Ar) as a source gas. Since the silicon oxide film 52 deposited by the high-density plasma CVD method has excellent gap fill properties, even in a region where the second-layer wirings 51 are densely packed,
The space between the wirings can be sufficiently buried.
Thereafter, the silicon oxide film 52 is etched using a photoresist film (not shown) as a mask, thereby forming the second
Through hole 5 exposing a part of wiring 51 of the layer
Form 3 Thereafter, a plug 54 is formed in the through hole 53 in the same manner as the plug 50, and a third layer is formed on the silicon oxide film 52 in the same manner as the second layer wiring 51.
The wiring 55 of the layer is formed. After that, the silicon oxide film 5
A passivation film 56 composed of, for example, a stacked film of a silicon oxide film and a silicon nitride film is deposited on the second layer 2 so as to cover the third-layer wiring 55 by a CVD method or the like.

As described above, according to the first embodiment, the following effects can be obtained.

(1) By forming the connection hole 43 for the lower electrode in a self-aligned manner with respect to the hole 41 for forming the lower electrode, a planar connection between the lower electrode 45 and the connection hole 43 for the lower electrode is formed. Since there is no need to secure a margin for alignment, miniaturization of the memory cell can be promoted.

(2) Lower electrode 45 and connection hole 4 for lower electrode
Since no misalignment occurs between the lower electrode 45 and the MISFET Qs, the increase in electrical resistance between the lower electrode 45 and the memory cell selecting MISFET Qs can be prevented.

(3) Since the plane area of the lower electrode 45 can be increased, the contact area between the lower electrode 45 and the conductor film 21 can be increased. Therefore, it is possible to reduce the electric resistance between the lower electrode 45 and the memory cell selecting MISFET Qs.

(4) Lower electrode 45 and connection hole 4 for lower electrode
Since there is no planar misalignment between them, no aperture is formed between them. That is, at the time of patterning the lower electrode, a problem such as a microtrench does not occur in the conductor film in the connection hole for the lower electrode. Therefore, the lower electrode 45 and the memory cell selecting MISFE
Reliability in electrical connection with TQs can be ensured.

(5) Since the plane area of the connection hole 43 for the lower electrode can be increased, the formation of the opening of the connection hole 43 becomes easy. In addition, it becomes easy to embed the conductor film in the connection hole 43. Therefore, the manufacture of the semiconductor device is facilitated, and the yield and reliability of the semiconductor device can be improved.

(6) During the process of forming the lower electrode 45,
Since the collapse can be prevented, the yield of the semiconductor device can be improved.

(Embodiment 2) In Embodiment 2, as a capacitive insulating film of a DRAM or FeRAM, for example, BST, STO, BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT (PbZr)
_X Ti _1-X O ₃ ), PLT (PbLa _X Ti
_A process in which a film needs to be formed in an oxidizing atmosphere such as _1-X O ₃ ), PLZT, or the like and uses a material that itself has a strong oxidizing power will be described. In this case, due to the nature of the capacitance insulating film, the lower electrode material of the capacitor is also made of a metal material such as platinum (Pt) that is not itself oxidized or an oxide such as ruthenium (Ru) or iridium (Ir). Materials having conductivity are preferred. Note that ruthenium oxide (RuO ₂ ), iridium oxide (IrO ₂ ), or the like can be used as the lower electrode material.

FIGS. 35 to 53 illustrate a method of manufacturing a semiconductor device according to the second embodiment. In addition, DRA
The sectional view of the peripheral circuit region of M is the same as that of the first embodiment, and is not shown.

First, in the second embodiment, after the steps of FIGS. 1 to 7 used in the description of the first embodiment, the conductor film 21 of FIG.
It is removed by a CMP method or an anisotropic dry etching method so as to be left only in the inside. At this time, in the second embodiment, as shown in FIG. 35, the upper surfaces of the conductor films 21 in the contact holes 19 and 20 are
Is slightly lower (for example, about 500 °) than the upper surface height of. Subsequently, as shown in FIG. 36, a titanium film 57 is deposited on the semiconductor substrate 1 by a CVD method or the like. After that, by performing a heat treatment on the semiconductor substrate 1,
As shown in FIG. 37, after forming a titanium silicide layer 58 at the contact interface between the titanium film 57 and the conductor film 21, the excess titanium film 57 is removed. The reason for removing the excess titanium film 57 is that titanium has a property that it easily attracts oxygen. Thereafter, for example, a titanium nitride film containing aluminum ((Ti, Al) N) is formed on the semiconductor substrate 1.
38) is deposited by a CVD method, a sputtering method or the like, and then etched back by a CMP method or the like, thereby forming a titanium silicide layer 58 as shown in FIG.
The conductor film 59 is formed only on the upper side. The barrier conductor film 60 is formed by the laminated film of the titanium silicide layer 58 and the conductor film 59.
To form By providing the barrier conductor film 60, the conductor film 21 directly connected to the semiconductor substrate 1
It is possible to prevent a silicide reaction from occurring at a contact portion of the capacitor with the lower electrode. Further, for example, at the time of the step of forming the capacitive insulating film in an oxygen atmosphere or at the time of the crystallization annealing step, oxygen is prevented from diffusing into the conductive film 21 via the lower electrode, and the upper part of the conductive film 21 is oxidized. And the occurrence of poor conduction can be prevented. (Ti,
The reason why the Al) N film was adopted was that it was found from the result of the study by the present inventors that this material had the highest ability to prevent diffusion of oxygen. Such a barrier conductor film 6
0 is not limited to the above-described materials, and can be variously changed. For example, a titanium nitride film, TaSi
Any of N, TiSiN, WSiN, or WN, or these or the above (Ti, Al) N films may be appropriately selected and stacked. The technique of forming the barrier conductor film 60 above the conductor film 21 as described above can also be applied to the capacitor C of the first embodiment. Also in this case, the same material as described above can be used for the constituent material of the barrier conductor film 60.

Next, as shown in FIG. 39, as in the first embodiment, the silicon nitride film 22, the silicon oxide film 23, the silicon oxide film 24, the silicon oxide film 36, the silicon oxide film 37, and the silicon nitride film 38 are formed. , A silicon oxide film 39 and a silicon nitride film 61 are sequentially deposited from the lower layer, and then, as shown in FIG.
A hole 41 for forming a lower electrode is formed. Silicon nitride film 6
1 is formed by the same CVD method as the other silicon nitride films. However, instead of the silicon nitride film 61, a polycrystalline silicon film 40 can be used as in the first embodiment. In the second embodiment, an example will be described in which a mask film for forming a connection hole for a lower electrode is not used as a part of the lower electrode, as described later. Therefore, the polycrystalline silicon film 40 is not used. , A silicon nitride film 61 is used. Subsequently, as shown in FIG. 41, as in the first embodiment, after forming a side wall spacer 42s2 on the side surface of the hole 41 for forming a lower electrode, a connection hole 43 for the lower electrode is formed. In the second embodiment, the sidewall spacer 42s2 is formed of, for example, a silicon nitride film. The reason is that the silicon nitride film 6
Same as 1. Therefore, a low-resistance polycrystalline silicon film can be used in place of the silicon nitride film in place of the side wall spacer 42s2 as in the first embodiment. However, the mask film (corresponding to the silicon nitride film 61 and the side wall 42s2) for forming the lower electrode forming hole and the lower electrode connecting hole as in the second embodiment is not limited to the lower electrode material. Thereby, the degree of freedom in material selection can be improved. Therefore, for example, it is possible to select a material with an emphasis on processability, such as selecting a material having high etching selectivity with a base or the like as a mask film.
It is possible to improve dimensional accuracy and reliability. Thereafter, in the second embodiment, as shown in FIGS. 42 and 43, the silicon nitride film 61 is removed under conditions such that the silicon nitride film is selectively etched away, and the side wall spacers 42s2 are also removed. Will be removed. FIG. 43 is a cross-sectional view of FIG.
This corresponds to a cross-sectional view taken along the line C.

Next, as shown in FIG. 44 and FIG. 45, a conductor film (for example, ruthenium (Ru))
The conductive film 44b is deposited by a CVD method, a sputtering method, a plating method (an electrolytic plating method and an electroless plating method), or the like. FIG. 45 is a cross-sectional view of FIG.
This corresponds to a cross-sectional view taken along the line C. When the electroless plating method is used to form the conductive film 44b, a thin conductive film made of, for example, ruthenium or the like is formed in the lower electrode forming hole 41,
After depositing in advance in the connection hole 43 for the lower electrode and on the silicon oxide film 39 by a CVD method or the like, a conductive film 44b is formed by an electrolytic plating method using the thin conductive film as a seed layer. The reason why ruthenium was selected as the material of the conductive film 44b is that processing is easier than other materials. In other words, the conductor film 44b is formed by CMP
This is because polishing is performed by a method or the like, and in that case, by using a solution in which rubidium is dissolved, polishing of the conductive film 44b can be facilitated. The material of the conductor film 44b is not limited to ruthenium but can be variously changed.
For example, platinum (Pt), rubidium oxide (RuO ₂ ), iridium (Ir), or iridium oxide (IrO ₂ ) can be used. When platinum is used as the lower electrode material, oxidation of the lower electrode can be prevented, so that the capacity of the capacitor C can be secured.
Subsequently, as shown in FIGS. 46 and 47, the conductive film 44b is polished by the CMP method as in the first embodiment, thereby forming the lower electrode forming hole 41 and the lower electrode connecting hole 43. Only the lower electrode 45 formed of the conductor film 44b is formed. FIG. 47 shows FIG. 2 after this step.
6 corresponds to a cross-sectional view taken along line CC.

Next, as in the first embodiment, the silicon oxide film 39 is removed using the silicon nitride film 38 as an etching stopper, as shown in FIGS. Expose. FIG. 49 corresponds to a cross-sectional view taken along line CC of FIG. 26 after this step. After this step, the silicon nitride film 38 may be selectively removed. By removing the silicon nitride film 38, the wiring capacitance and the like between different wiring layers can be reduced, and the operation reliability of the semiconductor device can be improved. Further, it is possible to promote the operation speed of the semiconductor device.
Subsequently, as shown in FIGS. 50 and 51, a capacitance insulating film 46 and an upper electrode 47 are formed as in the first embodiment. In the second embodiment, the capacitance insulating film 46 is made of, for example, BST, STO, BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT
(PbZr _X Ti _1-X O ₃ ), PLT (PbLa _X Ti
_It is a high (ferro) dielectric film made of a metal oxide such as _1-X O ₃ ) and PLZT. As the material of the upper electrode 47 in this case, for example, ruthenium is used from the viewpoint of ease of processing.
t), ruthenium oxide (RuO ₂ ), iridium (I
r) or iridium oxide (IrO ₂ ) can also be used. Subsequent steps are the same as in the first embodiment, and a description thereof will be omitted.

FIGS. 52 and 53 show a modification of the second embodiment. In FIG. 52, a barrier conductor film 61 is formed on the bottom surface of the connection hole 43 for the lower electrode so as to cover at least the upper surface of the conductor film 21. Also,
In FIG. 53, a barrier conductor film 60 is formed on the bottom and side surfaces of the connection hole 43 for the lower electrode. In any case, the barrier conductor film 60 may be a stacked film of the titanium silicide layer 58 and the conductor film 59 in the same manner as described above, or may be a single film of the barrier material described above or a stacked film thereof. It is good.

(Embodiment 3) Embodiment 3 describes a process for forming a lower electrode having a three-dimensional structure such as a crown shape. In the third embodiment, the projected area of the lower electrode portion of the capacitor is gradually reduced as the size of the semiconductor device is reduced, but the required storage capacity remains almost constant. This is in consideration of the fact that the lower electrode has a three-dimensional structure in order to secure a large capacitance.
Note that the third embodiment can be combined with the second embodiment.

FIGS. 54 to 60 illustrate a method of manufacturing a semiconductor device according to the third embodiment. In addition, DRA
The cross-sectional view of the peripheral circuit region of M is the same as that of the first embodiment, and therefore is not shown.

First, in the third embodiment, after the steps of FIGS. 1 to 7 used in the description of the first embodiment, the steps of FIGS. 35 to 43 used in the description of the second embodiment are performed. Then, as shown in FIGS. 54 and 55, with the mask film used for forming the connection hole for the lower electrode removed, the inner surface of the hole 41 for forming the lower electrode and A conductive film (second conductive film) 44c is deposited on the inner surface of the connection hole 43 for the lower electrode by a CVD method or the like. FIG. 55 corresponds to a cross-sectional view taken along line CC of FIG. 5 after this step. The conductor film 44c is made of, for example, low-resistance polycrystalline silicon or ruthenium, like the conductor films 44a and 44b described in the first and second embodiments. However, in the third embodiment, the thickness of the conductor film 44c is adjusted so that the entire inside of the lower electrode forming hole 41 is not filled with the conductor film 44c. Therefore, the conductor film 4
4c is attached to the side surface of the hole 41 for forming the lower electrode, but is not formed at the center of the plane of the hole 41;
The conductor film 44c in 1 has a concave cross section.

Subsequently, on the conductor film 44c, for example, S
After depositing a sacrificial film 62 made of an OG (Spin On Glass) film or a photoresist film and filling the depression on the upper surface of the conductor film 44c, a planarization process is performed on the upper surface of the sacrificial film 62. Thereafter, a part of the sacrificial film 62 and the conductor film 44c (the part on the silicon oxide film 39) is replaced with the silicon oxide film 3
By etching back by a CMP method or the like until the upper surface of 9 is exposed, a lower electrode 45 having, for example, a crown-shaped cross section is formed as shown in FIGS. FIG. 57 corresponds to a cross-sectional view taken along line CC of FIG. 26 after this step. Also in the third embodiment, similarly to the first and second embodiments, the lower electrode 45 of the capacitor is provided.
Is not larger than the first planar area of the lower electrode forming hole 41 during the process, so that the area occupied by the capacitor can be prevented from increasing.

Next, the silicon oxide film 39 is removed by etching using the silicon nitride film 38 as an etching stopper in the same manner as in the first and second embodiments.
As shown in FIG. 59, the surface of the side wall portion of the lower electrode 45 is exposed. FIG. 59 shows FIG. 26 after this step.
Corresponds to a cross-sectional view taken along the line CC of FIG. Subsequently, as shown in FIG. 60, a capacitance insulating film 46 and an upper electrode 47 are formed in the same manner as in the first or second embodiment.
Subsequent steps are the same as those in the first embodiment, and a description thereof will be omitted.

In the third embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained. That is, the cross-sectional shape of the lower electrode 45 of the capacitor C is made into a crown shape or the like, so that the lower electrode 45 is formed.
The surface area of the lower electrode 45 can be increased without increasing the occupied area of the capacitor C. Therefore, it is possible to increase the capacitance of the capacitor C with a small occupied area.

(Embodiment 4) Embodiment 4 is a modification of Embodiment 3, in which only the inside of a crown-shaped lower electrode is used as a capacitor.
Note that the fourth embodiment and the second embodiment can be combined.

First, in the fourth embodiment, a sacrificial film 62 made of a photoresist film is deposited in the steps described in FIGS. 54 and 55 of the third embodiment.
The sacrificial film 62 used here may be any material that can increase the etching selectivity with respect to the silicon oxide film 39.
Subsequently, as described with reference to FIGS. 56 and 57 of the third embodiment, the sacrificial film 62 and the conductor film 44c are etched back by CMP or the like to such an extent that the upper surface of the silicon oxide film 39 is exposed, thereby forming the lower electrode 45. Form. Thereafter, in the fourth embodiment, by removing only the sacrificial film 62 remaining inside the hollow at the center of the plane of the lower electrode 45, as shown in FIG. Only the upper surface is exposed. That is,
In the fourth embodiment, the silicon oxide film 39 is not removed. For this reason, the step difference between the memory region M and the peripheral circuit region P can be reduced. Therefore, the silicon oxide film 39
It is possible to improve the reliability and the dimensional accuracy of the wiring formed in a layer higher than that, particularly, the wiring formed over both the memory region M and the peripheral circuit region P. Thereafter, as shown in FIG.
Similarly to steps 2 and 3, the capacitor insulating film 46 and the upper electrode 47 are formed. Subsequent steps are the same as those in the first, second, and third embodiments, and a description thereof will be omitted.

(Fifth Embodiment) A fifth embodiment is a modification of the first embodiment, and is formed in a self-aligning manner with respect to a hole for forming a lower electrode of a capacitor which is an information storage capacitor. The connection hole for the lower electrode to be formed is directly connected to the semiconductor substrate 1. That is, the lower electrode is electrically connected directly to the semiconductor substrate without using a plug. According to the fifth embodiment, the number of steps of forming the conductive film 21 (plug) for the capacitor can be reduced, so that the number of steps and the number of photomasks can be reduced. The fifth embodiment can also have a crown shape as in the third and fourth embodiments.

FIGS. 63 to 69 illustrate the method of manufacturing the semiconductor device according to the fifth embodiment. In addition, DRA
The cross-sectional view of the peripheral circuit region of M is the same as that of the first embodiment, and therefore is not shown.

First, in the fifth embodiment, after the steps of FIGS. 1 and 2 used in the description of the first embodiment, FIG.
As shown in FIG.
6. Silicon oxide films 17 and 18 are formed. Subsequently, a photoresist film R6 is formed on the silicon oxide film 18 so that the plug formation region for the bit line is exposed and the other portions are covered. Similarly, contact hole 19
To form At this stage, no contact hole for the capacitor (corresponding to reference numeral 20 in the first embodiment) is formed. Thereafter, as shown in FIG.
After the conductive film 21 is buried in the contact hole 19 and a plug is formed in the same manner as in the first embodiment,
A bit line and a first layer wiring (not shown in FIG. 64) are formed, and a silicon nitride film 2 is formed on the silicon oxide film 18 and the conductor film 21 so as to cover them.
2, silicon oxide films 23, 36, 37, silicon nitride film 38, silicon oxide film 39, and polycrystalline silicon film 40
Is formed in the same manner as in the first embodiment.

Next, as shown in FIG. 65, as in the first embodiment, the polycrystalline silicon film 40, the silicon oxide film 39 and the silicon nitride film 38 are partially removed to form a hole for forming a lower electrode. 41 are formed, and a sidewall spacer 42s is formed on the inner wall surface. Subsequently, the silicon oxide films 37, 36, 23, the silicon nitride film 22, the silicon oxide films 18, 17, 16 and the silicon nitride film 13 are etched using the remaining polycrystalline silicon film 40 and the sidewall spacers 42s as an etching mask. By removing, a connection hole 43 for the lower electrode is formed as shown in FIG. The main surface of the semiconductor substrate 1 is exposed from the bottom surface of the connection hole 43 for the lower electrode. In this etching process, for example, the following is performed. First, the silicon oxide films 37 and 36 and the silicon oxide film 23 are selectively removed by etching using the silicon nitride film 22 as an etching stopper, and then the silicon nitride film 22 is selectively removed by etching. Subsequently, the silicon oxide film 1 is selectively etched using the silicon nitride film 13 as an etching stopper in the same manner as in the method of forming the contact hole 20 described in the first embodiment.
8, after the silicon oxide film 17 and the SOG film 16 are removed by etching, the silicon nitride film 13 is selectively removed by etching. By doing so, when forming the connection hole 43 for the lower electrode, there is no possibility of damaging the element in the lower layer.

Next, as shown in FIG. 67, as in the first embodiment, the conductor film 44a (or the conductor film 44)
b, 44c) are buried and etched back by a CMP method or the like to form the lower electrode 45.
The lower electrode 45 is directly in contact with and electrically connected to the semiconductor region 9 of the semiconductor substrate 1 under the lower electrode 45.
Subsequently, as shown in FIGS. 68 and 69, the capacitance insulating film 46 and the upper electrode 47 are formed as in the first, second, and third embodiments. FIG. 69 corresponds to a cross-sectional view taken along line CC of FIG. Hereinafter, the first and second embodiments,
Description is omitted because it is the same as 3 and 4.

(Embodiment 6) Embodiment 6 describes a process for forming a lower electrode having, for example, a bar-shaped cross section. Note that the sixth embodiment can be combined with the second and fifth embodiments.

First, in the sixth embodiment, after the steps shown in FIGS. 1 to 13 used in the description of the first embodiment, as shown in FIG.
On the silicon oxide film 37, a silicon nitride film 38 and a silicon oxide film 39 are sequentially deposited from a lower layer. In the sixth embodiment, the mask film (such as the polycrystalline silicon film 40) deposited in the first embodiment is not deposited. Further, similarly to the second embodiment, a barrier film may be formed on the upper surface of the conductor film 21. Subsequently, a photoresist film R7 is formed on the silicon oxide film 39 so that a planar rectangular opening for exposing the lower electrode formation region is formed and the other portions are covered. Using R7 as an etching mask, the silicon oxide film 39, the silicon nitride film 38, the silicon oxide films 37, 36, 23 and the silicon nitride film 22 are removed by etching to form holes 63 for forming a lower electrode. In this etching process, for example, the following is performed. First, using the silicon nitride film 38 as an etching stopper, the silicon oxide film 3
9 is selectively removed by etching. Subsequently, after removing the silicon nitride film 38, the etching conditions are changed, and the silicon oxide films 37, 36, and 23 are selectively etched away using the silicon nitride film 22 as an etching stopper.
Thereafter, the silicon nitride film 22 is selectively removed by etching. Thus, the hole 63 for the lower electrode can be formed without removing the insulating film at the bottom of the hole 63 for the lower electrode or damaging the element. The planar shape of the lower electrode hole 63 is the same as that of the first embodiment.

Then, after removing the photoresist film R7, as shown in FIG. 71, the conductor film 44a (or the conductor film 44b) is formed on the semiconductor substrate 1 in the same manner as in the first, second, third and fourth embodiments. The lower electrode 45 made of the conductor film 44a (or the conductor film 44b) is formed in the hole 63 for the lower electrode as shown in FIG. 72 by depositing and etching back by the CMP method or the like. In the sixth embodiment, the lower electrode 45 has a bar shape in cross section. Therefore, the manufacturing process can be simplified. The lower electrode 45 has a rod-shaped cross section, but is rectangular in plan, so that its surface area can be increased and its capacity can be ensured. Further, in the sixth embodiment, the lower electrode 45
It is suitable when platinum is used as the material for forming the above. It is generally known that when platinum is selected as the lower electrode material, the processing is difficult. However, in the sixth embodiment, since the lower electrode has a simple cross-sectional rod shape, a fine etching This is because they can be formed without performing the process. When platinum is used as a material for forming the lower electrode 45, a barrier film can be formed on the upper surface of the conductor film 21 in contact with the lower electrode 45, as in the second embodiment. After forming such a lower electrode 45, the silicon oxide film 39 is etched away using the silicon nitride film 38 as an etching stopper, thereby exposing only the upper portion of the lower electrode 45 as shown in FIG. Since the silicon nitride film 38 is used as an etching stopper, the lower insulating film and the element are not damaged during the etching process for exposing the upper portion of the lower electrode 45. Thereafter, as shown in FIG.
Similarly to 4 and 5, the capacitance insulating film 46 and the upper electrode 47 are formed. Hereinafter, the first, second, and third embodiments will be described.
The description is omitted because it is the same as 4 and 5.

(Embodiment 7) This embodiment 7 shows a modification of the arrangement of the memory cells, in which a connection between a bit line and a plug is provided between capacitors adjacent to each other in the bit line extending direction. This explains a structure in which no area is arranged. According to the seventh embodiment, it is possible to secure an arrangement margin in the connection hole for the lower electrode of the capacitor adjacent to each other in the extending direction of the bit line, so that the plane area of the lower electrode can be further increased. It is possible to increase the capacitance of the capacitor. Therefore, the seventh embodiment is particularly effective when applied to the case where the lower electrode 45 has a rod-like cross section as in the sixth embodiment. That is, by adopting the seventh embodiment, the lower electrode 4
This is because the capacity can be obtained even if the section 5 has a bar shape. However, the seventh embodiment can be applied to any of the first to fifth embodiments other than the sixth embodiment.
Since the cross-sectional structure is the same as that of any of the first to sixth embodiments, the description is omitted. The technical idea of the seventh embodiment is that a connection region between a bit line and a plug is not provided between capacitors adjacent to each other in a direction in which the bit line extends, and is limited to a specific planar structure to be described below. It is not something to be done.

In the seventh embodiment, as shown in FIGS. 75 and 76, the configuration of one memory cell MC is
Same as in the first to sixth embodiments, except that active regions L of individual memory cells MC are arranged obliquely. Therefore, the lower electrodes 45 of the two capacitors of the same memory cell MC are not arranged on the same straight line extending in the horizontal direction in FIGS. 75 and 76, and the lower electrodes 45 of the memory cells MC different from each other 45 are arranged. Figure 75
And active region L arranged on the same column in FIG.
Are arranged parallel to each other. The active regions L arranged on adjacent columns are arranged such that their inclination angles are inverted from each other.

In each active region L, two word lines WL are arranged not to be electrically connected but to overlap in a plane, and the active regions L where the two word lines WL are not arranged are arranged.
Are arranged so that the bit lines BL are overlapped in a plane at the center. The bit line BL extends so as to intersect with the word line WL, and is electrically connected to the semiconductor region of the memory cell selection MISFET Qs at the center of the active region L through the conductor film 21 in the contact hole 19. ing. The lower electrode 45 is provided in the contact hole 2
Memory cell selection MIS at both ends of the active region L through the conductor film 21 and the connection hole 43 for the lower electrode.
It is electrically connected to the semiconductor region of the FET Qs.

In the seventh embodiment, as described above, a region for connecting bit line BL and conductive film 21 is provided between lower electrodes 45 of capacitors C adjacent in the horizontal direction in FIGS. 75 and 76. Not been. Therefore, in the lower electrode 45 of the capacitor C, the horizontal dimension in FIGS. 75 and 76 can be further extended. That is, since the surface area of the lower electrode 45 can be increased, the capacitance of the capacitor C can be increased.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the above description, the case where the invention made by the present inventor is mainly applied to a DRAM or FeRAM which is a background of application is described. However, the present invention is not limited to this.
The present invention can be applied to a semiconductor device in which an M or FeRAM and a logic circuit are provided on the same semiconductor substrate.

[0099]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method of manufacturing a semiconductor device according to the present invention, the second opening for forming the first electrode is moved with respect to the first opening which is the connection hole for the first electrode. By piercing in a self-aligned manner, it is possible to prevent a planar misalignment between the first electrode and the connection hole for the first electrode.

(2) According to the above (1), it is possible to eliminate the necessity to secure a planar alignment allowance between the first electrode and the connection hole for the first electrode. Thus, miniaturization of the memory cell can be promoted.

(3) According to the above (1), it is possible to prevent an increase in electric resistance between the first electrode and the field effect transistor for selecting a memory cell.

(4) According to the above (1), no aperture is formed between the first electrode and the connection hole for the first electrode. That is, at the time of patterning the first electrode, a problem such as a microtrench does not occur in the conductor film in the connection hole for the first electrode. Therefore, reliability in electrical connection between the first electrode and the field effect transistor for selecting a memory cell can be ensured.

(5) According to the above (1), it is possible to eliminate the necessity of securing a planar alignment allowance between the first electrode and the connection hole for the first electrode. The plane area of the connection hole for the electrode can be increased. Therefore, it is easy to form the connection hole. In addition, it becomes easy to embed the conductor film in the connection hole. Therefore, the manufacture of the semiconductor device is facilitated, and the yield and reliability of the semiconductor device can be improved.

(6) According to the above (1), the reliability of connection between the first electrode and the connection hole for the first electrode can be improved.

(7) According to the above (1), the reliability of connection between the first electrode and the connection hole for the first electrode can be improved without complicating the process.

(8) According to the method of manufacturing a semiconductor device of the present invention, it is possible to prevent the collapse of the first electrode of the information storage capacitor during the formation process, thereby improving the yield of the semiconductor device. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2;

4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;

FIG. 5 is a plan view of a main part of a memory area of the semiconductor device after the step of FIG. 4;

FIG. 6 is a sectional view taken along line BB of FIG. 5;

FIGS. 7 (a) and (b) are views taken along lines AA and B-B of FIG. 5 during the manufacturing process of the semiconductor device following FIG.
It is sectional drawing of the B line.

8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;

9 (a) and 9 (b) are respectively a line AA and a line B-B of FIG. 5 during the manufacturing process of the semiconductor device following FIG.
It is sectional drawing of the B line.

10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;

11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10;

12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;

13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13;

15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15;

17 is a cross-sectional view of the semiconductor device at the time of the step of FIG. 16 corresponding to the position of line CC in FIG. 5;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 16 and 17;

19 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18;

20 is a cross-sectional view of the semiconductor device at the time of the process of FIG. 19, corresponding to the position taken along the line CC of FIG. 5;

21 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 19 and FIG. 20;

22 is a cross-sectional view of the semiconductor device at the time of the process of FIG. 21 corresponding to the position of line CC in FIG. 5;

23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21 and FIG. 22;

24 is a cross-sectional view of the semiconductor device at the time of the process of FIG. 23, corresponding to the position taken along the line CC of FIG. 5;

FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23 and FIG. 24;

26 is a plan view of relevant parts of a memory region of the semiconductor device after the step of FIG. 25;

FIG. 27 is a sectional view taken along line CC of FIG. 26;

FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25, FIG. 26 and FIG. 27;

FIG. 29 of the semiconductor device in the step of FIG. 28;
FIG. 5 is a cross-sectional view corresponding to a position taken along line CC of FIG.

30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28 and FIG. 29;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 30;

32 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 31;

FIG. 33 is a view of the semiconductor device in the step of FIG. 32;
FIG. 5 is a cross-sectional view corresponding to a position taken along line CC of FIG.

FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32 and FIG. 33;

FIG. 35 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;

36 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 35;

FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36;

38 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 37;

39 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 38;

40 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 39;

FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40;

42 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 41;

FIG. 43 is a cross-sectional view corresponding to the position of line CC in FIG. 5 at the time of the step of FIG. 42;

FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42 and FIG. 43;

FIG. 45 is a cross-sectional view corresponding to the position of line CC in FIG. 5 during the step of FIG. 44;

46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44 and FIG. 45;

FIG. 47 is a cross-sectional view corresponding to the position of line CC in FIG. 26 at the time of the step of FIG. 46;

FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46 and FIG. 47;

FIG. 49 is a cross-sectional view corresponding to the position of line CC in FIG. 26 at the time of the step of FIG. 48;

50 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 48 and FIG. 49;

FIG. 51 is a cross-sectional view corresponding to the position of line CC in FIG. 26 at the time of the step of FIG. 50;

FIG. 52 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;

FIG. 53 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;

FIG. 54 is a fragmentary cross-sectional view of the semiconductor device of another embodiment of the present invention during the manufacturing step thereof;

FIG. 55 is a cross-sectional view corresponding to the position of line CC in FIG. 5 at the time of the step of FIG. 54;

56 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 54 and FIG. 55;

FIG. 57 is a cross-sectional view corresponding to the position of line CC in FIG. 26 at the time of the step of FIG. 56;

58 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 56 and FIG. 57;

FIG. 59 is a cross-sectional view corresponding to the position of line CC in FIG. 26 at the time of the step of FIG. 58;

60 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 58 and FIG. 59;

61 is a fragmentary cross-sectional view of a semiconductor device according to another embodiment of the present invention during a manufacturing step thereof; FIG.

62 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 61;

FIG. 63 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;

64 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 63;

FIG. 65 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 64;

FIG. 66 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 65;

67 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 66;

FIG. 68 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 67;

69 is a cross-sectional view corresponding to a position taken along line CC of FIG. 26 at the time of the step of FIG. 68;

FIG. 70 is an essential part cross sectional view of the semiconductor device of another embodiment of the present invention during a manufacturing step;

FIG. 71 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 70;

FIG. 72 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 71;

73 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 72;

74 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 73;

FIG. 75 is a plan view of a main part during a manufacturing step of a semiconductor device according to still another embodiment of the present invention;

76 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 75;

[Explanation of symbols]

1 semiconductor substrate 2a, 2b p-well 3 semiconductor region 4 n-well 5 separating unit 6 separation groove 7 gate insulating film 8A, 8B, 8C gate electrode 9 n-type semiconductor regions 9a, 9b n ^- -type semiconductor regions 10a n ^- -type Semiconductor region 10b n ⁺ type semiconductor region 11a p ⁻ type semiconductor region 11b p ⁺ type semiconductor region 12 cap insulating film 13 silicon nitride film 13s sidewall spacer 16 SOG film 17 silicon oxide film 18 silicon oxide film 19 contact hole REFERENCE SIGNS LIST 20 contact hole 21 conductor film 22 silicon nitride film 23 silicon oxide film 24 through hole 25-29 contact hole 30 titanium film 31 titanium silicide layer 32 titanium nitride film 33 tungsten film 34 plug 35 first layer wiring 36 silicon oxide film 37 Silicon oxide film 3 Silicon nitride film 39 Silicon oxide film 40 Polycrystalline silicon film 41 Hole 42 Low resistance polycrystalline silicon film 42s, 42s2 Side wall spacer 43 Connection hole 44a Conductive film 44b Conductive film 44c Conductive film 45 Lower electrode 46 Tantalum pentoxide film 47 Upper electrode 48 silicon oxide film 49a, 49b through hole 50 plug 51 second layer wiring 52 silicon oxide film 53 through hole 54 plug 55 third layer wiring 56 passivation film 57 titanium film 58 titanium silicide layer 59 conductor film 60 barrier conductor Film 61 Silicon nitride film 62 Sacrificial film 63 Hole M Memory region P Peripheral circuit region Qs MISFET for memory cell selection LR1 to R7 Photoresist film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8247 29/788 29/792 F term (Reference) 5F001 AA17 AD12 AD17 AG07 AG09 AG10 AG40 5F038 AC05 AC09 AC15 DF05 EZ14 EZ15 EZ18 5F083 AD42 AD48 AD49 AD56 FR02 GA02 JA06 JA14 JA15 JA38 JA39 JA40 JA43 JA53 JA56 KA20 MA03 MA04 MA06 MA17 MA20 PR06 PR07 PR09 PR22 PR23 PR29 PR39 PR40 PR43 PR44 PR45 PR46 PR53 PR54 PR55 PR56

Claims (26)

[Claims] 1. A method of manufacturing a semiconductor device having a memory cell in which an information storage capacitive element and a memory cell selecting field effect transistor are connected in series, comprising: Forming a field effect transistor; (b) forming a first insulating film on the semiconductor substrate so as to cover the memory cell selecting field effect transistor; and (c) forming the first insulating film. After forming a connection hole in the film at a position where the semiconductor region of the memory cell selection field effect transistor is formed, a first hole electrically connected to the semiconductor region of the memory cell selection field effect transistor is formed in the connection hole. (E) forming a second insulating film and a sacrificial film on the semiconductor substrate after the step (c) in order, and (e).
After forming a first resist film for determining a plane pattern of a first electrode of the information storage capacitor on the sacrificial film, the second insulating film is formed on the sacrificial film using the first resist film as an etching mask. Forming a first opening that is exposed; and (f) removing the second insulating film that is exposed from the first opening, thereby forming the first conductor in the second insulating film. Forming a second opening for exposing a film in a self-aligned manner with respect to the first opening; and (g) forming the first opening in the first opening and the second opening. Forming a second electrode electrically connected to the conductive film to form a first electrode of the information storage capacitor formed by the second conductive film; and (h) Removing the sacrificial film to project a part of the first electrode. The method of manufacturing a semiconductor device, characterized in that. 2. The method for manufacturing a semiconductor device according to claim 1, wherein after the step (h), a step of forming a capacitor insulating film so as to cover a protruding surface of the first electrode; Forming a second electrode of the information storage capacitive element so as to cover the semiconductor device. 3. A method of manufacturing a semiconductor device having a memory cell in which an information storage capacitive element and a memory cell selecting field effect transistor are connected in series, comprising: Forming a field effect transistor; (b) forming a first insulating film on the semiconductor substrate so as to cover the memory cell selecting field effect transistor; and (c) forming the first insulating film. After forming a connection hole in the film at a position where the semiconductor region of the memory cell selection field effect transistor is formed, a first hole electrically connected to the semiconductor region of the memory cell selection field effect transistor is formed in the connection hole. (D) forming a second insulating film and a third insulating film on the semiconductor substrate after the step (c) in order,
(E) After forming a first resist film for determining a plane pattern of a first electrode of the information storage capacitor on the third insulating film, the third resist film is used as an etching mask. Forming a first opening in the film where the second insulating film is exposed; and (f) removing the second insulating film exposed from the first opening to form the second opening. Forming a second opening for exposing the first conductor film in the insulating film in a self-aligned manner with respect to the first opening; and (g) forming the second opening and the second opening. Forming a second conductor film electrically connected to the first conductor film in the opening of the first electrode of the information storage capacitor element formed by the second conductor film. Forming a semiconductor device. 4. A method of manufacturing a semiconductor device having a memory cell in which an information storage capacitive element and a memory cell selecting field effect transistor are connected in series, comprising: Forming a field effect transistor; (b) forming a first insulating film on the semiconductor substrate so as to cover the memory cell selecting field effect transistor; and (c) forming the first insulating film. Forming a second insulating film and a third insulating film thereon in sequence, and (d) determining a plane pattern of a first electrode of the information storage capacitor on the third insulating film. After forming one resist film, using it as an etching mask,
A first insulating film exposing the second insulating film to the third insulating film;
(E) removing the second insulating film and the first insulating film exposed from the first opening to form the second insulating film and the first insulating film. A second opening in which one of a pair of semiconductor regions of the memory cell selecting field effect transistor is exposed in the film;
Forming in a self-aligned manner with respect to the opening of
Forming a second conductive film in the first opening and the second opening, the second conductive film being electrically connected to one of a pair of semiconductor regions of the memory cell selecting field effect transistor; Forming a first electrode of an information storage capacitive element formed of the conductive film described above. 5. The method of manufacturing a semiconductor device according to claim 3, wherein a first conductive film is buried in the first opening and the second opening to form a first portion of the information storage capacitor. Forming the first electrode and after forming the first electrode,
Removing the third insulating film to project a part of the first electrode, forming a capacitive insulating film so as to cover a protruding surface of the first electrode, Forming a second electrode of the information storage capacitor element thereon. 6. The method for manufacturing a semiconductor device according to claim 3, wherein a second conductor film is formed in the first opening and the second opening so that a cross-sectional shape thereof is concave. Forming a first electrode of the information storage capacitor element having a concave cross section, and removing a portion of the first electrode having a concave cross section by removing the third insulating film;
Forming a capacitive insulating film so as to cover the protruding surface of the first electrode having a concave cross section; and forming a second electrode of the information storage capacitive element on the capacitive insulating film. A method for manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 3, wherein a second conductor film is formed in the first opening and the second opening so that a cross-sectional shape thereof is concave. Forming a first electrode of the information storage capacitor element having a concave cross section, forming a capacitance insulating film so as to cover an exposed surface of the first electrode having a concave cross section, Forming a second electrode of the information storage capacitor element thereon. 8. The method for manufacturing a semiconductor device according to claim 3, wherein after forming the third insulating film, forming a first mask film thereon. Forming the first opening in the third insulating film and the first mask film, forming a second mask film on a side surface of the first opening, and forming the first mask Forming the second opening in the second insulating film in a self-aligned manner with the first opening using the film and the second mask film as an etching mask. A method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 8, wherein said second mask film is formed of a conductive material,
After the second opening is formed, a conductor film is formed in the first opening and the second opening while the second mask film is left, so that the conductor film and the second film are formed. A method of manufacturing a semiconductor device, comprising a step of forming a first electrode of the information storage capacitor element formed by a second conductor film including a mask film. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the first electrode comprises forming the second opening, and leaving the second mask film.
A step of depositing the conductive film on the semiconductor substrate including the inside of the first opening and the second opening; and a step of shaving the conductive film until the third insulating film is exposed. Manufacturing method of a semiconductor device. 11. The method for manufacturing a semiconductor device according to claim 9, wherein said conductive film and said second mask film are made of a polycrystalline silicon film. 12. The method of manufacturing a semiconductor device according to claim 8, further comprising: after forming the second opening, removing the second mask film; and after removing the second mask film. The second opening in the first opening and the second opening.
Forming a first electrode of the information storage capacitor element formed by the second conductive film by forming the conductive film of (i). 13. The method of manufacturing a semiconductor device according to claim 12, wherein, in the step of forming the first electrode, after forming the second opening, removing the second mask film; Depositing the second conductive film on the semiconductor substrate including the inside of the first opening and the second opening, and shaving the second conductive film until the third insulating film is exposed; A method for manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 12, wherein said second mask film is made of a silicon nitride film, and said first, second and third insulating films are made of a silicon oxide film. A method for manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 3, wherein the second insulating film and the third insulating film are provided between the second insulating film and the third insulating film. Fourth, which can make the etching selectivity relatively large with respect to the insulating film.
Forming a first insulating film, and removing the third insulating film after the first electrode forming step, using the fourth insulating film as an etching stopper. . 16. The method of manufacturing a semiconductor device according to claim 15, wherein said second insulating film and said third insulating film are made of a silicon oxide film, and said fourth insulating film is made of a silicon nitride film. A method for manufacturing a semiconductor device. 17. The method of claim 1, 2, 3, 4, 5, 6, 7,
17. The method for manufacturing a semiconductor device according to 15 or 16,
The shape and dimensions of the plane of the first opening are the same as those of the second opening.
A method of manufacturing a semiconductor device, wherein the shape and size of the plane of the opening are the same. 18. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive film is a single film of platinum, ruthenium, ruthenium oxide, iridium, or iridium oxide, or any of these single films. A method for manufacturing a semiconductor device, comprising a laminated film formed by stacking two or more layers. 19. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier conductor film for suppressing diffusion of oxygen between the first conductor film and the second conductor film is provided. A method for manufacturing a semiconductor device, comprising a step of forming. 20. The method for manufacturing a semiconductor device according to claim 19, wherein the barrier conductor film is made of a titanium nitride film containing aluminum, a silicon nitride film, tantalum silicide, titanium nitride silicide, tungsten nitride silicide, titanium nitride or nitride. A semiconductor device comprising a single film of tungsten, a stacked film obtained by stacking any two or more of these single films, or a stacked film formed by stacking any one or more of the single films on a silicide film. Production method. 21. The method for manufacturing a semiconductor device according to claim 2, wherein the second conductive film is a single film of platinum, ruthenium, ruthenium oxide, iridium, or iridium oxide, or a stack of any two or more of these single films. Forming a barrier conductor film for suppressing diffusion of oxygen between the first conductor film and the second conductor film, wherein the capacitor insulating film is made of a PZT-based material. Alternatively, a method for manufacturing a semiconductor device, comprising a BST-based material. 22. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming a third conductor film on said insulating film. 23. The method of manufacturing a semiconductor device according to claim 22, wherein the plane pattern of the second opening is large in a direction parallel to a direction in which a wiring formed by the third conductive film extends. Is larger than the size in the vertical direction. 24. The method of manufacturing a semiconductor device according to claim 22, wherein the plane pattern of the second opening has a size in a direction parallel to an extending direction of a wiring formed by the third conductive film. Is larger than a size in a direction parallel to an extending direction of the wiring in the plane pattern of the first conductive film. 25. The method of manufacturing a semiconductor device according to claim 22, further comprising a memory cell array region in which a plurality of said memory cells are regularly arranged on said semiconductor substrate. A method of manufacturing a semiconductor device, wherein an interval between information storage capacitors is larger than a width of a wiring formed by the third conductive film. 26. A method of manufacturing a semiconductor device having a memory cell in which an information storage capacitive element and a memory cell selecting field effect transistor are connected in series, comprising: (a)
Forming the field effect transistor for memory cell selection on a semiconductor substrate; and (b) covering the field effect transistor for memory cell selection on the semiconductor substrate,
Forming a first insulating film; and (c) forming a connection hole in the first insulating film at a position where a semiconductor region of the memory cell selecting field effect transistor is formed, and Forming a first conductive film electrically connected to a semiconductor region of the memory cell selecting field effect transistor; and (d) forming a second insulating film and a third insulating film on the semiconductor substrate after the step (c). (E) forming a first resist film for determining a plane pattern of a first electrode of the information storage capacitor on the third insulating film, and then forming the first resist film on the third insulating film. As an etching mask,
Forming a first opening through which the first conductive film is exposed in the second and third insulating films; and (f) forming the first opening.
Forming a second conductor film electrically connected to the first conductor film in the opening of the first electrode of the information storage capacitor element formed by the second conductor film. Forming a semiconductor device.