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WO2002093638A1 - Mounting structure and mounting method for semiconductor chip - Google Patents

Mounting structure and mounting method for semiconductor chip Download PDF

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Publication number
WO2002093638A1
WO2002093638A1 PCT/JP2001/004089 JP0104089W WO02093638A1 WO 2002093638 A1 WO2002093638 A1 WO 2002093638A1 JP 0104089 W JP0104089 W JP 0104089W WO 02093638 A1 WO02093638 A1 WO 02093638A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
metal
connection
terminal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2001/004089
Other languages
French (fr)
Japanese (ja)
Inventor
Hidehiko Kira
Kenji Kobae
Norio Kainuma
Hiroshi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2002590410A priority Critical patent/JP4295517B2/en
Priority to PCT/JP2001/004089 priority patent/WO2002093638A1/en
Publication of WO2002093638A1 publication Critical patent/WO2002093638A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

Definitions

  • the present invention relates to a mounting structure for flip-chip mounting a semiconductor chip on a substrate and a mounting method thereof.
  • Conventional technology
  • the first method is a pressure bonding method in which the terminals of the semiconductor chip are pressed against the terminals of the substrate by contraction of the resin to make an electrical connection therebetween.
  • bumps 12 are formed by Au wires on terminal portions (aluminum terminal portions, not shown) of the semiconductor chip 10.
  • step 12 in order to match the height of the pump 1 2, crush it by pressing it on the plate 13 to crush it.
  • the conductive adhesive 15 is applied to the bump 12 by pressing against the conductive adhesive 15 applied on the glass plate 14 (FIG. 21).
  • an insulating adhesive 18 is applied to cover the terminals 17 of the substrate 16 (FIG. 22).
  • the substrate 16 and the semiconductor chip 10 are aligned and stacked, and heated in a furnace while being pressed by a pressing jig 19 to cure the insulating adhesive. Shrinkage of the insulating adhesive during cooling causes the bumps 1 2 to be pressed against the terminals 17, thereby establishing an electrical connection between the terminals 11 and 17.
  • the second method is to use an anisotropic conductive adhesive instead of the insulating adhesive 18 described above.
  • the method is the same as the first method up to the point that the bumps 12 are formed on the terminal portions of the semiconductor chip 10 and the bumps 12 are leveled.
  • anisotropic conductive adhesive 20 is applied so as to cover terminals 17 of substrate 16.
  • the substrate 16 and the semiconductor chip 10 are aligned and overlapped, and heated in a furnace while being pressurized by a pressing jig 19, and anisotropically conductive adhesive 20. To cure the It is.
  • the terminals 11 and 17 are brought into pressure contact with each other, and electrical conduction is established. Since the portion of the anisotropic conductive adhesive 20 pressed between both terminals is conductive, it is not necessary to apply the conductive adhesive 15 to the bumps 12 in advance as in the first method. .
  • the third method is a method in which the terminals of the semiconductor chip and the terminals of the substrate are metal-to-metal connected by ultrasonic waves.
  • bumps 12 are formed on the terminals of the semiconductor chip 10, while an insulating adhesive 18 is applied to the substrate 16 so as to cover the terminals 17.
  • the substrate 16 and the semiconductor chip 10 are aligned and overlapped, and ultrasonic waves are applied while applying pressure to the semiconductor chip 10 by the ultrasonic head 21.
  • the two terminals 11 and 17 are electrically connected by metal-to-metal connection.
  • the insulating adhesive 18 is hardened by separately heating in a furnace.
  • the first method has the following problems.
  • a curing step of the insulating adhesive 18 is required at the same time as the mounting of the semiconductor chip, which requires a long time of up to about 30 minutes.
  • the second method although the number of steps is relatively small, there is a probability that the conductive particles will not be sandwiched between the bumps 12 and the terminals 17 and the bonding reliability is poor. Further, there is a problem that a curing step of the anisotropic adhesive 20 is required, which also takes a long time.
  • the third method is the most advantageous method because the number of steps is small and the connection between terminals by ultrasonic waves can be performed in a short time of about 0.5 seconds.
  • this method is not suitable for connecting multiple pins (more than 30 pins).
  • the connection by ultrasonic waves is extremely short, transmission of ultrasonic energy cannot be performed uniformly, and although connection has not been made between certain terminals, connection has already been completed between other terminals. This is because the connection is broken when the ultrasonic wave is applied. Disclosure of the invention
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a mounting structure and a mounting method of a semiconductor chip in which connection between terminals is ensured even with a large number of pins. .
  • connection structure between the terminal of the semiconductor chip and the terminal of the substrate is connected to the group of metal-to-metal connection terminals connected by the metal-to-metal connection by pressure welding.
  • some of the terminal groups are connected by metal-to-metal connection using ultrasonic waves, and the remaining terminal groups are joined by pressure welding. But the connection can be made reliably.
  • a semiconductor chip with high reliability of connection even when stress is generated by making sure that the terminals at locations where stress occurs in the semiconductor chip due to the difference in thermal expansion between the semiconductor chip and the substrate is made of metal. Can be provided.
  • the ultrasonic connection step and the step of curing the insulating adhesive are separate steps, and the step of curing the insulating adhesive can be performed simultaneously in a furnace with a large number of substrates. Process time can be reduced.
  • FIG. 1 is an explanatory view of a state in which bumps are formed on a semiconductor chip
  • FIG. 2 is an explanatory view of a state in which an insulating adhesive is applied on a substrate
  • FIG. 3 is a state in which ultrasonic bonding is performed.
  • FIG. 4 is an explanatory view showing a stress concentration site on a semiconductor chip. 5 to 8 show a second embodiment
  • FIG. 5 is an explanatory view of a state in which a bump is formed at a portion of the semiconductor chip to be connected between metals
  • FIG. 6 is an explanatory view of a state in which a bump is formed at a portion of the substrate to be pressed and joined
  • FIG. FIG. 8 is an explanatory diagram of a state where an insulating adhesive is applied on a substrate
  • FIG. 8 is an explanatory diagram of a state where ultrasonic bonding is performed.
  • FIG. 9 is an explanatory view showing a state where the shape of the ultrasonic head is deformed in the third embodiment.
  • FIG. 10 is an explanatory view showing a fourth embodiment, in which a cushion material is arranged only at a necessary portion on the lower surface of the substrate.
  • FIGS. 11 to 15 show the fifth embodiment
  • FIG. 11 is an explanatory view showing a state in which bumps are formed on a portion of the semiconductor chip to be pressed and joined
  • FIG. 12 is an explanatory view showing leveling
  • FIG. 13 is a connection between metals of the semiconductor chip.
  • FIG. 14 is an explanatory view of a state in which bumps are formed at a portion to be processed
  • FIG. 14 is an explanatory view of a state in which an insulating adhesive sheet is arranged on a semiconductor chip
  • FIG. 15 is a state in which ultrasonic bonding is performed.
  • FIGS. 16 to 18 show the sixth embodiment
  • FIG. 16 is an explanatory view showing a state in which bumps are formed in two steps on a portion of a semiconductor chip to be connected between metals
  • FIG. 17 is an explanatory view showing a state in which an insulating adhesive is applied to a substrate.
  • FIG. 18 is an explanatory diagram of a state where ultrasonic bonding is performed.
  • FIGS. 19 to 23 show the first conventional method.
  • FIG. 19 is an explanatory view showing a state in which bumps are formed on a semiconductor chip
  • FIG. 20 is an explanatory view showing leveling
  • FIG. 21 is an explanatory view showing a state in which a conductive adhesive is applied to the bumps.
  • FIG. 22 is an explanatory view of a state in which an insulating adhesive is applied to the substrate
  • FIG. 23 is an explanatory view of a state in which pressure welding is performed.
  • FIGS. 24 to 25 show the second conventional method.
  • FIG. 24 is an explanatory view of a state in which an anisotropic conductive adhesive is applied on a substrate
  • FIG. 25 is an explanatory view of a state in which pressure welding is performed.
  • FIG. 26 to 28 show the third conventional method
  • FIG. 26 is an explanatory view of a state in which bumps are formed on a semiconductor chip
  • FIG. FIG. 28 is an explanatory diagram of a state in which an insulating adhesive is applied on a plate
  • FIG. 28 is an explanatory diagram of a state in which ultrasonic bonding is performed.
  • a bump 11 is provided on a terminal portion (aluminum terminal portion, not shown) of a semiconductor chip 10 by an Au wire by a known method to form a terminal 11.
  • the bump 12 may be formed by an Au plating film.
  • terminal including the semiconductor chip side and the mounting board side refers to a solid terminal section on which no processing is performed (the A1 terminal section on the semiconductor chip side, and the Cu terminal on the board side). Part) and the terminal part formed with a plating film or a bump made of a wire.
  • terminal refers to the one that has not processed anything.
  • an insulating adhesive 18 such as an epoxy resin is applied so as to cover the terminals 17 of the substrate 16.
  • Reference numeral 22 denotes a cushion material made of an elastic material such as rubber.
  • ultrasonic energy is applied to a part of the terminal group by the ultrasonic head 21 so that a part of the terminal group is connected to the metal by the ultrasonic wave.
  • connection condition between metals by ultrasonic waves is shown below.
  • the terminal group connected by the metal-to-metal connection be a terminal group in a portion where stress occurs in the semiconductor chip 10 due to a difference in thermal expansion between the semiconductor chip 10 and the substrate 16.
  • Thermal expansion coefficient of the semiconductor chip (silicon) is paired to a 3 ⁇ 4 X 1 0- 6 Z cm, the thermal expansion coefficient of the resin substrate is as large as 1 6 ⁇ 1 7 X 1 0- 6 / cm different. Therefore, the stress concentration due to the expansion and contraction of the substrate 16 is mainly directed to the four corner terminals 11 (portions indicated by black circles) of the semiconductor chip 10 as shown in FIG. Therefore, it is ensured that at least the connection between the terminal 11 at this portion and the corresponding terminal 17 on the substrate 16 side is made by ultrasonic connection.
  • the stress concentration due to the warpage of the substrate 16 is directed to the terminals 11 near the center of each side of the semiconductor chip 10 when the terminals 11 at the four corners of the semiconductor chip 10 are fixed.
  • the center of each side of the semiconductor chip 10 should be provided in addition to the terminal 11 at the four corners and the corresponding terminal 17. It is even more preferable that the connection between the nearby terminal 11 and the corresponding terminal 17 on the substrate 16 side is made by an ultrasonic wave.
  • a plurality of substrates 16 are housed in a heating furnace (not shown), and simultaneously pressurized and heated to obtain insulating properties.
  • the adhesive 18 is heated and hardened.
  • the connection between the terminals by ultrasonic waves is about 0.5 seconds, but the heat treatment in the furnace requires a long time of about 5 to 30 minutes.
  • both processes are separate, a large number of substrates can be housed in a heating furnace at a time, so that the overall processing time can be reduced.
  • the insulating adhesive 18 After the insulating adhesive 18 is hardened, it cools and contracts, so that both terminals 11 and 17 are pressed and electrically connected.
  • the terminal group to be pressure-welded may be connected between metals, but this is for preventing the ultrasonic energy from being dispersed as much as possible so that the target terminal group is reliably connected to the metal.
  • Metal diffusion rate when ultrasonic energy is applied is to make the metal composition between the terminals so that the metal diffusion rate is higher than the metal diffusion rate of the metal composition between the terminals to be press-welded.
  • the following metal configuration metal configuration on the terminal surface
  • metal configuration on the terminal surface metal configuration on the terminal surface
  • a wire bump 12 is formed by an Au wire on a terminal portion of the semiconductor chip 10 to be connected between metals.
  • the other terminal portions of the semiconductor chip 10 (the portions to be pressed and joined) expose the A1 terminal portions as they are.
  • an Au plating film (plating bump) 12a is formed on all the terminals on the substrate 16, and a wire bump 12 is further formed on the terminals to be press-welded by an Au wire. Form.
  • an insulating adhesive 18 is applied so as to cover the Au plating film 12 a and the wire bumps 12. The tip of the wire bump 17 slightly protrudes above the insulating adhesive 18.
  • the terminal 11 of the semiconductor chip 10 is positioned and placed on the terminal 17 of the substrate 16, and the ultrasonic head 21 is brought into contact with the semiconductor chip 10 while applying pressure. Ultrasonic is applied to join both terminals. Since the metal diffusion rate between Au and Au is higher than the metal diffusion rate between Au and A1, the terminals to be connected between metals are surely connected between metals.
  • the substrate 16 is accommodated in a heating furnace and subjected to a heat treatment to cure the insulating adhesive 18.
  • the metal diffusion rate between Au and Au is higher than the metal diffusion rate between Au and a metal other than Au.
  • it is Au plating film like 4
  • scratching the surface reduces the contact area, which reduces the metal diffusion rate.
  • Fig. 9 shows an example of an ultrasonic tool devised so that more ultrasonic energy concentrates on the terminals connected to the metal.
  • the ultrasonic head 21 is formed in a head shape so as to abut on the upper surface of the semiconductor chip 10 in the area where the terminals 11 and 17 to be connected between metals are arranged. ing.
  • Fig. 6 shows that the cushioning material 2 2 is placed on the lower surface side of the substrate 16 in the area where the terminals 11 and 17 to be connected between metals are placed, and the ultrasonic head 2 is attached to the terminals 11 and 17. Ultrasonic energy is concentrated by applying more than one load.
  • FIGS. 11 to 15 show a fifth embodiment.
  • a wire bump 12 is formed by an Au wire on a terminal portion of the semiconductor chip 10 to be pressed and joined.
  • the wire bumps 12 are pressed against the contact plate 13 to perform leveling to make the heights of the wire bumps 12 uniform.
  • a wire bump 12b is formed by an Au wire on a terminal portion of the semiconductor chip 10 to be connected between metals.
  • the insulating adhesive sheet 18a is arranged on the semiconductor chip 10.
  • the insulating adhesive sheet 18 b is a B-stage (uncured, flexible and sticky) sheet, with the wire bumps 12 buried and the sharp tips of the wire bumps 12 b Break through and expose the insulating adhesive sheet 18b.
  • the semiconductor chip 10 is placed with the terminal 11 of the semiconductor chip 10 aligned with the terminal 17 of the substrate 16, and the ultrasonic head 21 is brought into contact with the semiconductor chip 10 and pressurized. While applying ultrasonic waves, the two terminals are joined.
  • the semiconductor chip 10 is pressed by the ultrasonic head 21, so that both terminals 11 and 17 come into contact with each other. Then, pressure and heat treatment are performed in a heating furnace to thermally cure the insulating adhesive sheet 18b.
  • FIGS. 16 to 18 show a sixth embodiment.
  • wire bumps 12 are formed by Au wires on all terminal portions of the semiconductor chip 10, and further, on the first wire pumps 12 of the terminal portions to be connected between metals, A second wire bump 12c is formed by the Au wire.
  • the wire bumps of the terminal 11 to be connected between the metals are formed in two stages, and the height is higher than the other terminals.
  • an insulating adhesive 18 is applied so as to cover the terminals (the bumps of the Au plating film are formed) 17 (Fig. 17).
  • the semiconductor chip 10 is placed on the terminal 17 of the substrate 16 with the terminal 11 of the semiconductor chip 10 aligned, and the ultrasonic head 21 is attached to the semiconductor chip.
  • the two terminals are joined by applying ultrasonic waves while applying pressure.
  • the tall terminal 11 the terminal having the wire bump 12b
  • the ultrasonic energy is concentrated on this terminal.
  • the child's metal connection can be made reliably.
  • the other terminal 11 comes into contact with the terminal 17 when the ultrasonic connection is completed.
  • the insulating adhesive sheet 18b is thermally cured by applying pressure and heat in a heating furnace.
  • some terminal groups are connected by metal-to-metal connection using ultrasonic waves. And the remaining terminal groups are joined by pressure welding, so even multi-pin terminals can be reliably connected.
  • a semiconductor chip with high reliability of connection even when stress is generated by making sure that the terminals at locations where stress occurs in the semiconductor chip due to the difference in thermal expansion between the semiconductor chip and the substrate is made of metal. Can be provided.
  • the ultrasonic connection step and the step of curing the insulating adhesive are separate steps, and the step of curing the insulating adhesive can be performed in a furnace with a large number of substrates collectively. Therefore, the process time can be shortened as a whole.

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Abstract

A semiconductor chip having a large number of pins is connected reliably to terminals on a substrate. A mounting structure of a semiconductor chip includes bonds formed by ultrasonic welding and pressure welding, respectively. Thus, a semiconductor chip having a large number of pins can be connected reliably using the two types of welding, i.e., ultrasonic welding and pressure welding.

Description

明 細 書 半導体チップの実装構造および半導体チップの実装方法 技術分野  Description Semiconductor chip mounting structure and semiconductor chip mounting method

本発明は、 半導体チップを基板にフリップチップ実装する実装構造とその実装 方法に関する。 従来の技術  The present invention relates to a mounting structure for flip-chip mounting a semiconductor chip on a substrate and a mounting method thereof. Conventional technology

半導体チップを基板にフリップチップ実装する、 従来の代表的な 3つの方法に ついて説明する。  The following describes three typical conventional methods for flip-chip mounting a semiconductor chip on a substrate.

第 1の方法は、 樹脂の収縮によって、 半導体チップの端子を基板の端子に圧接 せしめて両者間の電気的接続をとる圧接接合方法である。  The first method is a pressure bonding method in which the terminals of the semiconductor chip are pressed against the terminals of the substrate by contraction of the resin to make an electrical connection therebetween.

まず、 図 1 9に示すように、 半導体チップ 1 0の端子部 （アルミニウム端子部、 図示せず） 上に A uワイヤによりバンプ 1 2を形成する。 次いで、 パンプ 1 2の 高さを一致させるために当板 1 3上に押しつけて潰すバンプレペリングを行う First, as shown in FIG. 19, bumps 12 are formed by Au wires on terminal portions (aluminum terminal portions, not shown) of the semiconductor chip 10. Next, in order to match the height of the pump 1 2, crush it by pressing it on the plate 13 to crush it.

(図 2 0 )。 次に、 ガラス板 1 4上に塗布した導電性接着剤 1 5に押し当てて、 バ ンプ 1 2上に導電性接着剤 1 5を付着させる （図 2 1 )。一方、 基板 1 6の端子 1 7を覆って絶縁性接着剤 1 8を塗布しておく （図 2 2 )。次に、 基板 1 6と半導体 チップ 1 0とを位置合わせして重ね、 加圧治具 1 9により加圧しつつ炉内で加熱 して絶縁性接着剤を硬化させる。 冷却時の絶縁性接着剤の収縮によりバンプ 1 2 が端子 1 7に圧接され、 これにより両端子 1 1、 1 7間の電気的接続がとられる(Figure 20). Next, the conductive adhesive 15 is applied to the bump 12 by pressing against the conductive adhesive 15 applied on the glass plate 14 (FIG. 21). On the other hand, an insulating adhesive 18 is applied to cover the terminals 17 of the substrate 16 (FIG. 22). Next, the substrate 16 and the semiconductor chip 10 are aligned and stacked, and heated in a furnace while being pressed by a pressing jig 19 to cure the insulating adhesive. Shrinkage of the insulating adhesive during cooling causes the bumps 1 2 to be pressed against the terminals 17, thereby establishing an electrical connection between the terminals 11 and 17.

(図 2 3 )。 (Figure 23).

第 2の方法は、 上記の絶縁性接着剤 1 8の代わりに異方性導電接着剤を用いる 方法である。 半導体チップ 1 0の端子部にバンプ 1 2を形成し、 このバンプ 1 2 をレべリングする点までは第 1の方法と同じである。一方、 図 2 4に示すように、 基板 1 6の端子 1 7を覆って異方性導電接着剤 2 0を塗布しておく。 そして、 図 2 5に示すように、 基板 1 6と半導体チップ 1 0とを位置合わせして重ね、 加圧 治具 1 9により加圧しつつ炉内で加熱して異方性導電接着剤 2 0を硬化させるの である。 異方性導電接着剤 2 0がやはり収縮することによって両端子 1 1、 1 7 が圧接し、 電気的導通がとられる。 両端子間で加圧された異方性導電接着剤 2 0 の部位が導電性を有するので、 第 1の方法のように、 あらかじめ導電性接着剤 1 5をバンプ 1 2に塗布する必要はない。 The second method is to use an anisotropic conductive adhesive instead of the insulating adhesive 18 described above. The method is the same as the first method up to the point that the bumps 12 are formed on the terminal portions of the semiconductor chip 10 and the bumps 12 are leveled. On the other hand, as shown in FIG. 24, anisotropic conductive adhesive 20 is applied so as to cover terminals 17 of substrate 16. Then, as shown in FIG. 25, the substrate 16 and the semiconductor chip 10 are aligned and overlapped, and heated in a furnace while being pressurized by a pressing jig 19, and anisotropically conductive adhesive 20. To cure the It is. When the anisotropic conductive adhesive 20 is also contracted, the terminals 11 and 17 are brought into pressure contact with each other, and electrical conduction is established. Since the portion of the anisotropic conductive adhesive 20 pressed between both terminals is conductive, it is not necessary to apply the conductive adhesive 15 to the bumps 12 in advance as in the first method. .

第 3の方法は、 超音波により半導体チップの端子と基板の端子とを金属間接続 させる方法である。  The third method is a method in which the terminals of the semiconductor chip and the terminals of the substrate are metal-to-metal connected by ultrasonic waves.

この場合には、 図 2 6に示すように、 半導体チップ 1 0の端子部にバンプ 1 2 を形成し、 一方基板 1 6には端子 1 7を覆って絶縁性接着剤 1 8を塗布しておき (図 2 7 )、図 2 8に示すように、基板 1 6と半導体チップ 1 0とを位置合わせし て重ね、 超音波ヘッド 2 1により半導体チップ 1 0を加圧しつつ超音波をかけ、 両端子 1 1、 1 7を金属間接続して電気的に接続するのである。 また、 別途炉内 で加熱して絶縁性接着剤 1 8を硬化させる。 技術的課題  In this case, as shown in FIG. 26, bumps 12 are formed on the terminals of the semiconductor chip 10, while an insulating adhesive 18 is applied to the substrate 16 so as to cover the terminals 17. Every other (FIG. 27), as shown in FIG. 28, the substrate 16 and the semiconductor chip 10 are aligned and overlapped, and ultrasonic waves are applied while applying pressure to the semiconductor chip 10 by the ultrasonic head 21. The two terminals 11 and 17 are electrically connected by metal-to-metal connection. Further, the insulating adhesive 18 is hardened by separately heating in a furnace. Technical issues

上記第 1の方法では次の課題がある。  The first method has the following problems.

すなわち、 単に接触しているだけの圧接接合の信頼性を高めるために、 バンプ 1 2に導電性接着剤 1 5を塗布する必要があり、 他の方法と比較して工程数が多 くなる。 また、 半導体チップ実装と同時に絶縁性接着剤 1 8の硬化工程が必要と なり、 最大 3 0分ほどの長時間を要する。  That is, it is necessary to apply the conductive adhesive 15 to the bumps 12 in order to increase the reliability of the pressure welding just in contact, and the number of steps is increased as compared with other methods. In addition, a curing step of the insulating adhesive 18 is required at the same time as the mounting of the semiconductor chip, which requires a long time of up to about 30 minutes.

上記第 2の方法では、 工程数は比較的少ないが、 バンプ 1 2と端子 1 7との間 に導電粒子を挟み込まない確率が生じ、 接合信頼性に劣る。 また、 異方性接着剤 2 0の硬化工程が必要となり、 やはり長時間を要するという課題がある。  In the second method, although the number of steps is relatively small, there is a probability that the conductive particles will not be sandwiched between the bumps 12 and the terminals 17 and the bonding reliability is poor. Further, there is a problem that a curing step of the anisotropic adhesive 20 is required, which also takes a long time.

また第 3の方法では、 工程数が少なく、 超音波による端子間接続も 0 . 5秒程 度の短時間で済むので最も優位な方法である。 しかし、 この方法では多ピン （3 0ピン以上） の接続には不向きである。 すなわち、 超音波による接続が極めて短 時間な故に、 超音波エネルギーの伝達が均一には行えず、 ある端子間ではまだ接 続されていないのに、 別な端子間では既に接続が完了し、 なおも超音波が付与さ れると逆に接続が破壊されることになるからである。 発明の開示 The third method is the most advantageous method because the number of steps is small and the connection between terminals by ultrasonic waves can be performed in a short time of about 0.5 seconds. However, this method is not suitable for connecting multiple pins (more than 30 pins). In other words, because the connection by ultrasonic waves is extremely short, transmission of ultrasonic energy cannot be performed uniformly, and although connection has not been made between certain terminals, connection has already been completed between other terminals. This is because the connection is broken when the ultrasonic wave is applied. Disclosure of the invention

そこで、 本発明は上記課題を解決すべくなされたものであり、 その目的とする ところは、 多ピンであっても端子間の接続が確実になされる半導体チップの実装 構造と実装方法を提供する。  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a mounting structure and a mounting method of a semiconductor chip in which connection between terminals is ensured even with a large number of pins. .

すなわち、 本発明に係る半導体チップの実装構造では、 半導体チップの端子と 基板の端子との間の接続構造が、 金属間接続により接続されている金属間接続端 子群と圧接接合により接続されている圧接接合端子群とに分かれていることを特 このように、 一部の端子群を超音波による金属間接続により接続し、 残りの端 子群を圧接接合により接合するので、 多ピンのものでも確実に接続を行うことが できる。  That is, in the mounting structure of the semiconductor chip according to the present invention, the connection structure between the terminal of the semiconductor chip and the terminal of the substrate is connected to the group of metal-to-metal connection terminals connected by the metal-to-metal connection by pressure welding. In this way, some of the terminal groups are connected by metal-to-metal connection using ultrasonic waves, and the remaining terminal groups are joined by pressure welding. But the connection can be made reliably.

特に、 半導体チップと基板との熱膨張差により半導体チップに応力が生じる部 位の端子群を超音波による確実な金属間接続とすることによって、 応力が生じて も接続の信頼性の高い半導体チップの実装構造を提供できる。  In particular, a semiconductor chip with high reliability of connection even when stress is generated by making sure that the terminals at locations where stress occurs in the semiconductor chip due to the difference in thermal expansion between the semiconductor chip and the substrate is made of metal. Can be provided.

また、 本発明の半導体チップの実装方法では、 前記基板の端子を覆って絶縁性 接着剤を塗布する工程と、 前記半導体チップを前記基板上に、 基板と半導体チッ プの対応する端子とが重なるように位置合わせして載置する工程と、 前記位置合 わせした後に、超音波装置の超音波へッドを半導体チップの所要部位に押し当て、 超音波を発して前記端子群の一部を金属間接合により接続する超音波接続工程と、 超音波接続工程の後に、 半導体チップを加圧しつつ、 加熱して前記絶縁性接着剤 を硬化させる工程とを含むことを特徴としている。  In the method for mounting a semiconductor chip according to the present invention, a step of applying an insulating adhesive to cover the terminals of the substrate, and the substrate and the corresponding terminal of the semiconductor chip overlap the semiconductor chip on the substrate. And positioning, and after the alignment, the ultrasonic head of the ultrasonic device is pressed against a required portion of the semiconductor chip, and an ultrasonic wave is emitted to partially remove the terminal group. It is characterized by including an ultrasonic connection step of connecting by metal-to-metal bonding, and, after the ultrasonic connection step, a step of heating the semiconductor chip while pressurizing the semiconductor chip to cure the insulating adhesive.

超音波接続工程と絶縁性接着剤を硬化させる工程とは別工程であり、 絶縁性接 着剤を硬化させる工程は多数の基板をまとめて一斉に炉内で行うことができるの で、 全体として工程時間の短縮が行える。 図面の簡単な説明  The ultrasonic connection step and the step of curing the insulating adhesive are separate steps, and the step of curing the insulating adhesive can be performed simultaneously in a furnace with a large number of substrates. Process time can be reduced. BRIEF DESCRIPTION OF THE FIGURES

図 1〜図 4は第 1実施例を示し、  1 to 4 show the first embodiment,

図 1は半導体チップ上にバンプを形成した状態の説明図であり、 図 2は基板上 に絶縁性接着剤を塗布した状態の説明図であり、 図 3は超音波接合している状態 の説明図であり、 図 4は、半導体チップ上での応力集中部位を示す説明図である。 図 5〜図 8は第 2実施例を示し、 FIG. 1 is an explanatory view of a state in which bumps are formed on a semiconductor chip, FIG. 2 is an explanatory view of a state in which an insulating adhesive is applied on a substrate, and FIG. 3 is a state in which ultrasonic bonding is performed. FIG. 4 is an explanatory view showing a stress concentration site on a semiconductor chip. 5 to 8 show a second embodiment,

図 5は半導体チップの金属間接続すべき部位にバンプを形成した状態の説明図 であり、 図 6は基板の圧接接合すべき部位にバンプを形成した状態の説明図であ り、 図 7は基板上に絶縁性接着剤を塗布した状態の説明図であり、 図 8は超音波 接合している状態の説明図である。  FIG. 5 is an explanatory view of a state in which a bump is formed at a portion of the semiconductor chip to be connected between metals, FIG. 6 is an explanatory view of a state in which a bump is formed at a portion of the substrate to be pressed and joined, and FIG. FIG. 8 is an explanatory diagram of a state where an insulating adhesive is applied on a substrate, and FIG. 8 is an explanatory diagram of a state where ultrasonic bonding is performed.

図 9は第 3実施例で、超音波へッドの形状を変形した状態を示す説明図である。 図 1 0は第 4実施例で、 クッション材を基板下面の必要部位のみに配置した状 態を示す説明図である。  FIG. 9 is an explanatory view showing a state where the shape of the ultrasonic head is deformed in the third embodiment. FIG. 10 is an explanatory view showing a fourth embodiment, in which a cushion material is arranged only at a necessary portion on the lower surface of the substrate.

図 1 1〜図 1 5は第 5実施例を示し、  FIGS. 11 to 15 show the fifth embodiment,

図 1 1は半導体チップの圧接接合すべき部位にバンプを形成した状態の説明図 であり、 図 1 2はレべリングを行った説明図であり、 図 1 3は半導体チップの金 属間接続をすべき部位にバンプを形成した状態の説明図であり、 図 1 4は半導体 チップ上に絶縁性接着剤シートを配置した状態の説明図であり、 図 1 5は超音波 接合している状態の説明図である。  FIG. 11 is an explanatory view showing a state in which bumps are formed on a portion of the semiconductor chip to be pressed and joined, FIG. 12 is an explanatory view showing leveling, and FIG. 13 is a connection between metals of the semiconductor chip. FIG. 14 is an explanatory view of a state in which bumps are formed at a portion to be processed, FIG. 14 is an explanatory view of a state in which an insulating adhesive sheet is arranged on a semiconductor chip, and FIG. 15 is a state in which ultrasonic bonding is performed. FIG.

図 1 6〜図 1 8は第 6実施例を示し、  FIGS. 16 to 18 show the sixth embodiment,

図 1 6は半導体チップの金属間接続すべき部位にバンプを 2段に形成した状態 を示す説明図であり、 図 1 7は基板に絶縁性接着剤を塗布した状態を示す説明図 であり、 図 1 8は超音波接合している状態の説明図である。  FIG. 16 is an explanatory view showing a state in which bumps are formed in two steps on a portion of a semiconductor chip to be connected between metals, and FIG. 17 is an explanatory view showing a state in which an insulating adhesive is applied to a substrate. FIG. 18 is an explanatory diagram of a state where ultrasonic bonding is performed.

図 1 9〜図 2 3は従来の第 1の方法を示すもので、  FIGS. 19 to 23 show the first conventional method.

図 1 9は半導体チップにバンプを形成した状態の説明図であり、 図 2 0はレべ リングを行った説明図であり、 図 2 1はバンプに導電性接着剤を塗布した状態の 説明図であり、 図 2 2は基板に絶縁性接着剤を塗布した状態の説明図であり、 図 2 3は圧接接合を行っている状態の説明図である。  FIG. 19 is an explanatory view showing a state in which bumps are formed on a semiconductor chip, FIG. 20 is an explanatory view showing leveling, and FIG. 21 is an explanatory view showing a state in which a conductive adhesive is applied to the bumps. FIG. 22 is an explanatory view of a state in which an insulating adhesive is applied to the substrate, and FIG. 23 is an explanatory view of a state in which pressure welding is performed.

図 2 4から図 2 5は従来の第 2の方法を示すもので、  FIGS. 24 to 25 show the second conventional method.

図 2 4は基板上に異方性導電接着剤を塗布した状態の説明図であり、 図 2 5は 圧接接合を行っている状態の説明図である。  FIG. 24 is an explanatory view of a state in which an anisotropic conductive adhesive is applied on a substrate, and FIG. 25 is an explanatory view of a state in which pressure welding is performed.

図 2 6〜図 2 8は従来の第 3の方法を示し、  Figures 26 to 28 show the third conventional method,

図 2 6は半導体チップ上にバンプを形成した状態の説明図であり、 図 2 7は基 板上に絶縁性接着剤を塗布した状態の説明図であり、 図 2 8は超音波接合を行つ ている状態の説明図である。 発明を実施するための最良の形態 FIG. 26 is an explanatory view of a state in which bumps are formed on a semiconductor chip, and FIG. FIG. 28 is an explanatory diagram of a state in which an insulating adhesive is applied on a plate, and FIG. 28 is an explanatory diagram of a state in which ultrasonic bonding is performed. BEST MODE FOR CARRYING OUT THE INVENTION

以下本発明の好適な実施例を添付図面に基づいて詳細に説明する。  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(第 1実施例）  (First embodiment)

前記従来の技術に示したのと同一の部材は同一符号を付す。  The same members as those shown in the prior art are denoted by the same reference numerals.

まず、 図 1に示すように、 半導体チップ 1 0の端子部 （アルミニウム端子部、 図示せず） 上に A uワイヤにより公知の手法によりバンプ 1 2を設けて端子 1 1 を形成する。 バンプ 1 2は A uめっき皮膜により形成してもよい。  First, as shown in FIG. 1, a bump 11 is provided on a terminal portion (aluminum terminal portion, not shown) of a semiconductor chip 10 by an Au wire by a known method to form a terminal 11. The bump 12 may be formed by an Au plating film.

なお、 本発明では、 半導体チップ側および実装基板側を含めて、 端子というと きは、 何も処理をしていない無垢の端子部 （半導体チップ側は A 1端子部、 基板 側は C u端子部） の他、 該端子部にめっき皮膜やワイヤによるバンプを形成した ものの双方を含むものとする。 端子部というときは、 何も処理をしていないもの をいう。  In the present invention, the term “terminal” including the semiconductor chip side and the mounting board side refers to a solid terminal section on which no processing is performed (the A1 terminal section on the semiconductor chip side, and the Cu terminal on the board side). Part) and the terminal part formed with a plating film or a bump made of a wire. The term “terminal” refers to the one that has not processed anything.

一方、 図 2に示すように、 基板 1 6の端子 1 7を覆って、 エポキシ樹脂等の絶 縁性接着剤 1 8を塗布する。  On the other hand, as shown in FIG. 2, an insulating adhesive 18 such as an epoxy resin is applied so as to cover the terminals 17 of the substrate 16.

そして、 図 3に示すように、 基板 1 6の端子 1 7に半導体チップ 1 0の端子 1 1を位置合わせして載せ、 超音波ヘッド 2 1を半導体チップ 1 0に当接し、 加圧 しながら超音波をかけて両端子を接合する。 なお、 2 2はゴム等の弾性材からな るクッション材である。  Then, as shown in FIG. 3, the terminal 11 of the semiconductor chip 10 is aligned and placed on the terminal 17 of the substrate 16, and the ultrasonic head 21 is brought into contact with the semiconductor chip 10 while applying pressure. Ultrasonic is applied to join both terminals. Reference numeral 22 denotes a cushion material made of an elastic material such as rubber.

この場合に、 超音波ヘッド 2 1により超音波のエネルギーが端子群の一部に加 わるようにし、 端子群の一部が超音波による金属間接続となるようにするのであ る。  In this case, ultrasonic energy is applied to a part of the terminal group by the ultrasonic head 21 so that a part of the terminal group is connected to the metal by the ultrasonic wave.

超音波による金属間接続条件の一例を下に示す。  An example of the connection condition between metals by ultrasonic waves is shown below.

タクト時間 = 1〜3秒  Takt time = 1-3 seconds

温度 = 3 0〜2 0 0 °C  Temperature = 30 ~ 200 ° C

超音波付与時間 = 0 . 5秒  Ultrasound application time = 0.5 seconds

荷重 = 3 0〜； 1 0 0 g /パンプ この金属間接続により接続される端子群が、 半導体チップ 1 0と基板 1 6との 熱膨張差により半導体チップ 1 0に応力が生じる部位の端子群となるようにする と好適である。 Load = 30-; 100 g / pump It is preferable that the terminal group connected by the metal-to-metal connection be a terminal group in a portion where stress occurs in the semiconductor chip 10 due to a difference in thermal expansion between the semiconductor chip 10 and the substrate 16.

半導体チップ （シリコン） の熱膨張係数は 3〜4 X 1 0— 6Z c mであるのに対 し、 樹脂製の基板の熱膨張係数は 1 6〜 1 7 X 1 0— 6 / c mと大きく異なる。 このため、 基板 1 6が伸縮することによる応力集中は、 図 4に示すように、 主 として、 半導体チップ 1 0の 4隅の端子 1 1 (黒丸で示した部位） に向けられる。 したがって、 少なくともこの部位の端子 1 1と基板 1 6側の対応する端子 1 7と の間が確実に超音波による金属間接続となるようにする。 Thermal expansion coefficient of the semiconductor chip (silicon) is paired to a 3~4 X 1 0- 6 Z cm, the thermal expansion coefficient of the resin substrate is as large as 1 6~ 1 7 X 1 0- 6 / cm different. Therefore, the stress concentration due to the expansion and contraction of the substrate 16 is mainly directed to the four corner terminals 11 (portions indicated by black circles) of the semiconductor chip 10 as shown in FIG. Therefore, it is ensured that at least the connection between the terminal 11 at this portion and the corresponding terminal 17 on the substrate 16 side is made by ultrasonic connection.

また、 基板 1 6の反りによる応力集中は、 半導体チップ 1 0の 4隅の端子 1 1 が固定された場合、 半導体チップ 1 0の各辺の中央部付近の端子 1 1に向けられ る。 この応力集中による端子間の接続の剥がれ等を防止するためには、 上記 4隅 の端子 1 1とこれに対応する端子 1 7との間の他、 半導体チップ 1 0の各辺の中 央部付近の端子 1 1とこれに対応する基板 1 6側の端子 1 7との間も超音波によ る金属間接続となるようにすると一層好適となる。  The stress concentration due to the warpage of the substrate 16 is directed to the terminals 11 near the center of each side of the semiconductor chip 10 when the terminals 11 at the four corners of the semiconductor chip 10 are fixed. In order to prevent the connection between the terminals from being peeled off due to this stress concentration, the center of each side of the semiconductor chip 10 should be provided in addition to the terminal 11 at the four corners and the corresponding terminal 17. It is even more preferable that the connection between the nearby terminal 11 and the corresponding terminal 17 on the substrate 16 side is made by an ultrasonic wave.

上記のように、 一部の端子群を超音波により金属間接続した後、 基板 1 6を複 数個加熱炉 （図示せず） に収容して同時に加圧、 加熱処理をして、 絶縁性接着剤 1 8を熱硬ィ匕させる。 超音波による端子の金属間接続は 0 . 5秒ほどであるが、 炉内での加熱処理は 5〜3 0分ほどの長時間を要する。 しかし、 両工程は別個で あるから、 まとめて多数の基板を加熱炉に収容して行えるので、 全体としての処 理時間は短縮できる。  As described above, after connecting some of the terminal groups to each other by ultrasonic waves, a plurality of substrates 16 are housed in a heating furnace (not shown), and simultaneously pressurized and heated to obtain insulating properties. The adhesive 18 is heated and hardened. The connection between the terminals by ultrasonic waves is about 0.5 seconds, but the heat treatment in the furnace requires a long time of about 5 to 30 minutes. However, since both processes are separate, a large number of substrates can be housed in a heating furnace at a time, so that the overall processing time can be reduced.

絶縁性接着剤 1 8が硬化した後、 冷却して収縮することにより、 両端子 1 1、 1 7が圧接され、 電気的に接続される。  After the insulating adhesive 18 is hardened, it cools and contracts, so that both terminals 11 and 17 are pressed and electrically connected.

(第 2実施例）  (Second embodiment)

上記の金属間接続される端子群に効率的に超音波エネルギーが集中するように、 種々の工夫をするとよい。 圧接接合される端子群が金属間接続されても構わない が、 できるだけ超音波エネルギーが分散されないようにして、 目的とする端子群 が確実に金属間接続されるようにするためである。  Various measures may be taken so that the ultrasonic energy is efficiently concentrated on the terminal group connected between the metals. The terminal group to be pressure-welded may be connected between metals, but this is for preventing the ultrasonic energy from being dispersed as much as possible so that the target terminal group is reliably connected to the metal.

そのための 1つの方法は、 金属間接続される端子間の金属構成の金属拡散速度 (超音波エネルギーが付与された際の金属拡散速度） の方が、 圧接接合される端 子間の金属構成の金属拡散速度よりも大きくなるように、 各端子間の金属構成を することである。 One way to do this is to use the metal diffusion rate of the metal (Metal diffusion rate when ultrasonic energy is applied) is to make the metal composition between the terminals so that the metal diffusion rate is higher than the metal diffusion rate of the metal composition between the terminals to be press-welded. .

例えば、 次の金属構成 （端子表面の金属構成） を採用できる。  For example, the following metal configuration (metal configuration on the terminal surface) can be adopted.

金属間接続側 圧接接合側  Metal connection side Pressure welding side

チップ端子 基 te端子 チップ而子 基板端子 Chip terminal Base te terminal Chip board substrate terminal

① Auめっき皮膜 Auめっき皮膜 A uめっき皮膜 Cu端子部① Au plating film Au plating film A u plating film Cu terminal

② Auめっき皮膜 A uめっき皮膜 A uめっき皮膜 S nめっき皮膜② Au plating film A u plating film A u plating film S n plating film

③ Auめっき皮膜 Auめっき皮膜 Auめっき皮膜 Cuめっき皮膜③ Au plating film Au plating film Au plating film Cu plating film

④ Auめっき皮膜 Auめっき皮膜 Auめっき皮膜 Auめっき皮膜 ④ Au plating film Au plating film Au plating film Au plating film

(傷を入れる） (Scratch)

⑤ Auワイヤバンプ A uめっき皮膜 A 1端子部 A uワイヤバンプ この⑤の場合を図 5〜図 8により説明する。 ⑤ Au wire bump A u plating film A 1 terminal part A u wire bump The case of ① is described with reference to FIGS.

図 5に示すように、 半導体チップ 1 0の、 金属間接続すべき端子部上に Auヮ ィャによりワイヤバンプ 1 2を形成する。 半導体チップ 1 0の他の端子部 （圧接 接合する部位） は、 A 1端子部をそのまま露出させている。  As shown in FIG. 5, a wire bump 12 is formed by an Au wire on a terminal portion of the semiconductor chip 10 to be connected between metals. The other terminal portions of the semiconductor chip 10 (the portions to be pressed and joined) expose the A1 terminal portions as they are.

一方、 図 6に示すように、 基板 1 6上の全端子部上に Auめっき皮膜 （めっき バンプ） 1 2 aを形成し、 圧接接合すべき端子部上にはさらに Auワイヤにより ワイヤバンプ 1 2を形成する。 そして図 7に示すように、 A uめっき皮膜 1 2 a やワイヤバンプ 1 2を覆って絶縁性接着剤 1 8を塗布する。 ワイヤバンプ 1 7の 先端は絶縁性接着剤 1 8上に若干突出する。  On the other hand, as shown in Fig. 6, an Au plating film (plating bump) 12a is formed on all the terminals on the substrate 16, and a wire bump 12 is further formed on the terminals to be press-welded by an Au wire. Form. Then, as shown in FIG. 7, an insulating adhesive 18 is applied so as to cover the Au plating film 12 a and the wire bumps 12. The tip of the wire bump 17 slightly protrudes above the insulating adhesive 18.

次いで、 図 8に示すように、 基板 1 6の端子 1 7に半導体チップ 1 0の端子 1 1を位置合わせして載せ、 超音波ヘッド 2 1を半導体チップ 1 0に当接し、 加圧 しながら超音波をかけて両端子を接合する。 A u— A u間の金属拡散速度の方が、 Au— A 1間の金属拡散速度よりも大きいので、 金属間接続すべき端子間が確実 に金属間接続される。 次に基板 1 6を加熱炉中に収容して加熱処理し、 絶縁性接 着剤 1 8を硬化させるのである。  Next, as shown in FIG. 8, the terminal 11 of the semiconductor chip 10 is positioned and placed on the terminal 17 of the substrate 16, and the ultrasonic head 21 is brought into contact with the semiconductor chip 10 while applying pressure. Ultrasonic is applied to join both terminals. Since the metal diffusion rate between Au and Au is higher than the metal diffusion rate between Au and A1, the terminals to be connected between metals are surely connected between metals. Next, the substrate 16 is accommodated in a heating furnace and subjected to a heat treatment to cure the insulating adhesive 18.

上記のように、 A u— A u間の金属拡散速度の方が、 Auと Au以外の他の金 属との間の金属拡散速度よりも大きい。 なお④のように Auめっき皮膜であって も、 その表面に傷を入れることによって、 接触面積が小さくなるから、 金属拡散 速度が低くなる。 As described above, the metal diffusion rate between Au and Au is higher than the metal diffusion rate between Au and a metal other than Au. In addition, it is Au plating film like ④ However, scratching the surface reduces the contact area, which reduces the metal diffusion rate.

このように、 金属拡散速度に差をもたせることにより、 超音波エネルギーを付 与した際、 金属拡散速度の大きい端子間が確実に金属間接続されることになる。  In this way, by providing a difference in the metal diffusion speed, when ultrasonic energy is applied, terminals having a high metal diffusion speed are surely connected between metals.

(第 3実施例）  (Third embodiment)

図 9は、 金属間接続する側の端子間により多く超音波エネルギーが集中しゃす いように超音波ツールに工夫をした例である。  Fig. 9 shows an example of an ultrasonic tool devised so that more ultrasonic energy concentrates on the terminals connected to the metal.

この実施例では、 超音波ヘッド 2 1を、 金属間接続すべき端子 1 1、 1 7が配 置されているエリアの半導体チップ 1 0の上面に当接するようにへッド形状を形 成している。  In this embodiment, the ultrasonic head 21 is formed in a head shape so as to abut on the upper surface of the semiconductor chip 10 in the area where the terminals 11 and 17 to be connected between metals are arranged. ing.

(第 4実施例）  (Fourth embodiment)

図 6は、 クッション材 2 2が、 金属間接続すべき端子 1 1、 1 7が配置されて いるエリアの基板 1 6の下面側に配置し、 当該端子 1 1、 1 7に超音波ヘッド 2 1からより多くの荷重が加わるようにして超音波エネルギーを集中させるように している。  Fig. 6 shows that the cushioning material 2 2 is placed on the lower surface side of the substrate 16 in the area where the terminals 11 and 17 to be connected between metals are placed, and the ultrasonic head 2 is attached to the terminals 11 and 17. Ultrasonic energy is concentrated by applying more than one load.

(第 5実施例）  (Fifth embodiment)

図 1 1〜図 1 5に第 5実施例を示す。  FIGS. 11 to 15 show a fifth embodiment.

図 1 1に示すように半導体チップ 1 0の、 圧接接合すべき端子部上に A uワイ ャによりワイヤバンプ 1 2を形成する。  As shown in FIG. 11, a wire bump 12 is formed by an Au wire on a terminal portion of the semiconductor chip 10 to be pressed and joined.

次に図 1 2に示すように、 ワイヤバンプ 1 2を当板 1 3に押し当ててワイヤバ ンプ 1 2の高さを揃えるレべリングを行う。  Next, as shown in FIG. 12, the wire bumps 12 are pressed against the contact plate 13 to perform leveling to make the heights of the wire bumps 12 uniform.

次いで図 1 3に示すように、 半導体チップ 1 0の金属間接続をすべき端子部上 に A uワイヤによりワイヤバンプ 1 2 bを形成する。  Next, as shown in FIG. 13, a wire bump 12b is formed by an Au wire on a terminal portion of the semiconductor chip 10 to be connected between metals.

そして図 1 4に示すように、 半導体チップ 1 0上に、 絶縁性接着剤シート 1 8 aを配置する。 絶縁性接着剤シート 1 8 bは Bステージ （未硬化で、 柔軟性かつ 粘着性を有するもの） 状のシートであって、 ワイヤバンプ 1 2は埋没し、 ワイヤ バンプ 1 2 bの尖った先端部は絶縁性接着剤シート 1 8 bを突き破り、露出する。 この半導体チップ 1 0を、 基板 1 6の端子 1 7に半導体チップ 1 0の端子 1 1 を位置合わせして載せ、 超音波ヘッド 2 1を半導体チップ 1 0に当接し、 加圧し ながら超音波をかけて両端子を接合する。 その際、 絶縁性接着材シート 1 8 bか ら突出しているワイヤバンプ 1 2 bの先端部に超音波エネルギーが集中するから、 金属間接続すべき端子の金属間接続が確実に行えるのである。 他の端子は、 超音 波へッド 2 1により半導体チップ 1 0が押圧されるから、 両端子 1 1、 1 7が当 接する状態となる。 次いで加熱炉で加圧、 加熱処理して絶縁性接着剤シート 1 8 bを熱硬化させるのである。 Then, as shown in FIG. 14, the insulating adhesive sheet 18a is arranged on the semiconductor chip 10. The insulating adhesive sheet 18 b is a B-stage (uncured, flexible and sticky) sheet, with the wire bumps 12 buried and the sharp tips of the wire bumps 12 b Break through and expose the insulating adhesive sheet 18b. The semiconductor chip 10 is placed with the terminal 11 of the semiconductor chip 10 aligned with the terminal 17 of the substrate 16, and the ultrasonic head 21 is brought into contact with the semiconductor chip 10 and pressurized. While applying ultrasonic waves, the two terminals are joined. At that time, since the ultrasonic energy is concentrated at the tip of the wire bump 12 b protruding from the insulating adhesive sheet 18 b, the metal-to-metal connection of the terminal to be connected can be reliably performed. As for the other terminals, the semiconductor chip 10 is pressed by the ultrasonic head 21, so that both terminals 11 and 17 come into contact with each other. Then, pressure and heat treatment are performed in a heating furnace to thermally cure the insulating adhesive sheet 18b.

(第 6実施例）  (Sixth embodiment)

図 1 6〜図 1 8に第 6実施例を示す。  FIGS. 16 to 18 show a sixth embodiment.

図 1 6に示すように、 半導体チップ 1 0の全端子部上に A uワイヤによりワイ ャバンプ 1 2を形成し、 さらに金属間接続すべき端子部の上記第 1のワイヤパン プ 1 2上に、 A uワイヤにより第 2のワイヤバンプ 1 2 cを形成する。  As shown in FIG. 16, wire bumps 12 are formed by Au wires on all terminal portions of the semiconductor chip 10, and further, on the first wire pumps 12 of the terminal portions to be connected between metals, A second wire bump 12c is formed by the Au wire.

すなわち、 金属間接続すべき端子 1 1のワイヤバンプが 2段に形成され、 他の 端子よりも高さを高くするのである。  That is, the wire bumps of the terminal 11 to be connected between the metals are formed in two stages, and the height is higher than the other terminals.

基板 1 6上には端子 （A uめっき皮膜のバンプを形成してある） 1 7を覆って 絶縁性接着剤 1 8を塗布する （図 1 7 )。  On the substrate 16, an insulating adhesive 18 is applied so as to cover the terminals (the bumps of the Au plating film are formed) 17 (Fig. 17).

次いで図 1 8に示すように、 半導体チップ 1 0を、 基板 1 6の端子 1 7に半導 体チップ 1 0の端子 1 1を位置合わせして載せ、 超音波へッド 2 1を半導体チッ プ 1 0に当接し、 加圧しながら超音波をかけて両端子を接合する。 その際、 高さ の高い端子 1 1 (ワイヤバンプ 1 2 bを有する端子） が基板 1 6側の端子 1 7と まず当接し、 この端子に超音波エネルギーが集中するから、 金属間接続すべき端 子の金厲間接続が確実に行えるのである。 他の端子 1 1は、 超音波接続が完了す る時点で端子 1 7に当接する状態となる。 次いで加熱炉で加圧、 加熱処理して絶 縁性接着剤シート 1 8 bを熱硬化させるのである。  Next, as shown in FIG. 18, the semiconductor chip 10 is placed on the terminal 17 of the substrate 16 with the terminal 11 of the semiconductor chip 10 aligned, and the ultrasonic head 21 is attached to the semiconductor chip. The two terminals are joined by applying ultrasonic waves while applying pressure. At that time, the tall terminal 11 (the terminal having the wire bump 12b) first contacts the terminal 17 on the substrate 16 side, and the ultrasonic energy is concentrated on this terminal. The child's metal connection can be made reliably. The other terminal 11 comes into contact with the terminal 17 when the ultrasonic connection is completed. Next, the insulating adhesive sheet 18b is thermally cured by applying pressure and heat in a heating furnace.

以上、 本発明の好適な実施例について種々述べたが、 本発明は上述の実施例に 限定されるのではなく、 発明の精神を逸脱しない範囲でさらに多くの改変を施し 得るのはもちろんである。 発明の効果  Various preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and it goes without saying that many more modifications can be made without departing from the spirit of the invention. . The invention's effect

以上のように、 本発明によれば、 一部の端子群を超音波による金属間接続によ り接続し、 残りの端子群を圧接接合により接合するので、 多ピンのものでも確実 に接続を行うことができる。 As described above, according to the present invention, some terminal groups are connected by metal-to-metal connection using ultrasonic waves. And the remaining terminal groups are joined by pressure welding, so even multi-pin terminals can be reliably connected.

特に、 半導体チップと基板との熱膨張差により半導体チップに応力が生じる部 位の端子群を超音波による確実な金属間接続とすることによって、 応力が生じて も接続の信頼性の高い半導体チップの実装構造を提供できる。  In particular, a semiconductor chip with high reliability of connection even when stress is generated by making sure that the terminals at locations where stress occurs in the semiconductor chip due to the difference in thermal expansion between the semiconductor chip and the substrate is made of metal. Can be provided.

また、 本発明方法では、 超音波接続工程と絶縁性接着剤を硬化させる工程とは 別工程であり、 絶縁性接着剤を硬化させる工程は多数の基板をまとめて一斉に炉 内で行うことができるので、 全体として工程時間の短縮が行える。  In addition, in the method of the present invention, the ultrasonic connection step and the step of curing the insulating adhesive are separate steps, and the step of curing the insulating adhesive can be performed in a furnace with a large number of substrates collectively. Therefore, the process time can be shortened as a whole.

Claims

請 求 の 範 囲 The scope of the claims 1 . 基板上に半導体チップがフリップチップ実装により搭載される半導体チップ の実装構造において、 1. In a semiconductor chip mounting structure in which a semiconductor chip is mounted on a substrate by flip chip mounting, 前記半導体チップの端子と前記基板の端子との間の接続構造が、 金属間接続に より接続されている金属間接続端子群と圧接接合により接続されている圧接接合 端子群とに分かれていることを特徴とする半導体チップの実装構造。  The connection structure between the terminal of the semiconductor chip and the terminal of the substrate is divided into a group of metal-to-metal connection terminals connected by metal-to-metal connection and a group of pressure-bonded connection terminals connected by pressure-bonded bonding. A semiconductor chip mounting structure. 2 . 前記金属間接続端子群が、 半導体チップと基板との熱膨張差により半導体チ ップに応力が生じる部位の端子群であることを特徴とする請求の範囲 1記載の半 導体チップの実装構造。 2. The semiconductor chip mounting according to claim 1, wherein the metal-to-metal connection terminal group is a terminal group in a portion where a stress is applied to the semiconductor chip due to a difference in thermal expansion between the semiconductor chip and the substrate. Construction. 3 . 前記金属間接続端子群が、 半導体チップの 4隅に位置する端子群を含むこと を特徴とする請求の範囲 1または 2記載の半導体チップの実装構造。 3. The semiconductor chip mounting structure according to claim 1, wherein the inter-metal connection terminal group includes terminal groups located at four corners of the semiconductor chip. 4 . 前記金属間接続端子群が、 半導体チップの各辺の中間に位置する端子群を含 むことを特徴とする請求の範囲 3記載の半導体チップの実装構造。 4. The semiconductor chip mounting structure according to claim 3, wherein the inter-metal connection terminal group includes a terminal group located in the middle of each side of the semiconductor chip. 5 . 前記金属間接続される端子間の金属構成の金属拡散速度の方が、 前記圧接接 合される端子間の金属構成の金属拡散速度よりも大きくなるように、 各端子間の 金属構成がされていることを特徴とする請求の範囲 1、 2、 3または 4記載の半 導体チップの実装構造。 5. The metal configuration between the terminals is set such that the metal diffusion rate of the metal configuration between the terminals connected between the metals is greater than the metal diffusion rate of the metal configuration between the terminals connected by the pressure connection. The mounting structure of a semiconductor chip according to claim 1, 2, 3, or 4, wherein: 6 . 前記金属間接続端子群が A u— A uの金属間接続により接続され、 前記圧接 接合端子群が A uと A u以外の金属との圧接接合により接続されていることを特 徴とする請求の範囲 5記載の半導体チップの実装構造。 6. The metal-to-metal connection terminal group is connected by a metal-to-metal connection of Au-Au, and the pressure-bonded connection terminal group is connected to the metal by a pressure-bonded connection between Au and a metal other than Au. A mounting structure for a semiconductor chip according to claim 5. 7 . 基板上に半導体チップをフリップチップ実装により搭載する半導体チップの 実装方法において、 前記基板の端子を覆って絶縁性接着剤を塗布する工程と、 7. In the method of mounting a semiconductor chip on a substrate by flip chip mounting, Applying an insulating adhesive covering the terminals of the substrate, 前記半導体チップを前記基板上に、 基板と半導体チップの対応する端子とが重 なるように位置合わせして載置する工程と、  Positioning the semiconductor chip on the substrate such that the substrate and the corresponding terminal of the semiconductor chip overlap with each other; 前記位置合わせした後に、 超音波装置の超音波へッドを半導体チップの所要部 位に押し当て、 超音波を発して前記端子群の一部を金属間接合により接続する超 音波接続工程と、  After the alignment, an ultrasonic connection step of pressing an ultrasonic head of an ultrasonic device against a required portion of the semiconductor chip, emitting ultrasonic waves, and connecting a part of the terminal group by metal-to-metal bonding, 超音波接続工程の後に、 半導体チップを加圧しつつ、 加熱して前記絶縁性接着 剤を硬化させる工程とを含むことを特徴とする半導体チップの実装方法。  Heating the semiconductor chip while pressurizing the semiconductor chip after the ultrasonic connection step to cure the insulating adhesive. 8 . 前記超音波接続工程で、 半導体チップと基板との熱膨張差により半導体チッ プに応力が生じる部位の端子群の金属間接続を行うことを特徴とする請求の範囲 7記載の半導体チップの接続方法 p 8. The semiconductor chip according to claim 7, wherein, in the ultrasonic connection step, metal-to-metal connection of a terminal group at a portion where stress occurs in the semiconductor chip due to a difference in thermal expansion between the semiconductor chip and the substrate is performed. Connection method p 9 . 前記金属間接続を行う端子の高さを、 前記圧接接合を行う端子の高さよりあ らかじめ高く形成しておくことを特徴とする請求の範囲 7または 8記載の半導体 チップの接続方法。 9. The method for connecting a semiconductor chip according to claim 7 or 8, wherein the height of the terminal for performing the metal-to-metal connection is formed higher than the height of the terminal for performing the pressure welding. .
PCT/JP2001/004089 2001-05-16 2001-05-16 Mounting structure and mounting method for semiconductor chip Ceased WO2002093638A1 (en)

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JPH09232506A (en) * 1996-02-20 1997-09-05 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JPH10303249A (en) * 1997-04-28 1998-11-13 Nec Kansai Ltd Semiconductor device
JP2000353766A (en) * 1999-04-06 2000-12-19 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
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JPH0964101A (en) * 1995-08-25 1997-03-07 Hitachi Ltd Semiconductor integrated circuit device and manufacturing method thereof
JPH09232506A (en) * 1996-02-20 1997-09-05 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JPH10303249A (en) * 1997-04-28 1998-11-13 Nec Kansai Ltd Semiconductor device
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JP2000353766A (en) * 1999-04-06 2000-12-19 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009176938A (en) * 2008-01-24 2009-08-06 Denso Corp Method for manufacturing semiconductor device

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