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JP2002118147A - Method of mounting semiconductor chip on printed wiring board and mounting sheet used for carrying out the method - Google Patents

Method of mounting semiconductor chip on printed wiring board and mounting sheet used for carrying out the method

Info

Publication number
JP2002118147A
JP2002118147A JP2000310210A JP2000310210A JP2002118147A JP 2002118147 A JP2002118147 A JP 2002118147A JP 2000310210 A JP2000310210 A JP 2000310210A JP 2000310210 A JP2000310210 A JP 2000310210A JP 2002118147 A JP2002118147 A JP 2002118147A
Authority
JP
Japan
Prior art keywords
semiconductor chip
mounting sheet
bump electrode
thermosetting resin
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000310210A
Other languages
Japanese (ja)
Inventor
Kunio Nishihara
邦夫 西原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Chemicals Inc
Original Assignee
Mitsui Chemicals Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Chemicals Inc filed Critical Mitsui Chemicals Inc
Priority to JP2000310210A priority Critical patent/JP2002118147A/en
Publication of JP2002118147A publication Critical patent/JP2002118147A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Abstract

(57)【要約】 【課題】 工程が単純で、コストが掛らず、しかも半導
体チップのバンプ電極とプリント配線基板の端子部との
接続不良等の問題を生じることのない新規な半導体チッ
プ実装方法及びその方法の実施に用いる装着用シートを
提供する 【解決手段】 本発明方法は、合成樹脂フィルム（２−
２）の一方の面に、バンプ電極の高さと同一程度の厚み
の熱硬化性樹脂層（２−１）を有する半導体チップ装着
用シート（２）を製造し、これを半導体ウエハー（１）
のバンプ電極面に圧着した状態で、半導体ウエハーの裏
面を研削し、然る後、この半導体ウエハーを、上記装着
用シート（２）が圧着されたままの状態で個片の半導体
チップ（１Ｐ）にダイシングし、得られた半導体チップ
（１Ｐ）のバンプ電極面に圧着されている装着用シート
の合成樹脂フィルム（２−２）を引き剥がした上で、半
導体チップのバンプ電極（１−２）が、プリント配線基
板(3)の端子部(3-2)に正しく対面、接触するよう位置決
めして、それらを互いに接合すると共に、熱硬化性樹脂
（２−１）を加熱硬化させることを特徴とする。 PROBLEM TO BE SOLVED: To provide a novel semiconductor chip mounting which has a simple process, is inexpensive, and does not cause a problem such as poor connection between a bump electrode of a semiconductor chip and a terminal portion of a printed wiring board. The present invention provides a method and a mounting sheet used for carrying out the method.
2) A semiconductor chip mounting sheet (2) having a thermosetting resin layer (2-1) having a thickness approximately equal to the height of a bump electrode on one surface is manufactured, and this is mounted on a semiconductor wafer (1).
The back surface of the semiconductor wafer is ground in a state in which the semiconductor wafer is pressed against the bump electrode surface, and then the semiconductor wafer is separated into individual semiconductor chips (1P) while the mounting sheet (2) is kept pressed. After the synthetic resin film (2-2) of the mounting sheet pressed to the bump electrode surface of the obtained semiconductor chip (1P) is peeled off, the bump electrode (1-2) of the semiconductor chip is peeled off. However, it is characterized in that it is positioned so as to correctly face and contact the terminal portion (3-2) of the printed wiring board (3), and they are joined to each other, and the thermosetting resin (2-1) is cured by heating. And

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップをプ
リント配線基板に装着する方法及びその方法の実施に用
いる半導体チップ装着用シートに関する．BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor chip on a printed wiring board and a semiconductor chip mounting sheet used for carrying out the method.

【０００２】[0002]

【従来の技術】従来、ＭＰＵやゲートアレー等に用いる
多ピンのＬＳＩパッケージをプリント配線基板に実装す
る場合には、半導体チップの接続パッド部に共晶ハン
ダ、高温ハンダ、金等から成るバンプ電極を形成し、所
謂フェースダウン方式により、それらのバンプ電極をプ
リント配線基板上の相対応する端子部に対面、接触さ
せ、溶融／拡散接合するフリップチップ実装方法が採用
されてきた。然し、この方法によるときは、温度の周期
的変動を受けたとき、半導体チップとプリント配線基板
の熱膨張係数の違いにより接合部が破断する恐れがある
ため、フェースダウンで接続された半導体チップのバン
プ電極が設けられた面全体と、相対向するプリント配線
基板の間の間隙に液状の熱硬化性樹脂（アンダーフィル
材）を注入、硬化させ、バンプ接合部全面をプリント配
線基板に接合してバンプ電極に集中する熱応力を分散さ
せ、破断を防止する方法が提案されている。然しなが
ら、フリップチップ実装における半導体チップとプリン
ト配線基板の間の空隙は４０〜２００μｍと小さく、そ
のためアンダーフィル材をボイドなく含浸させる工程に
は相当の時間が掛ること、及び、アンダーフィル材のロ
ット間の粘度管理が煩雑なこと等の問題がある。2. Description of the Related Art Conventionally, when a multi-pin LSI package used for an MPU, a gate array, or the like is mounted on a printed wiring board, bump electrodes made of eutectic solder, high-temperature solder, gold, or the like are provided on connection pads of a semiconductor chip. And a flip-chip mounting method in which the bump electrodes are brought into contact with the corresponding terminal portions on the printed wiring board by a so-called face-down method, and are fused / diffusion-bonded. However, according to this method, when the semiconductor chip and the printed wiring board are subjected to periodic fluctuations in temperature, the junction may be broken due to a difference in thermal expansion coefficient between the semiconductor chip and the printed wiring board. Liquid thermosetting resin (underfill material) is injected into the gap between the entire surface on which the bump electrodes are provided and the opposing printed wiring board and cured, and the entire bump joint is joined to the printed wiring board. There has been proposed a method of dispersing thermal stress concentrated on a bump electrode to prevent breakage. However, the gap between the semiconductor chip and the printed wiring board in flip-chip mounting is as small as 40 to 200 μm, so that the step of impregnating the underfill material without voids takes a considerable amount of time, and the lot of the underfill material between lots. There is a problem that the viscosity management is complicated.

【０００３】この解決方法としてシート状の熱硬化性樹
脂或いは熱可塑性樹脂を半導体チップとプリント配線基
板の間に挟み、熱圧着する技術が、例えば、特開平９−
２１３７４１号、特開平１０−２４２２０８号、特開平
１０−２７０４９７号などにより提案されている。然し
ながら、特開平９−２１３７４１号の技術は、別途封止
材によりバンプ部を囲むように封止部を設ける工程が必
要であり、工程が煩雑になると同時にボイドの発生を完
全に回避することができないという問題がある。又、特
開平１０−２４２２０８号の提案では、アンダーフィル
樹脂の位置合わせが必要であり、場所によりアンダーフ
ィル樹脂量の過不足が発生したり、逃げ穴によるボイド
発生の可能性があることが否めない。又更に、特開平１
０−２７０４９７号では、絶縁接着フィルムに半導体チ
ップのバンプ電極を食い込ませてプリント配線基板の端
子部に接続させているため、バンプ電極先端には絶縁接
着フィルムの被膜が残存し、接続の信頼性を損ねること
があるなど、工程の面、信頼性の面より問題がある。
又、近年、半導体パッケージの薄型化の要求拡大によ
り、半導体チップも薄く研削されることが通常に行われ
ている。その目的のため、従来、加工されたウエハーの
バンプ電極面にバックグラインドテープを圧着し、ウエ
ハーの裏面を研削した後、該テープを剥がし、ダイシン
グにより個片化し接合を行うという煩雑な工程を経て加
工されている。更に研削された薄板化ウエハーの搬送や
ハンドリンの際に破損することが多いという問題も生じ
ている。As a solution to this problem, a technique of sandwiching a sheet-like thermosetting resin or thermoplastic resin between a semiconductor chip and a printed wiring board and thermocompression bonding is disclosed in, for example, Japanese Patent Application Laid-Open No.
Japanese Patent Laid-Open Nos. 213741, 10-242208 and 10-270497. However, the technique disclosed in Japanese Patent Application Laid-Open No. 9-213741 requires a step of separately providing a sealing portion so as to surround the bump portion with a sealing material, which makes the process complicated and completely avoids the generation of voids. There is a problem that can not be. Further, in the proposal of Japanese Patent Application Laid-Open No. H10-242208, it is necessary to position the underfill resin, and there is a possibility that the amount of the underfill resin may be excessive or deficient depending on the location or that voids may be generated due to relief holes. Absent. Furthermore, Japanese Patent Laid-Open No.
In Japanese Patent Application No. 0-270497, since the bump electrode of the semiconductor chip is cut into the insulating adhesive film and connected to the terminal of the printed wiring board, a coating of the insulating adhesive film remains at the tip of the bump electrode, and the connection reliability is improved. There is a problem in terms of process and reliability, for example, in some cases.
In recent years, due to the increasing demand for thinner semiconductor packages, semiconductor chips are usually ground thinly. For that purpose, conventionally, a back grinding tape is pressure-bonded to the bump electrode surface of the processed wafer, and after grinding the back surface of the wafer, the tape is peeled off, dicing is performed to separate and bond, and a complicated process is performed. It has been processed. Further, there is also a problem that the thinned wafer which is ground is often broken when being transported or handled.

【０００４】[0004]

【発明が解決しようとする課題】本発明は上記の問題を
解決するためなされたものであって、その目的とすると
ころは、工程が単純で、コストが掛らず、しかもバンプ
電極を有するウエハーの薄板化、取り扱いを容易とし、
かつ半導体チップのバンプ電極が確実にプリント配線基
板の端子部に接続され、接続不良等の問題を生じること
のない新規な半導体チップ実装方法及びその方法の実施
に用いる装着用シートを提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a wafer which has a simple process, is inexpensive, and has bump electrodes. Thinner and easier to handle,
In addition, it is an object of the present invention to provide a novel semiconductor chip mounting method in which a bump electrode of a semiconductor chip is securely connected to a terminal portion of a printed wiring board and does not cause a problem such as a connection failure, and a mounting sheet used for carrying out the method. is there.

【０００５】[0005]

【課題を解決するための手段】本発明の上記第一の目的
は、下記〔ａ〕〜〔ｇ〕のステップ、即ち、〔ａ〕合成
樹脂フィルムの一方の面に、装着すべき半導体チップの
バンプ電極の高さＨと同一程度の厚みＴを有する熱硬化
性樹脂層を設けて成る半導体チップ装着用シートを製造
するステップと、〔ｂ〕装着すべき半導体チップの母体
となる半導体ウエハーのバンプ電極が設けられた面に、
上記半導体チップ装着用シートの熱硬化性樹脂層を圧着
するステップと、〔ｃ〕半導体チップ装着用シートが圧
着された状態の半導体ウエハーの裏面を研削し、所望の
厚さにするステップと、〔ｄ〕裏面が研削された半導体
ウエハーを、半導体チップ装着用シートが圧着されたま
まの状態で個片の半導体チップにダイシングするステッ
プと、〔ｅ〕ダイシングにより得られた半導体チップの
バンプ電極面に圧着されている半導体チップ装着用シー
トの合成樹脂フィルムを引き剥がすステップと、〔ｆ〕
半導体チップのバンプ電極が、対応するプリント配線基
板上の電極に正しく対面し、接触するよう位置決めする
ステップと、〔ｇ〕半導体チップのバンプ電極を、プリ
ント配線基板上の対応する電極に接合すると共に、熱硬
化性樹脂を加熱硬化させるステップと、を含むことを特
徴とする、半導体チップをプリント配線基板に装着する
方法によって達成される。尚、ここで熱硬化性樹脂層の
厚みＴを、装着すべき半導体チップのバンプ電極の高さ
Ｈと同一程度とするということは、具体的には、（Ｈ−
Ｔ）を、±３０μｍ以内、望ましくは±１５μｍ以内と
することを意味する。この偏差（Ｈ−Ｔ）の許容限界は
実際にはバンプ電極の形状、寸法、分布密度、配置、熱
硬化性樹脂の粘度などにもよるもので特定し難いが、上
記の如くすることにより殆ど総ての半導体チップに対し
て目的を達成し得るものである。The first object of the present invention is to provide the following steps [a] to [g], that is, [a] a method of mounting a semiconductor chip to be mounted on one surface of a synthetic resin film. A step of manufacturing a semiconductor chip mounting sheet provided with a thermosetting resin layer having a thickness T about the same as the height H of the bump electrode; and [b] a bump of a semiconductor wafer serving as a base of the semiconductor chip to be mounted. On the surface where the electrodes are provided,
Pressing the thermosetting resin layer of the semiconductor chip mounting sheet, and (c) grinding the back surface of the semiconductor wafer in a state where the semiconductor chip mounting sheet is pressed, to a desired thickness; d) dicing the semiconductor wafer whose back surface has been ground into individual semiconductor chips in a state where the semiconductor chip mounting sheet is pressed, and [e] forming a bump on the bump electrode surface of the semiconductor chip obtained by dicing. Peeling off the synthetic resin film of the semiconductor chip mounting sheet that has been crimped; [f]
Positioning the bump electrodes of the semiconductor chip so as to correctly face and contact the corresponding electrodes on the printed wiring board; [g] bonding the bump electrodes of the semiconductor chip to the corresponding electrodes on the printed wiring board; And heat-curing the thermosetting resin. A method for mounting a semiconductor chip on a printed circuit board is achieved. Here, the fact that the thickness T of the thermosetting resin layer is substantially the same as the height H of the bump electrode of the semiconductor chip to be mounted is specifically defined as (H−
T) is within ± 30 μm, preferably within ± 15 μm. The allowable limit of the deviation (HT) actually depends on the shape, dimensions, distribution density, arrangement, viscosity of the thermosetting resin and the like of the bump electrode, and is difficult to specify. The objective can be achieved for all the semiconductor chips.

【０００６】本発明の第二の目的は、合成樹脂フィルム
の一方の面に、装着すべき半導体チップのバンプ電極の
高さＨと同一程度の厚みＴを有する熱硬化性樹脂層を設
けて成る、上記の半導体チップをプリント配線基板に装
着する方法の実施に用いる半導体チップ装着用シートに
よって達成される。このとき使用する合成樹脂フィルム
は、その上に積層される熱硬化性樹脂の硬化温度より低
いガラス転移温度を有するものであることが望ましい。
熱硬化性樹脂としては、半導体チップのバンプ電極とプ
リント配線基板の電極の接合温度より低い硬化温度を有
するエポキシ樹脂組成物が推奨される。又更に、そのエ
ポキシ樹脂組成物は、５０重量％以上の無機質充填材を
含むものであることが望ましい。A second object of the present invention is to provide a thermosetting resin layer having a thickness T approximately equal to the height H of a bump electrode of a semiconductor chip to be mounted on one surface of a synthetic resin film. The present invention is achieved by a semiconductor chip mounting sheet used for carrying out the method of mounting the semiconductor chip on a printed wiring board. It is desirable that the synthetic resin film used at this time has a glass transition temperature lower than the curing temperature of the thermosetting resin laminated thereon.
As the thermosetting resin, an epoxy resin composition having a curing temperature lower than the bonding temperature between the bump electrode of the semiconductor chip and the electrode of the printed wiring board is recommended. Further, the epoxy resin composition desirably contains 50% by weight or more of an inorganic filler.

【０００７】[0007]

【発明の実施の形態】以下、図面により本発明の一実施
例について説明する。図は、本発明方法の構成を示す説
明図であるが、説明を判りやすくするため、これらの図
面には、バンプ電極と、装着用シートが誇張して表示さ
れている。図１は、半導体ウエハーの構成中、本発明に
関係する部分を示す一部拡大断面図、図２は、半導体ウ
エハーのバンプ電極側のフェース面上に半導体チップ装
着用シートを貼り合わせる状態を示す一部拡大断面図、
図３は、貼り合せ終了時の状態を示す一部拡大断面図、
図４は、半導体ウエハーの裏面を研削した状態を示す一
部拡大断面図、図５は、ダイシングにより個片半導体チ
ップとした状態を示す一部拡大断面図、図６は、貼り合
せた半導体チップ装着用シートの合成樹脂フィルムを引
き剥がす状態を示す一部拡大断面図、図７は、合成樹脂
フィルムを完全に引き剥がした状態を示す一部拡大断面
図、図８は、図７に示された半導体チップをフェースダ
ウン方式によりプリント配線基板に実装した状態を示す
一部拡大断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The drawings are explanatory views showing the configuration of the method of the present invention, but in order to make the description easier to understand, these drawings show bump electrodes and a mounting sheet in an exaggerated manner. FIG. 1 is a partially enlarged cross-sectional view showing a portion related to the present invention in a configuration of a semiconductor wafer, and FIG. 2 shows a state in which a semiconductor chip mounting sheet is bonded on a face surface of a semiconductor wafer on a bump electrode side. Partly enlarged sectional view,
FIG. 3 is a partially enlarged cross-sectional view showing a state at the time of completion of bonding.
FIG. 4 is a partially enlarged sectional view showing a state where the back surface of the semiconductor wafer is ground, FIG. 5 is a partially enlarged sectional view showing a state where individual semiconductor chips are formed by dicing, and FIG. 6 is a bonded semiconductor chip. FIG. 7 is a partially enlarged sectional view showing a state in which the synthetic resin film of the mounting sheet is peeled off, FIG. 7 is a partially enlarged sectional view showing a state in which the synthetic resin film is completely peeled off, and FIG. 8 is shown in FIG. FIG. 4 is a partially enlarged cross-sectional view showing a state where the semiconductor chip is mounted on a printed wiring board by a face-down method.

【０００８】而して、これらの図中、１は半導体ウエハ
ー、１−１はその基板、１−２はバンプ電極であり、１
Ｐは半導体ウエハー１をダイシングにより個片化した半
導体チップである。２は、合成樹脂フィルム２−２の一
方の面に熱硬化性樹脂層２−１を形成して成る半導体チ
ップ装着用シート（以下、単に「装着用シート」とも言
う。）、３はプリント配線基板であり、合成樹脂製の基
板３−１の上に、半導体チップ１Ｐのバンプ電極１−２
に対応する端子部３−２を具備する。In these figures, 1 is a semiconductor wafer, 1-1 is its substrate, 1-2 is a bump electrode, and 1 is a semiconductor wafer.
P is a semiconductor chip obtained by dicing the semiconductor wafer 1 by dicing. Reference numeral 2 denotes a semiconductor chip mounting sheet (hereinafter, also simply referred to as “mounting sheet”) formed by forming a thermosetting resin layer 2-1 on one surface of a synthetic resin film 2-2. A bump electrode 1-2 of a semiconductor chip 1P on a synthetic resin substrate 3-1.
Are provided.

【０００９】而して、本発明方法により、プリント配線
基板３上に半導体チップ１Ｐを実装する場合には、先
ず、前記ステップ〔ａ〕に記載の如く、合成樹脂フィル
ム２−２の一方の面に熱硬化性樹脂層２−１を形成して
成る半導体チップ装着用シート２を製造する。その場合
の熱硬化性樹脂層２−１の厚さＴは、この装着用シート
２を半導体ウエハー１に貼り付けた際、バンプ電極１−
２の先端が熱硬化性樹脂層２−１を貫通して合成樹脂フ
ィルム２−２に接触すると共に、その貼着領域の周縁に
適量の熱硬化性樹脂がはみ出し、貼着面にボイドが残ら
ないように定める。熱硬化性樹脂層２−１の厚さＴの上
限及び下限は、厳密には半導体ウエハー１（半導体チッ
プ１Ｐ）に形成されたバンプ電極１−２の寸法、形状、
数、全体積及び分布状況、並びに、熱硬化性樹脂層の硬
度などにより定められるが、一般に用いられている半導
体チップに対しては、概ねそのバンプ電極１−２の高さ
Ｈと同一とすると上記の条件を成就することができる。When the semiconductor chip 1P is mounted on the printed wiring board 3 by the method of the present invention, first, as described in the step [a], one side of the synthetic resin film 2-2 is set. The semiconductor chip mounting sheet 2 is formed by forming a thermosetting resin layer 2-1 on the substrate. In this case, the thickness T of the thermosetting resin layer 2-1 is such that when the mounting sheet 2 is attached to the semiconductor wafer 1, the bump electrode 1-
2 penetrates the thermosetting resin layer 2-1 and comes into contact with the synthetic resin film 2-2, and an appropriate amount of thermosetting resin protrudes around the periphery of the bonding area, leaving voids on the bonding surface. It is determined not to be. Strictly speaking, the upper and lower limits of the thickness T of the thermosetting resin layer 2-1 are determined by the size, shape, and the like of the bump electrode 1-2 formed on the semiconductor wafer 1 (semiconductor chip 1P).
It is determined by the number, the total volume and the distribution state, the hardness of the thermosetting resin layer, and the like. For a generally used semiconductor chip, it is assumed that the height is substantially equal to the height H of the bump electrode 1-2. The above conditions can be fulfilled.

【００１０】量産プラントにおいては、熱硬化性樹脂層
２−１の厚さＴを常時完全にバンプ電極１−２の高さＨ
と同一値に保持することは困難である。然しながら、熱
硬化性樹脂層２−１の厚さＴを、バンプ電極１−２の高
さＨの±３０μｍ以内とすれば、殆ど全ての半導体チッ
プ１Ｐに対して良好な結果が得られることが判明した。
熱硬化性樹脂層２−１の厚さＴの更に望ましい値は、バ
ンプ電極１−２の高さＨ±１５μｍ以内である。熱硬化
性樹脂層の厚みＴがこの範囲内にあると、装着用シート
２の圧着が容易であり、適切な圧着力でバンプ電極の先
端を合成樹脂フィルム２−２に接触させることができ、
かつ、貼着面にボイドが残らず、貼着領域の周縁にはみ
出す熱硬化性樹脂も適量に留まる。In a mass production plant, the thickness T of the thermosetting resin layer 2-1 is always completely set to the height H of the bump electrode 1-2.
It is difficult to keep the same value as However, if the thickness T of the thermosetting resin layer 2-1 is within ± 30 μm of the height H of the bump electrode 1-2, good results can be obtained for almost all the semiconductor chips 1P. found.
A more desirable value of the thickness T of the thermosetting resin layer 2-1 is within a height H ± 15 μm of the bump electrode 1-2. When the thickness T of the thermosetting resin layer is within this range, the pressing of the mounting sheet 2 is easy, and the tip of the bump electrode can be brought into contact with the synthetic resin film 2-2 with an appropriate pressing force.
In addition, no void remains on the sticking surface, and an appropriate amount of the thermosetting resin protruding to the peripheral edge of the sticking region also remains.

【００１１】熱硬化性樹脂層の厚みＴが、バンプ電極の
高さＨ＋３０μｍを超えると、装着用シート２をチップ
に圧着した際、バンプ電極が熱硬化性樹脂層を貫通せ
ず、プリント配線基板の端子部との接続が不充分となる
恐れがある上、貼着領域の周縁にはみ出す熱硬化性樹脂
量が過大になり不都合を生じる。又逆に、その厚みＴ
が、Ｈ−３０μｍ以下となると、半導体チップとプリン
ト配線基板との間隙を熱硬化性樹脂により十分に埋める
ことが出来ず、ボイドの発生する恐れが生じる。When the thickness T of the thermosetting resin layer exceeds the height H + 30 μm of the bump electrode, when the mounting sheet 2 is pressed against the chip, the bump electrode does not penetrate the thermosetting resin layer, and the printed wiring board does not penetrate. In addition, there is a possibility that the connection with the terminal portion may be insufficient, and the amount of the thermosetting resin protruding to the peripheral edge of the sticking area becomes excessive, which causes inconvenience. Conversely, its thickness T
However, if the thickness is less than or equal to 30 μm, the gap between the semiconductor chip and the printed wiring board cannot be sufficiently filled with the thermosetting resin, and there is a possibility that voids may be generated.

【００１２】熱硬化性樹脂層２−１を構成するエポキシ
樹脂組成物としては、単官能エポキシ樹脂、ビスフェノ
ールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹
脂、フェノールノボラック型エポキシ樹脂、クレゾール
ノボラック型エポキシ樹脂等の多官能エポキシ樹脂及び
これらの臭素化物の１種又は２種以上から成るエポキシ
樹脂と、多価フェノール化合物、尿素誘導体、アミン化
合物、イミダゾール化合物、変性アミン化合物、変性イ
ミダゾール化合物、酸無水物の１種又は２種以上を混合
して得た硬化剤より成る組成物が推奨される。The epoxy resin composition constituting the thermosetting resin layer 2-1 includes a monofunctional epoxy resin, a bisphenol A epoxy resin, a bisphenol F epoxy resin, a phenol novolak epoxy resin, a cresol novolak epoxy resin, and the like. And polyepoxy resins comprising one or more of these bromides; and polyhydric phenol compounds, urea derivatives, amine compounds, imidazole compounds, modified amine compounds, modified imidazole compounds, and acid anhydrides. A composition comprising a curing agent obtained by mixing seeds or two or more is recommended.

【００１３】この組成物には、結晶シリカ、溶融シリ
カ、アルミナ、窒化アルミ、窒化ボロン、窒化珪素、マ
グネシア、マグネシウムシリケートなどの無機質充填
材、ゴム成分、粘性調整剤、難燃剤などを加えても良
い。無機質充填材の添加量は、５０重量％以上が好まし
く、それ以下では熱膨張係数の低減効果、熱伝導効果が
乏しくなり、信頼性が低下する。尚、この組成物として
は、半導体チップのバンプ電極とプリント配線基板の電
極との接合温度より低い硬化温度を有するものが強く推
奨される。硬化温度が接合温度より高いと、接合後に接
合温度より高い温度での熱処理が必要となるので、工程
が煩雑となるばかりでなく、接合部の信頼性の低下を招
くからである。このエポキシ樹脂組成物は、通常、溶剤
にて適正な粘度に調整され、適宜の合成樹脂フィルムに
塗布、乾燥せしめられ、熱硬化性樹脂層を形成する。The composition may contain inorganic fillers such as crystalline silica, fused silica, alumina, aluminum nitride, boron nitride, silicon nitride, magnesia, magnesium silicate, etc., rubber components, viscosity modifiers, flame retardants, etc. good. The addition amount of the inorganic filler is preferably 50% by weight or more, and if it is less than that, the effect of reducing the thermal expansion coefficient and the effect of heat conduction are poor, and the reliability is reduced. It is strongly recommended that this composition has a curing temperature lower than the bonding temperature between the bump electrode of the semiconductor chip and the electrode of the printed wiring board. If the curing temperature is higher than the bonding temperature, a heat treatment at a temperature higher than the bonding temperature is required after the bonding, which not only complicates the process but also lowers the reliability of the bonded portion. This epoxy resin composition is usually adjusted to an appropriate viscosity with a solvent, applied to an appropriate synthetic resin film, and dried to form a thermosetting resin layer.

【００１４】合成樹脂フィルム２−２は、単に熱硬化性
樹脂層のキャリアーに過ぎないので、材質などには特段
の限定はないが、上記熱硬化性樹脂組成物の硬化温度よ
り低いガラス転移温度を有する熱可塑性樹脂、例えば、
ポリエチレン、ポリプロピレン等のポリオレフィン、エ
チレン酢酸ビニル共重合体、エチレン−アルキルアクリ
レート共重合体、ポリエステル、ポリ塩化ビニール、ポ
リ塩化ビニリデン、ポリウレタン、ポリアミド、ポリア
ミドイミド、ポリエーテルイミド、ポリスルホン、ポリ
エーテルスルホン、メチルペンテンコポリマー等により
作製された熱可塑性のフィルムが採用できる。フィルム
の厚さは特に限定しないが、通常３０〜５００μｍの厚
さで使用される。The synthetic resin film 2-2 is merely a carrier of the thermosetting resin layer, and thus there is no particular limitation on the material and the like, but the glass transition temperature is lower than the curing temperature of the thermosetting resin composition. A thermoplastic resin having, for example,
Polyolefins such as polyethylene and polypropylene, ethylene vinyl acetate copolymer, ethylene-alkyl acrylate copolymer, polyester, polyvinyl chloride, polyvinylidene chloride, polyurethane, polyamide, polyamideimide, polyetherimide, polysulfone, polyethersulfone, methyl A thermoplastic film made of a pentene copolymer or the like can be used. Although the thickness of the film is not particularly limited, it is usually used at a thickness of 30 to 500 μm.

【００１５】このようにして作製された装着用シート２
は、図２及び図３に示すように、その熱硬化性樹脂層２
−１を半導体ウエハー１のバンプ電極が設けられている
面に向けて貼り合わされる。貼り合わせる方法は特に限
定されないが通常ロールラミネーション、プレスラミネ
ーションにより行われる。貼り合せは、硬化前の熱硬化
性樹脂層の軟化温度以上、硬化温度以下にて行われる。
従って、この段階では熱硬化性樹脂層２−１は硬化前の
状態である。この貼り合せ工程により、バンプ電極１−
２は、熱硬化性樹脂層２−１を貫通し、それらの先端が
樹脂フィルム２−２に接触し、場合によってはその表面
を強く押圧するようになる。The mounting sheet 2 thus manufactured
Is the thermosetting resin layer 2 as shown in FIGS.
-1 is bonded to the surface of the semiconductor wafer 1 on which the bump electrodes are provided. The bonding method is not particularly limited, but is usually performed by roll lamination or press lamination. The bonding is performed at a temperature equal to or higher than the softening temperature of the thermosetting resin layer before hardening and equal to or lower than the curing temperature.
Therefore, at this stage, the thermosetting resin layer 2-1 is in a state before being cured. By this bonding step, the bump electrode 1-
Numeral 2 penetrates the thermosetting resin layer 2-1 and their ends come into contact with the resin film 2-2, and in some cases, strongly press the surface thereof.

【００１６】次に、図４に示す如く半導体ウエハー１の
裏面を研削し所望の厚さとする。研削の方法は特に限定
されない。通常５００〜１０００μｍの厚さを１００〜
６００μｍまで研削する。研削後、ダイシングソー、レ
ーザースクライブ等を用いた通常のダイシング工程を経
て図５に示される個片の半導体チップ１Ｐが得られる。
次に、図６に示す如くして装着用シート２の樹脂フィル
ム２−２を引き剥がす。図７は、樹脂フィルムが完全に
取り除かれた状態を示す。このとき、バンプ電極１−２
の先端は、熱硬化性樹脂層２−１の表面より露出した状
態となっている。最後に、図８に示す如く、フェースダ
ウン方式で、半導体チップ１Ｐの各バンプ電極１−２
を、プリント配線基板３のそれぞれ対応する端子部３−
２と正しく対面、接触させるよう位置決めし、熱圧によ
り、更には必要に応じ超音波振動を与えることにより接
合を行う。熱硬化性樹脂層２−１の樹脂組成物は、接合
時発生する熱により軟化し、然る後、硬化し、半導体チ
ップ１Ｐとプリント配線基板３の間に強固な硬化樹脂層
を形成する。このように接合した後に、必要に応じて熱
処理を加えても構わないが、その場合、接合温度より低
い温度であることが必要である。Next, as shown in FIG. 4, the back surface of the semiconductor wafer 1 is ground to a desired thickness. The grinding method is not particularly limited. Normally, a thickness of 500 to 1000 μm
Grind to 600 μm. After the grinding, the individual semiconductor chips 1P shown in FIG. 5 are obtained through a normal dicing process using a dicing saw, a laser scribe, or the like.
Next, the resin film 2-2 of the mounting sheet 2 is peeled off as shown in FIG. FIG. 7 shows a state in which the resin film has been completely removed. At this time, the bump electrodes 1-2
Is exposed from the surface of the thermosetting resin layer 2-1. Finally, as shown in FIG. 8, each bump electrode 1-2 of the semiconductor chip 1P is face-down type.
To the corresponding terminal portions 3-3 of the printed wiring board 3.
Positioning is performed so as to correctly face and come into contact with 2, and bonding is performed by applying heat and pressure and, if necessary, ultrasonic vibration. The resin composition of the thermosetting resin layer 2-1 is softened by the heat generated at the time of joining, and then hardens to form a strong cured resin layer between the semiconductor chip 1P and the printed wiring board 3. After joining in this manner, heat treatment may be applied as necessary, but in this case, the temperature must be lower than the joining temperature.

【００１７】以下、本発明方法により、実際に市販され
ている半導体チップを、プリント基板に実装する実施例
を示す。 〔実施例１〕フェノールノボラック型エポキシ樹脂、ビ
スフェノールＦ型エポキシ樹脂、フェノールノボラック
樹脂、尿素誘導体からなるエポキシ樹脂組成物１００重
量部に、球状アルミナ２６０重量部と溶剤を加え混練分
散し、得られた硬化温度１６０℃のエポキシ樹脂組成物
を、ガラス転移温度−２０℃、厚み１００μｍのエチレ
ン酢酸ビニル共重合体フィルムに塗付、乾燥し、半導体
チップ装着用シートを得た。熱硬化性樹脂層の厚みは９
０μｍであった。Hereinafter, an embodiment of mounting a commercially available semiconductor chip on a printed circuit board by the method of the present invention will be described. [Example 1] 260 parts by weight of spherical alumina and a solvent were added to 100 parts by weight of an epoxy resin composition comprising a phenol novolak type epoxy resin, a bisphenol F type epoxy resin, a phenol novolak resin, and a urea derivative, and kneaded and dispersed to obtain. The epoxy resin composition having a curing temperature of 160 ° C. was applied to an ethylene vinyl acetate copolymer film having a glass transition temperature of −20 ° C. and a thickness of 100 μm and dried to obtain a semiconductor chip mounting sheet. The thickness of the thermosetting resin layer is 9
It was 0 μm.

【００１８】この装着用シートを、共晶ハンダからなる
高さ１００μｍのバンプ電極が１００個所に形成された
半導体チップの原盤となる半導体ウエハーのバンプ電極
面に、プレスにより貼り付けを行った。貼り付け温度は
８０℃であった。その後、バックグラインド装置により
ウエハー厚みを６００μｍから２００μｍまで研削を行
った。続いてダイシングテープを裏面に貼り、レーザー
スクライバーを用いて個片の半導体チップに切断した。
この間の作業において、ウエハーのクラック、破損は無
かった。得られた個片の半導体チップから装着用シート
のエチレン酢酸ビニル共重合体フィルムを剥し、バンプ
電極の先端を露出させ、バンプ電極とプリント配線基板
の端子部の位置合わせを行い、２２０℃で２分間加熱加
圧を行い、バンプ電極と端子部を接合すると同時に、熱
硬化性樹脂層を硬化させた。接合後、更に１８０℃にて
１時間熱処理し熱硬化性樹脂の硬化を完了させた。この
半導体チップのバンプ電極とプリント配線基板の接合は
１００箇所とも良好であり、−５５℃と１２５℃の温度
サイクル試験１０００サイクル後も接続部の破断は生じ
なかった。This mounting sheet was bonded by pressing to a bump electrode surface of a semiconductor wafer serving as a master of a semiconductor chip having 100 μm-high bump electrodes made of eutectic solder formed at 100 locations. The sticking temperature was 80 ° C. Thereafter, the wafer was ground from a thickness of 600 μm to 200 μm using a back grinding apparatus. Subsequently, a dicing tape was attached to the back surface, and cut into individual semiconductor chips using a laser scriber.
During the operation during this time, there was no crack or breakage of the wafer. The ethylene vinyl acetate copolymer film of the mounting sheet is peeled off from the obtained individual semiconductor chips, the tips of the bump electrodes are exposed, the bump electrodes and the terminals of the printed wiring board are aligned, and the temperature is adjusted to 220 ° C. for 2 hours. The thermosetting resin layer was cured at the same time when the bump electrode and the terminal were joined by heating and pressing for minutes. After joining, heat treatment was further performed at 180 ° C. for 1 hour to complete the curing of the thermosetting resin. The bonding between the bump electrode of the semiconductor chip and the printed wiring board was good at all 100 points, and the connection portion did not break even after 1000 cycles of the temperature cycle test at −55 ° C. and 125 ° C.

【００１９】〔実施例２〕クレゾールノボラック型エポ
キシ樹脂、ビスフェノールＡ型エポキシ樹脂、酸無水
物、窒化ボロン、溶剤から成る硬化温度１８０℃の熱硬
化性樹脂組成物を、ガラス転移温度７０℃、厚さ５０μ
ｍのポリエステルフィルムに塗布、乾燥し、半導体チッ
プ装着用シートを得た。熱硬化性樹脂層の厚みは１６５
μｍであった。この装着用シートを、金からなる高さ１
２０μｍのバンプ電極が１００箇所に形成された半導体
チップの原盤となる半導体ウエハーのバンプ電極面に、
熱ロールによるラミネートにより１２０℃で貼り付けを
行った。その後、バックグラインド装置によりウエハー
厚みを８００μｍから６００μｍまで研削を行った。続
いてダイシングテープを裏面に貼り、ダイシングソーを
用いて個片の半導体チップに切断した。得られた個片の
半導体チップから、装着用シートのポリエステルフィル
ムを引き剥し、バンプ電極の先端を露出させ、バンプ電
極とプリント配線基板の端子部の位置合わせを行い、３
００℃にて３０秒間超音波振動を与えつつ加熱加圧を行
い、バンプ電極と端子部を接合すると同時に熱硬化性樹
脂層を硬化させた。この半導体チップのバンプ電極とプ
リント配線基板の接合は１００箇所とも良好であり、−
５５℃と１２５℃の温度サイクル試験１０００サイクル
後も接続部の破断は生じなかった。Example 2 A thermosetting resin composition comprising a cresol novolak type epoxy resin, a bisphenol A type epoxy resin, an acid anhydride, boron nitride and a solvent at a curing temperature of 180 ° C. was prepared by mixing a glass transition temperature of 70 ° C. 50μ
m, and dried by drying to obtain a semiconductor chip mounting sheet. The thickness of the thermosetting resin layer is 165
μm. This mounting sheet is made of gold and has a height of 1.
On a bump electrode surface of a semiconductor wafer serving as a master of a semiconductor chip having 20 μm bump electrodes formed at 100 locations,
Pasting was performed at 120 ° C. by lamination using a hot roll. Thereafter, the wafer was ground from a thickness of 800 μm to 600 μm using a back grinding apparatus. Subsequently, a dicing tape was attached to the back surface, and cut into individual semiconductor chips using a dicing saw. The polyester film of the mounting sheet is peeled off from the obtained individual semiconductor chips, the tips of the bump electrodes are exposed, and the bump electrodes and the terminals of the printed wiring board are aligned.
Heat and pressure were applied while applying ultrasonic vibration at 00 ° C. for 30 seconds to join the bump electrodes and the terminal portions and simultaneously cure the thermosetting resin layer. The bonding between the bump electrodes of the semiconductor chip and the printed wiring board was good at all 100 points.
After 1000 cycles of the temperature cycle test at 55 ° C. and 125 ° C., the connection portion did not break.

【００２０】〔比較例１〕実施例１にて用いた熱硬化性
樹脂組成物をシート状に成形し、実施例１で使用した個
片の半導体チップとプリント配線基板の間に直接挟み、
８０℃にて加熱圧した後、２２０℃に昇温し接合を行っ
た。半導体チップのバンプ電極とプリント配線基板の接
続部は、１７箇所が不良となった。[Comparative Example 1] The thermosetting resin composition used in Example 1 was molded into a sheet, and directly sandwiched between the individual semiconductor chips used in Example 1 and the printed wiring board.
After heating and pressing at 80 ° C., the temperature was raised to 220 ° C. to perform joining. In the connection portion between the bump electrode of the semiconductor chip and the printed wiring board, 17 portions were defective.

【００２１】〔比較例２〕実施例１にて使用した厚さ６
００μm の半導体ウエハーのバンプ電極面にバックグラ
インドテープを圧着した上でウエハーの裏面を２００μ
m まで研削し、その後上記バックグラインドテープを剥
がした後、ダイシングテープを裏面に貼り、ダイシング
ソーにて個片の半導体チップに切断した。この間の作業
ににおいて５０枚のウエハー加工にて１枚のウエハーに
クラックが生じた。得られた個片の半導体チップとプリ
ント配線基板の間に、実施例１で用いた熱硬化性樹脂組
成物をシート状に成形したものを直接挟み８０℃にて加
熱圧した後、２２０℃に昇温し接合を行った。半導体チ
ップのバンプ電極とプリント配線基板の接続部は、１７
箇所が不良となった。Comparative Example 2 Thickness 6 used in Example 1
A back grinding tape is pressed on the bump electrode surface of a 00 μm semiconductor wafer, and the back surface of the wafer is
m, and then the above-mentioned back grinding tape was peeled off. Then, a dicing tape was attached to the back surface, and cut into individual semiconductor chips with a dicing saw. During the operation during this time, cracks occurred in one wafer by processing 50 wafers. A sheet formed from the thermosetting resin composition used in Example 1 was directly sandwiched between the obtained individual semiconductor chip and the printed wiring board, and heated and pressed at 80 ° C., and then heated to 220 ° C. The temperature was raised and bonding was performed. The connection between the bump electrode of the semiconductor chip and the printed wiring board is 17
The part became defective.

【００２２】[0022]

【発明の効果】本発明は叙上の如く構成されるから、本
発明によるときは、工程が単純で、コストが掛らず、し
かも半導体チップのバンプ電極が確実にプリント配線基
板の端子部に接続され、接続不良等の問題を生じること
のない新規な半導体チップ実装方法及びその方法の実施
に用いる装着用シートを提供することができる。尚、本
発明は上記実施例に限定されるものでなく、その目的の
範囲内において上記の説明から当業者が容易に想到し得
るすべての変更実施例を包摂するものである。Since the present invention is constructed as described above, according to the present invention, the process is simple, the cost is low, and the bump electrodes of the semiconductor chip are securely connected to the terminal portions of the printed wiring board. It is possible to provide a novel semiconductor chip mounting method that is connected and does not cause a problem such as a connection failure, and a mounting sheet used for implementing the method. It should be noted that the present invention is not limited to the above embodiments, but encompasses all modified embodiments that can be easily conceived by those skilled in the art from the above description within the scope of the purpose.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 半導体ウエハーの構成中、本発明に関係する
部分を示す一部拡大断面図である。FIG. 1 is a partially enlarged sectional view showing a portion related to the present invention in a configuration of a semiconductor wafer.

【図２】 半導体ウエハーのバンプ電極側のフェース面
上に半導体チップ装着用シートを貼り合わせる状態を示
す一部拡大断面である。FIG. 2 is a partially enlarged cross-sectional view showing a state in which a semiconductor chip mounting sheet is bonded on a face surface of a semiconductor wafer on a bump electrode side.

【図３】 貼り合せ終了時の状態を示す一部拡大断面図
である。FIG. 3 is a partially enlarged sectional view showing a state at the time of completion of bonding.

【図４】 半導体ウエハーの裏面研削を行った状態を示
す一部拡大断面である。FIG. 4 is a partially enlarged cross-sectional view showing a state where the back surface of the semiconductor wafer is ground.

【図５】 ダイシングにより得られた個片の半導体チッ
プの状態を示す一部拡大図である。FIG. 5 is a partially enlarged view showing a state of an individual semiconductor chip obtained by dicing.

【図６】 貼り合せた半導体チップ装着用シートの合成
樹脂フィルムを引き剥がす状態を示す一部拡大断面図で
ある。FIG. 6 is a partially enlarged sectional view showing a state in which the synthetic resin film of the bonded semiconductor chip mounting sheet is peeled off.

【図７】 合成樹脂フィルムを完全に引き剥がした状態
を示す一部拡大断面図である。FIG. 7 is a partially enlarged sectional view showing a state where the synthetic resin film is completely peeled off.

【図８】 図７に示された半導体チップをプリント配線
基板に実装した状態を示す一部拡大断面図である。8 is a partially enlarged cross-sectional view showing a state where the semiconductor chip shown in FIG. 7 is mounted on a printed wiring board.

【符号の説明】[Explanation of symbols]

１ 半導体ウエハー １Ｐ 半導体チップ １−１ 基板 １−２ バンプ電極 ２ 半導体チップ装着用シート ２−１ 熱硬化性樹脂層 ２−２ 合成樹脂フィルム ３ プリント配線基板 ３−１ 基板 ３−２ 端子部 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1P Semiconductor chip 1-1 Substrate 1-2 Bump electrode 2 Semiconductor chip mounting sheet 2-1 Thermosetting resin layer 2-2 Synthetic resin film 3 Printed wiring board 3-1 Substrate 3-2 Terminal part

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 下記のステップ〔ａ〕〜〔ｇ〕を含むこ
とを特徴とする、半導体チップ（１Ｐ）をプリント配線
基板（３）に装着する方法。 〔ａ〕合成樹脂フィルム（２−２）の一方の面に、装着
すべき半導体チップのバンプ電極（１−２）の高さＨと
同一程度の厚みＴを有する熱硬化性樹脂層（２−１）を
設けて成る半導体チップ装着用シート（２）を製造する
ステップ。 〔ｂ〕装着すべき半導体チップの原盤となる半導体ウエ
ハー（１）のバンプ電極（１−２）が設けられた面に、
上記半導体チップ装着用シート（２）の熱硬化性樹脂層
（２−１）を圧着するステップ。 〔ｃ〕半導体チップ装着用シート（２）が圧着された状
態の半導体ウエハー（１）の裏面を研削し、所望の厚さ
にするステップ。 〔ｄ〕裏面が研削された半導体ウエハー（１）を、半導
体チップ装着用シート（２）が圧着されたままの状態で
個片の半導体チップ（１Ｐ）にダイシングするステッ
プ。 〔ｅ〕ダイシングにより得られた半導体チップ（１Ｐ）
のバンプ電極面に圧着されている半導体チップ装着用シ
ート（２）の合成樹脂フィルム（２−２）を引き剥がす
ステップ。 〔ｆ〕半導体チップ（１Ｐ）のバンプ電極（１−２）
が、対応するプリント配線基板（３）上の端子部（３−
２）に正しく対面し、接触するよう位置決めするステッ
プ。 〔ｇ〕半導体チップ（１Ｐ）のバンプ電極（１−２）
を、プリント配線基板（３）上の対応する端子部（３−
２）に接合すると共に、熱硬化性樹脂（２−１）を加熱
硬化させるステップ。1. A method for mounting a semiconductor chip (1P) on a printed wiring board (3), comprising the following steps [a] to [g]. [A] On one surface of the synthetic resin film (2-2), a thermosetting resin layer (2-) having the same thickness T as the height H of the bump electrode (1-2) of the semiconductor chip to be mounted. A step of manufacturing a semiconductor chip mounting sheet (2) provided with 1). [B] On the surface of the semiconductor wafer (1) on which the bump electrodes (1-2) are provided as the master of the semiconductor chip to be mounted,
Pressure bonding the thermosetting resin layer (2-1) of the semiconductor chip mounting sheet (2). [C] a step of grinding the back surface of the semiconductor wafer (1) in a state where the semiconductor chip mounting sheet (2) is pressed, to a desired thickness. [D] A step of dicing the semiconductor wafer (1) whose back surface has been ground into individual semiconductor chips (1P) with the semiconductor chip mounting sheet (2) kept pressed. [E] Semiconductor chip (1P) obtained by dicing
Peeling off the synthetic resin film (2-2) of the semiconductor chip mounting sheet (2) pressed against the bump electrode surface of (2). [F] Bump electrode (1-2) of semiconductor chip (1P)
Correspond to the terminal portion (3−3) on the corresponding printed circuit board (3).
Positioning to correctly face and contact 2). [G] Bump electrode (1-2) of semiconductor chip (1P)
To the corresponding terminal portion (3-
Step of bonding to 2) and heat-curing the thermosetting resin (2-1). 【請求項２】 合成樹脂フィルム（２−２）の一方の面
に、装着すべき半導体チップのバンプ電極（１−２）の
高さＨと同一程度の厚みＴを有する熱硬化性樹脂層（２
−１）を設けて成る、請求項１に記載の半導体チップを
プリント配線基板に装着する方法の実施に用いる半導体
チップ装着用シート（２）。2. A thermosetting resin layer having a thickness T substantially equal to a height H of a bump electrode (1-2) of a semiconductor chip to be mounted on one surface of a synthetic resin film (2-2). 2
A semiconductor chip mounting sheet (2) for use in carrying out the method for mounting a semiconductor chip on a printed wiring board according to claim 1, comprising (1). 【請求項３】 合成樹脂フィルム（２−２）が、熱硬化
性樹脂（２−１）の硬化温度より低いガラス転移温度を
有する、請求項２に記載の半導体チップ装着用シート
（２）。3. The semiconductor chip mounting sheet (2) according to claim 2, wherein the synthetic resin film (2-2) has a glass transition temperature lower than the curing temperature of the thermosetting resin (2-1). 【請求項４】 熱硬化性樹脂（２−１）がエポキシ樹脂
組成物より成り、そのエポキシ樹脂組成物が、半導体チ
ップ（１Ｐ）のバンプ電極（１−２）とプリント配線基
板（３）の端子部（３−２）の接合温度より低い硬化温
度を有する、請求項２又は３に記載の半導体チップ装着
用シート（２）。4. The thermosetting resin (2-1) is made of an epoxy resin composition, and the epoxy resin composition is used for forming a bump electrode (1-2) of a semiconductor chip (1P) and a printed wiring board (3). The semiconductor chip mounting sheet (2) according to claim 2 or 3, having a curing temperature lower than a bonding temperature of the terminal portion (3-2). 【請求項５】 熱硬化性樹脂（２−１）が、５０重量％
以上の無機質充填材を含む、請求項２乃至４の何れか一
に記載の半導体チップ装着用シート（２）。5. The thermosetting resin (2-1) contains 50% by weight.
The semiconductor chip mounting sheet (2) according to any one of claims 2 to 4, comprising the above inorganic filler. 【請求項６】 熱硬化性樹脂層（２−１）の厚みＴ（単
位μｍ。以下同様。）が、装着すべき半導体チップ（１
Ｐ）のバンプ電極（１−２）の高さをＨとしたとき、Ｈ
−30≦Ｔ≦Ｈ＋30の範囲内にある、請求項２乃至５の何
れか一に記載の半導体チップ装着用シート（２）。6. The semiconductor chip (1) to be mounted has a thickness T (unit: μm; the same applies hereinafter) of the thermosetting resin layer (2-1).
When the height of the bump electrode (1-2) of P) is H, H
The semiconductor chip mounting sheet (2) according to any one of claims 2 to 5, wherein satisfies -30≤T≤H + 30.
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