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WO2002056481A2 - Systeme et procede de mise en oeuvre d'un systeme de communication sans fil au moyen d'une puce reconfigurable avec matrice reconfigurable - Google Patents

Systeme et procede de mise en oeuvre d'un systeme de communication sans fil au moyen d'une puce reconfigurable avec matrice reconfigurable Download PDF

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Publication number
WO2002056481A2
WO2002056481A2 PCT/US2001/049436 US0149436W WO02056481A2 WO 2002056481 A2 WO2002056481 A2 WO 2002056481A2 US 0149436 W US0149436 W US 0149436W WO 02056481 A2 WO02056481 A2 WO 02056481A2
Authority
WO
WIPO (PCT)
Prior art keywords
configuration
reconfigurable
communication system
reconfigurable chip
communication unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/049436
Other languages
English (en)
Other versions
WO2002056481A9 (fr
WO2002056481A3 (fr
Inventor
Daniel J. Pugh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chameleon Systems Inc
Original Assignee
Chameleon Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chameleon Systems Inc filed Critical Chameleon Systems Inc
Priority to EP01998067A priority Critical patent/EP1336248A4/fr
Priority to AU2002249827A priority patent/AU2002249827A1/en
Publication of WO2002056481A2 publication Critical patent/WO2002056481A2/fr
Publication of WO2002056481A3 publication Critical patent/WO2002056481A3/fr
Anticipated expiration legal-status Critical
Publication of WO2002056481A9 publication Critical patent/WO2002056481A9/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70707—Efficiency-related aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70707—Efficiency-related aspects
    • H04B2201/7071—Efficiency-related aspects with dynamic control of receiver resources

Definitions

  • the present invention relates to communication systems, more particularly to wireless communication systems.
  • Wireless communication systems are typically implemented using integrated circuits.
  • ASICs application-specific integrated chips
  • This is especially done for wireless communication base stations, which can be used to service a large number of users.
  • FPGAs field programmable gate arrays
  • the FPGAs have a considerable down side.
  • the size and resulting cost of the FPGAs used to implement the complex algorithms used in wireless communication systems, especially base stations, can be significant. For this reason, it is desired to have a flexible yet inexpensive solution to the implementation of a computer communication system.
  • the present invention comprises using a reconfigurable chip with a background and foreground configuration plane to implement a communication system.
  • the wireless communication system can be a wireless communication system, for example, a wireless communication base station.
  • the reconfigurable chip allows a portion of the commumcation system algorithm to be loaded into the background configuration plane while another portion of the communication system algorithm operates as configured by the foreground configuration plane.
  • the configuration in the background plane can be quickly switched into the foreground plane. This is not possible with FPGAs.
  • FPGAs require a significant amount of time (in the range of one second) for the configuration loading. While this is acceptable in many situations, for communication algorithms, such as the multiple-step frame processing used in a wireless communication base station, the configuration needs to be switched much quicker.
  • Another embodiment of the present invention comprises a method of implementing a communication system comprising the step of loading a first portion of the communication design in the reconfigurable chip; running the first portion of the reconfigurable chip, and at least during part of the running step; loading a second portion of the configuration system design in the reconfigurable chip, and running the second portion of the communication design on the reconfigurable chip.
  • reconfigurable chip allows for the communication system design to be broken down into smaller configurations. This allows, for example, a smaller reconfigurable chip having foreground and background planes to be used in a situation where a larger FPGA would otherwise be needed. This can significantly reduce the cost of the communication system unit.
  • Fig. 1 illustrates an example of a reconfigurable chip with foreground and background configuration planes which can be used with the system of the present invention.
  • Fig. 2 A illustrates a preferable implementation of the switching between the foreground and background planes.
  • Fig. 2B shows a less preferred implementation of the switching between the foreground and background planes.
  • Figs. 3 A and 3B illustrate a single reconfigurable chip implemented such that it switches between three configuration functions.
  • Figs. 4 A and 4B illustrate two reconfigurable chips, one of which is implemented to switch between two commumcation system configurations.
  • Figs. 5 A and 5B illustrate the switching of a reconfigurable fabric between a path search configuration and a rake receiver configuration.
  • Fig. 6 is a flow chart illustrating the switching between a path searcher, rake receiver, and Viterbi configurations for a reconfigurable chip such as the system shown in Figs. 3 A and 3B.
  • Fig. 7 is a diagram illustrating the switching of the communication system configurations for a reconfigurable chip as well as the central processing unit processing during the different configurations for one embodiment of the system of the present invention.
  • Figs. 8 A and 8B illustrate a system using multiple reconfigurable chips, one of the reconfigurable chips switching between a Viterbi and Turbo configuration.
  • Fig. 9 illustrates a two-reconfigurable chip implementation of a CDMA communication system.
  • Fig. 10 illustrates the operation of the first reconfigurable chip in the system of Fig. 9.
  • Fig. 11 is a flow chart that illustrates the operation of the system shown in
  • Fig. 10 is an illustration of a reconfigurable chip 20 which can be used in one embodiment of the present invention.
  • the reconfigurable chip includes a foreground configuration plane 22 and a background configuration plane 24.
  • the foreground configuration plane 22 configures the elements of the reconfigurable fabric 26, such that a portion of the communication system design can be implemented.
  • the reconfigurable chip 20 also includes a processor 28 such as a reduced instruction set computing (RISC) central processing unit (CPU).
  • RISC reduced instruction set computing
  • CPU 28 runs portions of a communication system algorithm which are difficult to implement in the reconfigurable fabric.
  • the reconfigurable fabric 26 in a preferred embodiment, includes a number of configurable data path units, memory units, and interconnect elements.
  • the data path units include comparators, an arithmetic logic unit (ALU), and registers which are configurable to implement operations of the algorithm.
  • the reconfigurable fabric 26 also includes dedicated elements such as multipliers and memory elements. The memory elements can be used for storing data of the algorithm.
  • the configuration bits for the different configurations of the communication system are implemented by compiling the algorithm with a software compiler which allocates the reconfigurable elements in the reconfigurable fabric to portions of the algorithm.
  • the external memory 30 can be used to store the different configurations for the communication system algorithm. These configurations can be loaded using the memory access unit 32 and bus 34 into the background plane.
  • the background and foreground planes are interleaved with the reconfigurable elements in the fabric. The loading of the background plane is preferably done with a separate bus system from the data-connect lines used in the reconfigurable fabric 26. Additional details of the reconfigurable chip can be found from the disclosure of U.S. Patent No.
  • Fig. 2 A illustrates the preferred configuration of the switching between the foreground and background planes.
  • the background configuration memory element 40 is loadable from the external memory, while the foreground configuration memory element 42 configures the configurable unit 44 within the reconfigurable fabric.
  • the background plane is activated, the data in the background plane writes over the data in the foreground plane. If the old configuration needs to be run again, it is reloaded into the background plane.
  • Fig. 2B shows an alternate and less preferred embodiment in which the background configuration element 40' and foreground configuration element 42' are connected to the configurable unit 44' using a multiplexer 46. Due to the additional overhead of this embodiment, it has been found to be less preferable than the example of Fig. 2A.
  • Figs. 3 A and 3B illustrate a reconfigurable chip 50 which implements three portions of a wireless communication system.
  • the reconfigurable chip 50 is part of a base station unit which implements, within a frame 52 operation time, three different configurations: a path search configuration 52a, a rake receiver configuration 52b, and a Viterbi configuration 52c.
  • a path search configuration 52a a path search configuration
  • a rake receiver configuration 52b a rake receiver configuration
  • a Viterbi configuration 52c a Viterbi configuration
  • FIG. 4A illustrates an alternate system in which two reconfigurable chips, reconfigurable chip 54 and reconfigurable chip 56, are used.
  • a path search configuration 58a and rake receiver configuration 58b operate.
  • the reconfigurable chip 56 is implemented with a Viterbi configuration.
  • Figs. 5 A and 5B illustrate the switching between a path searcher configuration and a rake receiver configuration.
  • An example of this -switching is done at the transition between configurations 52a and 52b of Fig. 3B, and 58a and 58b of Fig. 4B.
  • the foreground configuration memory 60 contains the path searcher configuration. This configures the reconfigurable fabric 62 into the path search configuration, and the reconfigurable fabric implements the path searching portion of the computer system.
  • the rake receiver configuration is loaded into the background plane 64.
  • the reconfigurable fabric includes a memory unit which can allow data from one configuration to be accessed by a second configuration without requiring data transfer.
  • the rake receiver configuration from the background plane 64' can be loaded into the foreground plane 60' .
  • This then almost instantaneously configures the reconfigurable fabric 62' in the rake receiver configuration, which can be completely different from the path search configuration.
  • the switching as shown in Figs. 5A and 5B, can be done within a single clock cycle, as long as there is sufficient time during the processing of the prior configuration to load the next configuration into the background plane.
  • Fig. 6 is a flow chart of the system of Figs. 3 A and 3B. Note while one of the configurations is being loaded, the other configuration can be run concurrently.
  • Fig. 7 illustrates the use of a reconfigurable chip in multiple configurations. This shows the reconfigurable fabric processing as well as the CPU processing. The CPU allows the calculation of portions of the communication algorithm difficult to implement on the reconfigurable fabric. It also provides a resource for calculation which is separate from the reconfigurable fabric. The use of the CPU on a reconfigurable chip having a reconfigurable fabric thus provides advantages to implementing the communication system algorithm.
  • Fig. 8 A illustrates an embodiment with multiple reconfigurable chips, some of the reconfigurable chips implementing a fixed configuration.
  • the symbol rate processor 70 switches between a Viterbi configuration 72a and a Turbo configuration 72b.
  • Figs. 9-11 illustrate an implementation of a wireless communication system following a U.S. standard for wireless Code Division Multiple Access (CDMA).
  • CDMA Code Division Multiple Access
  • Fig. 9 illustrates an embodiment in which a reconfigurable chip 80 implements pseudo-random-number generation, demodulation, figure search and access search, while reconfigurable chip 82 implements the Viterbi and other processing.
  • Fig. 10 illustrates the switching between the different configurations in the reconfigurable chip 80 of Fig. 9.
  • Fig. 11 is a flow chart illustrating the operation of the reconfigurable chip
  • reconfigurable chips used in the present invention are especially useful in the base station operation of a wireless communication system.
  • the base station operation multiple communication connections are operated processed.
  • the assignment of the number configurations to the different reconfigurable chips is partially determined by the number of users serviced by the base station and the resulting processing burden in each configuration.
  • Large base stations may have many users and use more reconfigurable chips, some of which are dedicated to a single configuration.
  • a base station working with fewer users may have more of the communication system configurations implemented on a single reconfigurable chip.
  • the required processing speeds also affect this implementation arrangement. Note that in the systems of Figs. 3-8, a pseudo-random-number generator is not shown.
  • the pseudo-random-number generator is implemented as a portion of the path searcher or rake receiver implementation, which may require additional configuration switching. Alternately, the pseudorandom-number generator can be implemented in a spare time slot. In one embodiment, the pseudo-random-number generator is a gold-code generator. Additional details of one embodiment of an implementation of a communication system (a wireless base station) on a reconfigurable chip is given in the following appendices. Appendix 1 describes an overview of the path searching and rake receiver. Appendix 2 gives details of the rake receiver embodiment including details of a gold-code generator. Appendix 3 gives details of the implementation of a Viterbi algorithm on a reconfigurable chip.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Logic Circuits (AREA)
  • Transceivers (AREA)

Abstract

Cette invention concerne un système de communication sans fil pouvant être mis en oeuvre au moyen d'un ou de plusieurs microcircuits reconfigurables qui présentent des plans de reconfiguration avant et arrière. L'arrière-plan peut être chargé avec un algorithme de communication, une autre partie dudit algorithme étant configurée dans l'avant plan et fonctionnant au sein de la matrice reconfigurable. La commutation entre les configurations d'avant-plan et d'arrière-plan se fait pratiquement instantanément. Le système selon la présente invention se prête à la mise en oeuvre d'un système de communication complexe, tel qu'un récepteur de station de base pour un système de communication sans fil, ceci sur un petit microcircuit reconfigurable et non sur un prédiffusé programmable (FPGA) beaucoup plus gros.
PCT/US2001/049436 2000-10-27 2001-10-25 Systeme et procede de mise en oeuvre d'un systeme de communication sans fil au moyen d'une puce reconfigurable avec matrice reconfigurable Ceased WO2002056481A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01998067A EP1336248A4 (fr) 2000-10-27 2001-10-25 Systeme et procede de mise en oeuvre d'un systeme de communication sans fil au moyen d'une puce reconfigurable avec matrice reconfigurable
AU2002249827A AU2002249827A1 (en) 2000-10-27 2001-10-25 System and method of implementing a wireless communication system using a reconfigurable chip with a reconfigurable fabric

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69907800A 2000-10-27 2000-10-27
US09/699,078 2000-10-27

Publications (3)

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WO2002056481A2 true WO2002056481A2 (fr) 2002-07-18
WO2002056481A3 WO2002056481A3 (fr) 2002-09-06
WO2002056481A9 WO2002056481A9 (fr) 2003-05-30

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EP (1) EP1336248A4 (fr)
CN (1) CN1248417C (fr)
AU (1) AU2002249827A1 (fr)
WO (1) WO2002056481A2 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7017140B2 (en) 2002-08-29 2006-03-21 Bae Systems Information And Electronic Systems Integration Inc. Common components in interface framework for developing field programmable based applications independent of target circuit board
US7847730B2 (en) 2006-09-27 2010-12-07 Bae Systems Information And Electronic Systems Integration, Inc. Software defined navigation signal generator
CN1703839B (zh) * 2002-10-07 2011-01-12 松下电器产业株式会社 通信装置和用于重新配置通信装置的方法
US8095927B2 (en) 2002-08-30 2012-01-10 Wisterium Development Llc Object oriented component and framework architecture for signal processing
US10743317B1 (en) 2010-09-14 2020-08-11 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US11006343B2 (en) 2006-12-26 2021-05-11 Dali Wireless, Inc. Distributed antenna system
US11159129B2 (en) 2002-05-01 2021-10-26 Dali Wireless, Inc. Power amplifier time-delay invariant predistortion methods and apparatus
US11297603B2 (en) 2010-08-17 2022-04-05 Dali Wireless, Inc. Neutral host architecture for a distributed antenna system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103383677B (zh) * 2012-05-03 2016-06-22 中国科学院电子学研究所 兼具无线配置和无线收发模式的无线可编程片上系统的方法

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Publication number Priority date Publication date Assignee Title
JP2869826B2 (ja) * 1991-08-28 1999-03-10 キヤノン株式会社 半導体製造方法
US5970254A (en) * 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US6096091A (en) * 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US5999990A (en) * 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11159129B2 (en) 2002-05-01 2021-10-26 Dali Wireless, Inc. Power amplifier time-delay invariant predistortion methods and apparatus
US7017140B2 (en) 2002-08-29 2006-03-21 Bae Systems Information And Electronic Systems Integration Inc. Common components in interface framework for developing field programmable based applications independent of target circuit board
US7464360B2 (en) 2002-08-29 2008-12-09 Bae Systems Information And Electronic Systems Integration Inc. Common interface framework for developing field programmable device based applications independent of a target circuit board
US8095927B2 (en) 2002-08-30 2012-01-10 Wisterium Development Llc Object oriented component and framework architecture for signal processing
CN1703839B (zh) * 2002-10-07 2011-01-12 松下电器产业株式会社 通信装置和用于重新配置通信装置的方法
US7847730B2 (en) 2006-09-27 2010-12-07 Bae Systems Information And Electronic Systems Integration, Inc. Software defined navigation signal generator
US11006343B2 (en) 2006-12-26 2021-05-11 Dali Wireless, Inc. Distributed antenna system
US11818642B2 (en) 2006-12-26 2023-11-14 Dali Wireless, Inc. Distributed antenna system
US11297603B2 (en) 2010-08-17 2022-04-05 Dali Wireless, Inc. Neutral host architecture for a distributed antenna system
US11013005B2 (en) 2010-09-14 2021-05-18 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US10743317B1 (en) 2010-09-14 2020-08-11 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US11368957B2 (en) 2010-09-14 2022-06-21 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US20220295487A1 (en) 2010-09-14 2022-09-15 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US11805504B2 (en) 2010-09-14 2023-10-31 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods
US12382444B2 (en) 2010-09-14 2025-08-05 Dali Wireless, Inc. Remotely reconfigurable distributed antenna system and methods

Also Published As

Publication number Publication date
WO2002056481A9 (fr) 2003-05-30
CN1484887A (zh) 2004-03-24
EP1336248A4 (fr) 2005-04-20
CN1248417C (zh) 2006-03-29
WO2002056481A3 (fr) 2002-09-06
EP1336248A2 (fr) 2003-08-20
AU2002249827A1 (en) 2002-07-24

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