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WO2001097580A1 - Dispositif electronique et procede de fabrication dudit dispositif - Google Patents

Dispositif electronique et procede de fabrication dudit dispositif Download PDF

Info

Publication number
WO2001097580A1
WO2001097580A1 PCT/JP2001/004891 JP0104891W WO0197580A1 WO 2001097580 A1 WO2001097580 A1 WO 2001097580A1 JP 0104891 W JP0104891 W JP 0104891W WO 0197580 A1 WO0197580 A1 WO 0197580A1
Authority
WO
WIPO (PCT)
Prior art keywords
solder paste
circuit board
solder
electronic device
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2001/004891
Other languages
English (en)
Japanese (ja)
Inventor
Toshiharu Ishida
Tasao Soga
Hanae Shimokawa
Tetsuya Nakatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of WO2001097580A1 publication Critical patent/WO2001097580A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0545—Pattern for applying drops or paste; Applying a pattern made of drops or paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the surface mounting of electronic components using lead-free (Pb) -free solder alloy instead of lead-tin eutectic solder, and particularly to the occurrence of solder pools or solder ridges in surface mounting. It is about prevention.
  • Pb lead-free
  • solders that can replace Sn-37mass% Pb (hereinafter abbreviated as Sn-37Pb) solders.
  • Sn-Zn, Sn-Ag, Sn- Sb-based, Sn-Ag-Bi-based, etc. have been mentioned.
  • the alternative Pb-free solder has lower wettability and melt-separability than the Sn-37Pb eutectic solder.
  • the supply of solder to the wiring pattern of the circuit board is performed by transferring the solder paste by printing, using a print mask shape that matches the pattern, and using the conventional Sn-37Pb eutectic solder.
  • the pattern and print mask pattern generally had the same shape.
  • An object of the present invention is to reliably connect an electronic component to a conventional circuit board using Pb-free solder instead of Sn-37Pb solder. Disclosure of the invention
  • the printed shape of the solder paste supplied to the connection wiring pattern of the circuit board is V-shaped (concave or convex is also effective), and V-shaped (concave or convex) is used for leadless chip components. I turned to the direction.
  • the method for manufacturing an electronic device further comprising using a print mask having a pattern different from the connection wiring pattern of the circuit board, for example, a print mask having a pattern smaller than the connection wiring pattern of the circuit board, to form the connection wiring pattern on the circuit board.
  • the solder is supplied, the semiconductor device is mounted on the circuit board, and the circuit board and the semiconductor device are connected by reflow.
  • FIG. 1 is a diagram showing a state in which a semiconductor device is mounted on a wiring circuit.
  • FIG. 2 is a view showing a longitudinal section of a lead portion of a mounted semiconductor device.
  • FIG. 3 is a view showing a cross section of a mounted state of the semiconductor device.
  • FIG. 4 is a diagram showing a state where the semiconductor device is mounted on the wiring circuit.
  • FIG. 5 is a view showing a longitudinal section in a mounted state of the semiconductor device.
  • FIG. 6 is a diagram showing a cross section of a lead portion of a mounted semiconductor device.
  • FIG. 7 is a diagram showing a state where the semiconductor device is mounted on the wiring circuit.
  • FIG. 8 is a view showing a cross section of a mounted state of the semiconductor device.
  • FIG. 9 is a view showing a cross section of a lead portion of a mounted semiconductor device.
  • FIG. 10 is a diagram illustrating the description of the occurrence of solder poles.
  • FIG. 11 is a view showing a mounted state of a leadless chip component.
  • FIG. 12 is a diagram showing an entire cross section of mounting a leadless chip component.
  • FIG. 13 is a diagram showing a cross section of an electrode portion of a leadless chip component.
  • FIG. 14 is a diagram showing a mounted state of a leadless chip component.
  • FIG. 15 is a diagram showing an entire cross section of mounting a leadless chip component.
  • FIG. 16 is a diagram showing a cross section of an electrode portion of a leadless chip component.
  • FIG. 17 is a view showing a mounting state of a leadless chip component.
  • FIG. 18 is a diagram showing an entire cross section of mounting a leadless chip component.
  • FIG. 19J is a view showing a cross section of an electrode portion of the leadless chip component.
  • FIG. 20 is a diagram showing a cross section and a plane of the semiconductor module.
  • FIG. 21 is a diagram showing a connection state between a semiconductor module and a circuit board.
  • FIG. 22 is a diagram showing a manufacturing process of the electronic device. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 22 shows an example of a manufacturing process of an electronic device including a semiconductor device (semiconductor chip) and the like.
  • a semiconductor device semiconductor device
  • device circuits are formed on a wafer, and a spring probe and plated contact terminals are brought into contact with the electrodes of the wafer to perform probe inspection.
  • the wafer on which the circuit pattern has been formed is diced and individualized, placed on an island such as a lead frame, and attached (mounted).
  • the mounted chip and lead frame are wire-bonded with gold wire or the like to make electrical connection.
  • the lead frame is set in the mold, the temperature is increased, and the fluidized resin is pumped to seal the entire chip with the resin.
  • the non-defective semiconductor device that has passed the sorting process is mounted on a mounting board such as a mother board using solder. As a result, electronic devices (including multi-chip modules) are manufactured.
  • a so-called wafer-level chip size package (WL-CSP) is used in which relocation wiring is formed from electrodes on the wafer at the wafer level, external connection terminals (for example, solder bumps) are formed, and then dicing is performed. May be used.
  • the method for preparing the semiconductor device and the circuit board (mounting board) is not limited to the above.
  • FIG. 1 shows, for example, a solder paste 4 a to 4 d printed on a predetermined wiring pattern 3 a to 3 d in order to connect a semiconductor device 2 having relatively wide I leads 5 a to 5 d to a circuit board 1.
  • This shows a state in which the transfer is supplied and the semiconductor device 2 is mounted thereon.
  • 2 and 3 are cross-sectional views of the cross-section observation finger portions XX ′ (6) and YY ′ (7).
  • the solder pastes 4a to 4d are applied to the wiring patterns 3a to 3d in a state where the solder pastes 4a to 4d face the wiring patterns 3a to 3d and the leads 5a to 5d of the semiconductor device 2.
  • the semiconductor device 2 is transferred and supplied so as to be V-shaped on the leads 3a to 3d.
  • the solder is partially soldered to the leads 5a to 5d. There is no best. That is, it is supplied in a shape having a notch.
  • the solder paste melts. The molten solder tends to be repelled by the side bands of the leads 5a to 5d due to the weight of the semiconductor device 2, or spreads over the metallized portions of the leads 5a to 5d.
  • the resistance of the metallized portion is smaller than the resistance of the side band at the time of rejection, so that it spreads over the metallized portion facing the unprinted portions 8a and 8b of the solder paste.
  • This becomes a leading role and the solder spreads and spreads even on the unprinted portions 8a and 8b of the solder paste of the wiring patterns 3a to 3d facing each other, and there is little elution to the side band of the wiring pattern, The generation of solder poles or the generation of a bridge between the wiring patterns is suppressed.
  • FIGS. 4, 5, and 6 show, for example, a predetermined wiring pattern for connecting the semiconductor device 2 having the I leads 5a to 5d to the circuit board 1.
  • 4D is a state diagram of a semiconductor device 2 which is transferred and supplied in a concave shape to form a semiconductor device 2 thereon.
  • the solder pastes 4a to 4d are melted and spread along the metallized portions of the leads 5a to 5d. If there is residual solder, as in Example 1, the resistance at the time of metallization is lower than the rejection resistance, so that it spreads over the metallized side of the lead facing the unprinted portions 8a and 8b of the solder paste, Led by it
  • solder also wets the unsoldered paste printed part of the wiring pattern. As a result, the occurrence of solder poles and bridges is suppressed.
  • FIGS. 7, 8, and 9 show, for example, solder pastes 4 a to 4 d on a predetermined wiring pattern 3 a to 3 d for connecting a semiconductor device 2 having I leads 5 a to 5 d to a circuit board 1.
  • FIG. 6 is a state diagram of a semiconductor device 2 transferred and supplied in a convex shape, and a semiconductor device 2 placed thereon.
  • the solder pastes 4a to 4d are melted and the metallized portions 1 of the leads 5a to 5d 1 "Wetting spreads along 0a> 10b. If there is residual solder, the unprinted portion of solder paste 8a, 8 Wet spreads on the metallized side of the lead opposite to b, leading to it, the solder also wets the unsoldered paste printed part of the wiring pattern
  • Fig. 10 shows a 1608 chip with metallization for electrodes 10a and 10b, a Sn-AgCu-based solder paste 4 for a 2125 chip, and a common Pb-Sn for the wiring pattern 3 on the circuit board 1. It shows the appearance in which a large pole 11 with a diameter of 100 to 500 m is formed on the side of the chip after solder printing with the mask pattern used for polycrystalline solder and passing it through a furnace with a riff opening of max 245 ° C. Such a pole 11 is formed even if the amounts of Ag and Cu in the solder are slightly different.
  • the cause is poor wettability to the Cu pad, so the solder that has been ejected by press-fitting when mounting the chip cannot return to the Cu pad due to the effect of the resist step, and remains as a large pole.
  • FIGS. 11, 12, and 13 show the connection of the leadless chip component 9 to the circuit board 1 with the soldering pastes 4a, 4b applied to the predetermined wiring patterns 3a, 3b and inside the electrodes.
  • FIG. 4 is a diagram showing a state in which a transfer and supply are performed in a V-shape, and a leadless chip component is mounted thereon.
  • the solder paste is passed through a reflow furnace in this state, the solder pastes 4a and 4b are melted and spread along the metallized portions 10a and 10b. If there is residual solder, the occurrence of solder poles can be suppressed.
  • the area of the Cu pad portion is increased, the wetted portion is increased, and the probability of pole generation is further reduced.
  • the V type is superior in producing less poles than the concave and convex types shown below.
  • the chip if the chip is mounted with misalignment, the portion where the paste and the chip come into contact changes linearly, so even a slight misalignment does not cause a problem.
  • the chip touches the concave side surface, and the degree of influence on wetting without touching it May be adversely affected.
  • FIG. 4 is a state diagram of a state in which a transfer and supply are performed so as to form a concave shape toward, and a leadless chip component is mounted thereon.
  • the unprinted solder paste 8a, 8b is provided on the wiring patterns 3a, 3b. It can suppress the occurrence of solder poles.
  • FIG. 6 is a diagram showing a state in which transfer and supply are performed so as to project toward a portion, and a leadless chip component is mounted thereon. Even in the present embodiment, even if residual solder is generated as in the case of the fourth and fifth embodiments, the solder balls are provided by providing the unprinted solder paste 8a and 8b on the wiring patterns 3a and 3b. Can be suppressed. (Example 7)
  • Figure 20 shows the connection between the terminals of the module package, the terminal of the chip carrier, the terminal of the chip component, etc., which are practically used in mobile devices such as mobile phones. It uses the LGA (Lead Grid Array) method taken by comrades. In high-density mounting of solder paste, it is important not to generate solder residue defects such as pole residues and bridges. Pb-free solder has poor wettability and spreads, so only the printed portion gets wet on the free surface, but when pressurized, it is affected by it and spreads out where there is metallization. For this reason, if the amount of solder is large and there is no wet spot, the excess solder will protrude from the terminal, forming an independent pole or bridging with the adjacent terminal.
  • LGA Lead Grid Array
  • FIG. 20 (a) is a cross-sectional view including terminals of a module on which an LSI is mounted, and FIG.
  • (b) is a plan view thereof.
  • (C) is a cross section in a state where the solder paste 15 is printed on the circuit board 18 and the terminals 13 of the module 12 are positioned.
  • the bump height (h) in the module differs due to the unevenness and warpage of the circuit board, the inclination after connection between the module and the circuit board, or the difference in the amount of printed solder. For this reason, the terminals with a narrow gap and a large amount of solder may spill out and become an independent solder pole or a bridge with an adjacent terminal. Therefore, module side terminal diameter; b, solder printing diameter; a, circuit board terminal diameter; c, and a ⁇ b ⁇ c, terminals with narrow gaps and large amount of solder were applied.
  • solder is wet (effective when the amount of solder is large) 19 to secure the area 14 that can absorb the solder.
  • 2 At the time of repair, it is always broken by the solder on the module terminal side.
  • the pad is not peeled off by strengthening it with the resist film 16 even after several repairs.
  • the Cu pad surface is Ni / Au plated, the amount of solder may be insufficient. At this time (when the gap is wide), even if there is a portion where the substrate surface is not wet, there is no problem of Cu oxidation. Note that even if the connection terminals are terminals for heat dissipation, the views on solder poles and bridges are the same. Industrial applicability

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

L'invention concerne un dispositif électronique que l'on peut connecter de manière très fiable, à une carte de circuit traditionnelle au moyen d'une brasure tendre exempte de plomb utilisée en tant que substitut d'une brasure tendre de Sn-37Pb. La pâte à braser (4) est amenée sur le côté intérieur du modèle de câblage (3) de la carte de circuit (1) en forme de V, encastrée ou projetée, et ladite pâte est connectée au dispositif à semi-conducteur (2), ce qui permet au dispositif électronique d'être dotée d'une fiabilité de connexion élevée.
PCT/JP2001/004891 2000-06-12 2001-06-11 Dispositif electronique et procede de fabrication dudit dispositif Ceased WO2001097580A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-180711 2000-06-12
JP2000180711 2000-06-12

Publications (1)

Publication Number Publication Date
WO2001097580A1 true WO2001097580A1 (fr) 2001-12-20

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Application Number Title Priority Date Filing Date
PCT/JP2001/004891 Ceased WO2001097580A1 (fr) 2000-06-12 2001-06-11 Dispositif electronique et procede de fabrication dudit dispositif

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1263270A3 (fr) * 2001-06-01 2004-06-02 Nec Corporation Procédé de montage de composants électroniques sans la création de billes de soudure inutiles
US11285569B2 (en) 2003-04-25 2022-03-29 Henkel Ag & Co. Kgaa Soldering material based on Sn Ag and Cu

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62112179U (fr) * 1986-01-07 1987-07-17
JPH01186388A (ja) * 1988-01-22 1989-07-25 Hitachi Ltd ハンダ印刷マスク、その製造方法およびハンダ印刷方法
EP0957520A2 (fr) * 1998-04-16 1999-11-17 Sony Corporation Boítier pour semi-conducteur, panneau d'assemblage et methode d'assemblage
EP0976489A1 (fr) * 1996-12-17 2000-02-02 Sony Corporation Matériau pour soudure tendre

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62112179U (fr) * 1986-01-07 1987-07-17
JPH01186388A (ja) * 1988-01-22 1989-07-25 Hitachi Ltd ハンダ印刷マスク、その製造方法およびハンダ印刷方法
EP0976489A1 (fr) * 1996-12-17 2000-02-02 Sony Corporation Matériau pour soudure tendre
EP0957520A2 (fr) * 1998-04-16 1999-11-17 Sony Corporation Boítier pour semi-conducteur, panneau d'assemblage et methode d'assemblage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1263270A3 (fr) * 2001-06-01 2004-06-02 Nec Corporation Procédé de montage de composants électroniques sans la création de billes de soudure inutiles
US7013557B2 (en) 2001-06-01 2006-03-21 Nec Corporation Method of packaging electronic components without creating unnecessary solder balls
US11285569B2 (en) 2003-04-25 2022-03-29 Henkel Ag & Co. Kgaa Soldering material based on Sn Ag and Cu

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