WO1999060329A1

WO1999060329A1 - Electronic delay detonator

Info

Publication number: WO1999060329A1
Application number: PCT/JP1999/002080
Authority: WO
Inventors: Kazuhiro Kurogi; Midori Sakamoto
Original assignee: Asahi Kasei Kogyo Kabushiki Kaisha
Priority date: 1998-05-19
Filing date: 1999-04-20
Publication date: 1999-11-25
Also published as: JPH11325799A; AU3172099A; TW406184B

Abstract

Electric energy sent from a blasting machine is received via a pair of input terminals and charged to a charging circuit to drive an electronic timer. The electronic timer performs, by issuing an enable signal a preset time later and detecting the charging voltage level of the charging circuit, a first operation leading to detonation and a second operation for setting detonation conditions. The first operation issues a trigger signal a second reference time later set by the second operation and discharges the accumulated electric energy to cause detonation. Since a detonation start signal need not be received and, therefore, there is little possibility of detonation being erroneously started, a blasting operation will not fail to ensure a safe and erro-free blasting operation.

Description

Description Electronic delay detonator Technical field

The present invention provides a high-precision blasting operation in which a plurality of explosives are loaded on a crushing target (for example, a bedrock or a building) and each of them is sequentially or simultaneously detonated to crush the crushing target. The present invention relates to an electronic delay detonator capable of controlling the detonation time, ensuring the reliability of detonation, and further capable of arbitrarily programming the detonation time. Background art

Conventionally, a plurality of crushing targets are charged, each of which is detonated sequentially or simultaneously, and used as a primer for crushing the crushing target, and a technique for controlling the detonation time with high precision. A charging circuit for receiving the electric energy transmitted from the device and storing the electric energy, an electronic timer driven by the stored electric energy, and an electronic timer. When a trigger signal is generated, an ignition switch that discharges the accumulated electric energy and an ignition device that is detonated by the discharged electric energy form an electronic delay detonator. Proposed.

The conventional technology of this type of electronic delay detonator can be roughly classified from the functional point of view of the function of starting the timing of detonation. Sending, timing It is classified into the type that starts automatically.

For the electronic delay detonators belonging to the former type, the delay time is set at the time of shipment from the factory. For example, USP 4, 445, 435 and the user can freely program the delay time. For example, there are USP 4, 674, 047, USP 5, 460, 093, USP 5, 406, 890 and so on.

For electronic delay detonators of the type that the user can program arbitrarily, the step of programming the detonation delay time and after timing the programmed detonation time It has two operating stages: detonating the primer.

According to this type of prior art electronic delay detonator, the two operation stages are distinguished by a difference in control signal between the signal source and the electronic delay detonator based on the communication protocol.

Electronic delay detonators belonging to the latter type include USP 5,363,765 and others.

It is said that the accuracy of the electronic delay detonator of the type that sends only the above energy and starts timekeeping automatically is generally not better than the former type. According to 5, 363 and 765, this problem is solved by over-exciting the crystal oscillator and rapidly stabilizing the oscillation.

If a control mode is used that sends a detonation signal and starts timing separately from the above energy, there are some concerns in actual blasting work. .

One point of concern is the reliability of control signal communication. In communication of the control signal, there is a concern that the control signal is not transmitted to the detonator as intended, due to the noise environment and the connection reliability of the detonator. Since the connection operation of the detonator is performed artificially, it was necessary to assume that various failure phenomena would occur in the connection state, and the inspection and inspection were performed before the detonation operation Nevertheless, it is undeniable that the possibility that such a failure event as described above would occur at the time of the start of the explosion timing.

At the program stage, even if such control inconveniences occur, correct them by checking the program results. Is possible, but it is extremely difficult to correct this if it occurs at the time of the start of the timing of the detonation, and it is extremely severe if it occurs. Results. If the transmitted detonation signal is not transmitted as intended to one of the connected detonators, the detonator will be unexploded and the crushed object will be broken randomly. .

For this reason, it is assumed that the secondary crushing work may be dangerous and that the work load may be doubled, which will cause serious trouble. In addition, when multiple electronic delay detonators are simultaneously controlled from one signal source by applying general data communication technology as described above, the connection form is generally a distributed branching. The (parallel connection) method is preferred, and it is composed of a plurality of detonators connected in parallel to the signal source. In such a control system, the input impedance of an electronic delay detonator is generally designed to be relatively high, and the signal power is weak. In such cases, such concerns are even more acute. Another point of concern is the safety of the program or the safety against stray currents that may occur at the blasting site. About

According to W092 / 221067, the ignition element attached to the electronic delay detonator has a "designed misfire voltage", and the program is lower than the misfire voltage. It discloses the technology to be implemented. The safety during programming can be avoided by the technology disclosed in the above-mentioned W092 / 1067 or similar technology. However, this does not necessarily ensure the same safety against stray currents. In particular, when attempting to control the detonation circuit system by the distributed branching (parallel connection) method, the input impedance of the electronic delay detonator is set relatively high as described above. . When such an electronic delay detonator receives a stray current at the blasting site, even if it is a weak stray current, the input terminal voltage reaches a voltage sufficient to explode. There is concern that it will rise. In such a case, even if the start of the detonation is configured to be performed only by the control signal, the detonation does not necessarily result in the detonation operation due to a malfunction. .

These concerns are common to all types that send a detonation signal to start timing.

On the other hand, the type that leads to detonation only by supplying energy without exchanging the detonation signal is simple and has a simple structure, so the reliability is high, but the user can freely set the delay time. The things that can be programmed are not known. Also, this type of electronic delay detonator will detonate when supplied with sufficient electrical energy to operate as indicated by its characteristics. Because it operates, it is widely armed. In the case of adding such a function that enables the program control as described above to such an electronic delay detonator of the evening eve, work safety is ensured. To maintain the distinction between program control and detonation control while maintaining it requires an extra measure. Even if a control signal that gives priority to the program control is sent and the program control is harmed during the detonation operation, the detonator recognizes the control signal. It is assumed that this could not be done, or that a malfunction could lead to detonation.

In order to use electronic delay detonators industrially, it is essential to ensure the reliability and safety of electronic delay detonators, and to solve these issues. These technologies are not independent of each other, but are inseparable and closely related.

The electronic delay detonator according to the present invention can be programmed with an arbitrary detonation delay time with high reliability and safety in functionality, and can be reliably detonated. Regarding delay detonators. Disclosure of invention

In order to solve these problems, an electronic delay detonator according to the present invention includes a pair of input terminals for receiving electric energy transmitted from a blaster, a rectifier circuit, and the electric A charging circuit for storing energy, and an enable signal generated after a first reference time driven by the stored electric energy, and a second reference time that can be set. After receiving the enable signal and an electronic signal that emits a trigger signal later, the charging circuit detects the charging voltage level of the charging circuit, and If the electric voltage is equal to or higher than the first voltage, the first operation leading to detonation is performed, and if the charging voltage is equal to or lower than the second voltage which is lower than the first voltage, the detonation condition is set. An operation determining means for controlling to perform a second operation to be set; and receiving the trigger signal in the first operation and storing the trigger signal in the charging circuit. A detonation switch for discharging electric energy, a ignition device detonated by the discharged electric energy, and a control signal for receiving a control signal in the second operation Signal receiving means and a detonation condition setting means controlled by the control signal.

The second voltage is a misfire voltage that is not sufficient to ignite the igniter.

The control signal receiving means receives a control signal composed of a pulse train applied between the input terminals after the charging circuit is charged, and sets the firing condition according to the control signal. Means are configured to set the firing conditions.

Further, when the control signal receiving means receives the control signal for inspection, the firing condition set by the firing condition setting means is output as a pulse train between input terminals. It has an explosion condition output means.

The explosion condition output means comprises a side current signal generating means and a side current circuit for flowing a current applied between the signal input terminals, and the side current signal generating means comprises a program. A side current signal consisting of a pulse train corresponding to the condition is output, and when the side current circuit receives the side current signal, the constant current received following the inspection control signal described above. A controlled current is caused to flow by side to generate a voltage change between the input terminals, and the voltage change is It is configured to output to the outside as a pulse train of the firing condition.

Further, the electronic delay detonator of the present invention has a side-flow resistor between the input terminals. The side current resistor determines a signal voltage applied to an internal circuit of the electronic delay detonator when the control signal is applied while being controlled to a constant current. The resistance value of the side current resistor is preferably

It is composed of 100 Ω at a rate of 100 Ω, and more preferably about 10 Ω or about 20 Ω. For example, if the side current resistor is composed of 10 Ω or 20 Ω, the signal impedance will increase due to the lower input impedance, and the S / N ratio will increase. Has been significantly improved, and the reliability of communications can be increased. In addition, the input impedance of the electronic delay detonator is reduced by the side current resistor, and the safety against stray current is enhanced.

For the sake of safety, there is provided means for inhibiting the first operation when performing the second operation.

Further, when the operation determining means determines that the charging voltage is lower than the first voltage and higher than the second voltage, the charging is performed. It has self-discharge means for self-discharging the voltage.

In addition, the supply of electric energy for detonation, such as when supplying electric energy by blasting an evening eve that discharges the electric energy charged to a capacitor, In a case where the energy is configured to end at a predetermined time, the potential between the input terminals is detected after a predetermined time that has been determined in advance after receiving the enable signal. However, if the voltage is equal to or higher than the third voltage, a self-discharging means for self-discharging the electric energy accumulated in the charging circuit may be provided.

Regarding the start of the explosion timing, the charging signal level of the charging circuit is continuously detected in response to the enable signal, and it is determined that the charging voltage has reached the first voltage or higher. An operation determining means for detecting and generating a reset signal is provided, and the timing circuit receives the reset signal and generates a trigger signal after measuring a second reference time. It may be configured.

According to the electronic delay detonator of the present invention, it is possible to distinguish the operation based on the voltage level charged in the energy storage circuit.

First, by applying a voltage exceeding the first voltage level, it is possible to shift to the first operation in the detonation mode. Therefore, the detonation operation can be performed only by supplying the electric energy.

Second, by setting the second voltage level below the misfire level of the ignition device, the safety in performing the second operation other than the detonation mode is increased. You.

Third, by setting the first voltage level higher than the power supply voltage of the signal source that sends the control signal, the signal source may fail unexpectedly, and the power supply voltage may be directly applied to the primer. Even if it is applied, it does not shift to the detonation mode, and self-discharge can be safely performed. Further, since the detonation conditions can be set by receiving a control signal, for example, the detonation delay time can be set arbitrarily. Further set Since the detonation conditions can be output as a pulse train between the input terminals, the output pulse is analyzed and the intended detonation conditions are set without mistake. Can be confirmed. Brief description of the drawings

FIG. 1 is an example of a structural diagram of an electronic delay detonator according to an embodiment of the present invention.

FIG. 2 is an example of a structural diagram of an electric detonator 3 used for the electronic delay detonator of the embodiment of the present invention.

FIG. 3 is an example of a hybrid IC configuration of the electronic delay detonator of the embodiment of the present invention.

FIG. 4 shows an example of a block diagram for explaining the operation of the electronic delay detonator of the embodiment of the present invention.

FIG. 5 is a flowchart illustrating an overall operation of the electronic delay detonator according to the embodiment of the present invention.

FIG. 6 is a flowchart illustrating the detonating operation of the electronic delay detonator according to the embodiment of the present invention.

FIG. 7 is a flowchart illustrating an operation for specifying an operation mode of a signal control processing operation of the electronic delay detonator according to the embodiment of the present invention.

FIG. 8 is a flowchart showing an example of the operation of the electronic delay detonator of the embodiment of the present invention in the id data program mode.

FIG. 9 is a flowchart illustrating an operation of the electronic delay detonator according to the embodiment of the present invention in the detonation time data program mode.

FIG. 10 shows the id delay time of the electronic delay detonator of the embodiment of the present invention. 6 is a flowchart illustrating a check mode operation.

FIG. 11 is a flowchart illustrating an operation of the electronic delay detonator according to the embodiment of the present invention in the detonation time over time check mode operation.

FIG. 12 is a flowchart illustrating a pseudo ignition discharge operation of the electronic delay detonator of the embodiment of the present invention.

FIG. 13 is a flowchart illustrating a self-discharge operation of the electronic delay detonator of the embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

In order to explain the present invention in more detail, a specific embodiment will be described, and this will be described with reference to the accompanying drawings.

FIG. 1 illustrates a structural diagram of an electronic delay detonator according to the present embodiment. The electronic delay detonator of this embodiment has a pair of legs 1 for receiving electric energy or a control signal supplied from a signal source or a blaster (not shown), An energy storage capacitor 34 that charges the supplied electric energy, and an evening that is operated by the electric energy charged in the capacitor 34 It comprises an imaginary module 2 and an electric detonator 3 which is detonated by the electric energy charged in the capacitor 34.

In this embodiment, the timer module 2 and the electric detonator 3 are inserted into the bottomed insulated tube 5, and then both the capacitors 34 and the bottomed tubes are inserted. It is stored in the metal case 6.

The leg 1 is connected to the timer module 2 from the outside through an embolus 4 made of synthetic resin. The opening of the metal case 6 is sealed with the plug 4, and the metal case 6 is tightened and sealed.

FIG. 2 illustrates a structural diagram of an electric detonator 3 used in the electronic delay detonator of the present embodiment.

The electric detonator 3 includes a pair of legs 11 for receiving the discharge energy of the capacitor 34, and an ignition heater (electric bridge) 1 connected to an end of the leg 11. 3 and an ignition device 12 composed of an ignition device arranged around the ignition heater 13, and a priming 15 and an additive 16 are arranged in a bottomed manner as shown in FIG. 2. It is housed in a metal case 18 of the present invention.

The leg 11 connects the timer module 2 and the ignition heater 13 through an embolus 17 made of synthetic resin.

The opening of the metal case 18 is sealed with the plug 17, and the metal case 18 is tightened and sealed.

The metal case 6 has a thickness of, for example, 0.5 to lmm at a portion covering the timer module 2 and has a thickness covering a portion covering the electric detonator 3 at the tip. For example, it has an uneven thickness structure with a thickness of 0.2 to 0.3 mm. (The uneven thickness structure protects the module 2 from external shocks, for example, the explosion of an adjacent hole, and is effective to prevent the detonation power of the electric detonator 3 from being impaired. )

The insulating tube 5 is made of an electrically insulating plastic material, for example, vinyl chloride, polyster, polyethylene, and a metal case 6. Dramatically improves the antistatic performance between the electric detonator 3 and the metal case 6 and the timer module 2, and the static electricity Prevent the explosion of the electric detonator 3 and the failure due to the damage of the timer module 2. Although the shape is not limited, it is preferable to be molded in consideration of manufacturability. For this reason, a polystyrene excellent in moldability and preform is used as the material. It is optimal. Further, the insulating tube 5 of the present embodiment is configured to cover only the timer module 2 and the electric detonator 3, but this is extremely large. When a large amount of static electricity is received, the discharge point is discharged at the connection terminal of the capacitor 34 near the opening of the tube, and the static electricity generated at random To prevent the electric detonator 3 from exploding, but cover the capacitor 34 and extend it between the plug 4 and the case 6, and It may be tightened and sealed at the same time.

Next, with reference to FIGS. 3, 4, and 5, the operation of the evening imager module 2 will be described.

FIG. 3 shows an example of the timer IC module 2 of the electronic delay detonator of this embodiment.

FIG. 4 is a block diagram illustrating the operation of the timer IC 40 mounted on the timer module 2 of the electronic delay detonator of the present embodiment. It is a thing.

FIG. 5 exemplifies a flow chart of the overall operation of the electronic delay detonator of the present embodiment.

The electronic delay detonator according to the present embodiment has a charging circuit 34 for storing electric energy, and after a first reference time T1 which is predetermined after the charging circuit 34 is charged. A self-generated enable signal (SE) is generated at a predetermined time after the enable signal (SE) is generated. Then, the charging voltage of the charging circuit 34 is detected, and the following two selectable operations are performed according to the charging voltage level.

The first operation that can be selected is an initiating operation that starts the electric detonator 3 by measuring a settable second reference time T2.

The second operation that can be selected is a signal control processing operation determined by a transmitted control signal.

According to the second operation, the settable second reference time T2 can be programmed.

See the hybrid IC configuration in FIG.

When electric energy is received between the input terminals IN 1 and IN 2, it is rectified by the rectifier 32 and passed through the diode 33 to be connected to the capacitor. The sensor 34 is charged with the electric energy. When the charging voltage of the capacitor 34 reaches a predetermined voltage, the constant voltage circuit 38 connects the capacitor C 5, the time constant circuit 47, and the timer IC 40. To output a constant voltage.

When the IC 40 is supplied with the power supply voltage Vcc, the oscillation circuit 100 (FIG. 4) disposed inside the IC 40 sets the XT, The driving of the crystal oscillation circuit 50 connected to the XT bar terminal is started.

Initially, the IC 40 does not perform any operation and maintains the reset state. The reset release signal output point 54 of the time constant circuit 47 is connected to the RESET terminal of the timer IC 40, and the potential of the output point 54 is input. For example, a comparator (not shown) is provided inside the timer IC 40 so that the potential at the output point reaches a predetermined value. The first reference time Tl is counted. After the first reference time T1, the reset state of the RESET circuit 101 (FIG. 4) in the timer IC 40 is released.

(Fig. 5, Step 1)

Immediately after the reset state is released, the ESET circuit 101 (Fig. 4) resets all the functions of the timer IC 40 and returns to the state where the function can be operated. Become .

(Fig.5-Step 2)

See the block diagram in FIG.

The evening image IC 40 (Fig. 3) is composed of a power supply switch 100, a control circuit system 201, and a circuit system 202. The control circuit system 201 is composed of circuit systems 211 and 212.

Circuit system 211 has charge voltage judgment logic 111, input signal characteristic check logic 112, start signal judgment logic 113, program logic Includes 114, id data memory 115, and detonation time data memory 116. Circuit system 212 includes detonation time data counting logic 118. The circuit system 202 includes a REST circuit 101 and an oscillation circuit 102.

The power supply switching switch 100 (FIG. 4) receives and receives signals, which are fixed by the constant voltage circuit 38 (FIG. 3) via the Vcc terminal. Supply the power supply voltage to 01 and 202.

The RESET circuit 101 and the oscillation circuit 102 supply a reset release signal or a reset signal and an oscillation pulse to the necessary parts of the circuit system 201, respectively. . Evening IC 40 (Fig. 3) When the power is reset, the reset signal is applied to the output selection logic 1 17 from the reset circuit 101. (SP) is sent to prevent SCR 2 (Figure 3) from being inadvertently triggered. (1st operation prohibition means)

At the same time, in the charging voltage determination logic 111, the clocking of the step time t1 is started, and the input signal characteristic confirmation logic 112 is output. Then, timing of the step times t2 and t3 is started. (Fig. 5, Step 3)

When the time t 1 reaches, for example, 50 ms, the potentials of the charging voltage determination ports J C 1 1 and V CMP 2 and V CMP 3 are determined. (Figure 5 — Step 4)

In FIG. 3, VCMP 2 and VCMP 3 are respectively connected to a divided voltage output point 52 of a voltage divider circuit 42 and a divided voltage output point 53 of a voltage divider circuit 43, and The charge voltage of the capacitor 34 is detected.

When the charge voltage judgment logic 1 1 1 judges that the potential of VCMP 2 is equal to or lower than the second voltage set in advance, the start signal judgment logic 1 1 3 Then, the program logic 114 is activated to start the second operation, that is, the signal control processing operation.

(Fig. 5 — Step 5)

The charge voltage determination logic 111 is set so that the potential of VCMP 2 is lower than the preset first voltage, and the potential of VCMP 3 exceeds the preset second voltage. When it is determined that the voltage is a voltage that can be obtained, the charge voltage determination logic 111 sends a discharge signal (SD1) to the selected output logic 117. Selected output logic 1 1 7 Upon receiving the discharge signal (SD1), the self-discharge signal (SD) is output from the OUTB terminal of the IC 40 (FIG. 3).

In FIG. 3, the OUTB terminal is connected to the gate terminal of the SCR 1, and when the self-discharge signal (SD) is output, the energy is stored through the self-discharge circuit 44. Self-discharge the charge of capacitor 34.

(Figure 5 — Step 8)

When the charging voltage determination logic 1 1 1 is equal to or higher than the preset first voltage of the potential of VCMP 3 and the step time t 2 reaches, for example, 80 ms. The input signal characteristic confirmation logic 112 starts determination of the potential of VCMP 1, and determines the input signal characteristic in step time t 3, for example, 100 ms.

(Figure 5—Step 6)

In FIG. 3, V CMP1 is connected to the divided output point 51 of the voltage dividing circuit 41, and detects the potential between the input terminals IN 1 and IN 2 through the rectifier 32.

In the input signal characteristic confirmation logic 112, the period from time t2 to t3 is divided by a predetermined time interval dt, and the potential of VCMP1 is determined a predetermined number of times n times.

In addition, during the time interval d t, it is determined whether or not V CMP 1 is continuously receiving a voltage equal to or higher than the third voltage.

Finally, at the time t3, the total of the determination results is integrated, and during a period from the time t2 to the time t3, the potential of the VCMP1 is continuously set to be equal to or less than the third voltage set in advance. Make sure there is. This prevents erroneous judgment due to accidental noise.

The charge voltage determination logic 1 11 determines that the potential of VCMP 3 is equal to or higher than the preset first voltage at time t 1, and the input signal characteristics If the confirmation logic 112 determines that VCMP 1 is continuously lower than or equal to the third voltage in the time width from time t2 to t3, the input signal characteristic The confirmation logic 112 activates the detonation time delay counting logic 118 and shifts to the second operation, that is, the detonation operation.

(Fig. 5, Step 7)

Although charge voltage determination logic 1 1 1 has determined at time t 1 that the potential of VCMP 2 is greater than or equal to the preset first voltage. Input signal characteristics check Logic 1 12 determines that VCMP 1 has not been continuously below the third voltage in the time width from time t2 to t3. Then, the input signal characteristic confirmation logic 112 sends a discharge signal (SD2) to the output selection logic 117. Upon receiving the discharge signal (SD2), the selected output logic 117 outputs a self-discharge signal (SD) to the OUTB terminal.

In FIG. 3, the OUTB terminal is connected to the gate terminal of SCR1, and when the self-discharge signal (SD) is output, the self-discharge circuit 44 is activated. As a result, the charge stored in the energy storage capacitor 34 is self-discharged.

(Fig. 5, Step 8)

The first operation, ie, the detonation operation (FIG. 5, step 7) will be described with reference to FIGS. 3, 4, and 6. FIG. The input signal characteristic confirmation logic 112 sends a timing start signal (SS), activates the explosion time data counting logic 118, and transitions to the second operation immediately to the explosion operation. Then, the input signal characteristic confirmation logic 112 sends a protect release signal (SK1) to the selected output circuit 117. (Fig. 6, Step 9)

Subsequently, the input signal characteristic confirmation logic 112 sends a power switching signal (SV) to the power switching switch 100. The power switching switch 100 is switched when it receives a power switching signal (SV), and stops the supply of the power voltage to the circuit system 211.

(Fig. 6, Step 10)

Subsequently, the detonation time data counting logic 118 is pre-programmed by counting the output pulses of the oscillating circuit 102, a second reference which is pre-programmed. Time T 2.

The detonation time data counting logic 118 is connected to the detonation time data memory 116, and is used for the time data in the detonation time data memory 116. Count the corresponding pulses.

(Figure 6 — Step 1 1)

The oscillation circuit 102 outputs a pulse by driving a crystal oscillation circuit 50 connected through XT and XT-bar. The oscillation circuit 102 outputs the above output pulse by dividing the output pulse as needed to the circuit system 201 inside the IC 40. When the pulse corresponding to the time of the second reference time T2 is counted, the detonation time data counting logic 118 outputs a count end signal to the output selection circuit 117. Send (Se). Output selection circuit 1 1 7 When a signal (Se) is received, a trigger signal (ST) is output to OUTC. (Fig. 6-Step 1 2)

In FIG. 3, the OUTC terminal is connected to the gate terminal of SCR 2, and when the trigger signal (ST) is output, the energy storage capacitor 3 is output. The charge of 4 is ignited and discharged to the ignition discharge circuit including the OUT1 and OUT2 terminals, and the attached electric detonator 3 (Fig. 1) is detonated.

(FIG. 6—Step 13) Referring to FIG. 3 and FIG. 4, the entire operation of the second operation, ie, the signal control processing operation (FIG. 5, step 5) Explain.

The signal control processing operation is controlled by a control signal received from an external control signal source (not shown).

The control signal includes a start signal, a step signal, a program data signal, and a write signal which are transmitted from an external control signal source (not shown) in chronological order in a predetermined order. It consists of a combination of the input power signal and the return reference level signal.

The second operation is composed of a plurality of signal control operation modes each of which is independently executed, and in each of the signal control modes, execution of the second operation is determined. It is specified by the start signal sent later from the outside, and responds to the control signal and the program data signal related to each signal control mode sent continuously. And perform the action. The signal control operation mode and a start signal for specifying the operation mode will be exemplified below. • The start signal bit of the id data program mode is set.

[0 1 0 0 1].

• Set the start signal bit pattern of the detonation time data program mode to [0101].

• Set the start signal bit pattern of the id data check mode to [0110].

• Set the start signal bit pattern for the detonation time

[0 0 1 1 0].

• Set the start signal bit pattern of the pseudo ignition discharge mode to [0101].

'Set the start signal bit notation of the self-discharge mode to [0100].

[0] of the bit pattern is an "L" level signal, and

[1] is an "H" level signal. The start signal is, for example, a pulse train power of 5 b it, where the first b it is [0].

The electronic delay detonator detects the leading bit [0], and the external control signal source (not shown) and the electronic delay detonator are synchronized.

See the hybrid IC configuration in FIG.

The start signal and the continuous control signal are externally controlled to a constant current, input from IN 1 and IN 2, and correspond to the above-described constant current value by the input resistor R 1. It is supplied as a voltage. The control signal is supplied at a voltage approximately equal to or slightly lower than the charging potential of the energy storage capacitor 34. The control signal is pre-charged by a signal detection diode 33 via a rectifier 32. The signal is input to the DATAIN pin of the IC 40 without being affected by the potential of the energy storage capacitor 34.

The electronic delay detonator according to the present embodiment stores a step status signal indicating the progress of the control operation in response to the control signal and program data stored in an internal storage circuit described later. It has a function to reply to the outside.

In FIG. 3, the reply operation is performed by a serial pulse from the OUTA terminal of the timer IC 40 at a predetermined timing in accordance with a predetermined communication protocol. The output is sent to the gate terminal of MOS-FET 35. In the timing of performing the above-mentioned reply operation, the above-mentioned reply reference level signal is received immediately, that is, a continuous signal externally controlled to a constant current. When the signal is not output from the OUTA terminal at the time when the return reference level signal is being received, the potential between the input terminals IN1 and IN2 is controlled. At the time of signal reception, the voltage is held as a voltage corresponding to the constant current value by the input resistor R 1 similarly. MOS — When the FET 35 receives a signal at the gate terminal and turns on, the received constant current signal is divided by the MOS — FET 35 and the resistor R 2. And the potential between the input terminals INI and IN 2 drops. Therefore, the inverted signal string of the reply signal string output from the OUTA pin of the IC 40 is output to the outside. A change in the potential between the input terminals can be detected as a return signal. Therefore, the control signal source, the electronic delay detonator, and the control signal input from an external control signal source (not shown) are used in response to the return signal output from the electronic delay detonator. Is bidirectional Is communicated to

See the block diagram in FIG.

The control signal to be received via the DTA IN terminal is input to the start signal discriminating logic 113 and the program logic 114. The start signal discriminating logic 113 and the program logic 114 correspond to the first bit bit of the start signal transmitted first.

Detects [0] and synchronizes with an external control signal source (not shown). The start signal discriminating logic 113 identifies the signal control mode by discriminating the sequentially received start signal bit pattern sequence, and the control mode indicating the control mode. Send the specified signal (SC) to the program logic 114. When receiving the control mode specific signal (SC), the program logic 114 responds to the control signal which is continuously received and operates in accordance with the specific signal. Perform.

If the control mode is the id data program mode (start signal bit pattern [01001]), the received id program program The operation of writing one night into the id data memory 115 is executed. The id data memory 115 is preferably an electrically writable non-volatile memory such as R RM, and most preferably an EEPROM. Be composed.

If the control mode is the detonation time data program mode (start signal bit pattern [0 0 0 1 1]), the received detonation time program Executes the operation of writing the program data to the detonation time data memory 116. The detonation time memory 116 is preferably an electrically writable non-volatile memory such as a ROM. Most preferably, it consists of an EEPROM.

If the control mode is id data check mode (start signal bit pattern [0 1 1 0 0]), id data memory 1 15 An operation of reading the id data written to the terminal and outputting the id data to the OUTA terminal via the output selection logic 117 is executed.

If the control mode is the detonation time data check mode (start signal bito n ° [0 0 1 1 0]), the detonation time data will be lost. Operation to read out the explosion time data written in the memory 116 and output the explosion time data to OUTA terminal via output selection logic 117. Perform.

If the control mode is the pseudo ignition discharge mode (start signal bit pattern [0101]), program logic 114 is selected and output. After sending a protect release signal (SK2) to the power circuit 1 17 to set the ignition circuit to a state in which ignition is possible, it is written to the ignition time data memory 116. The detonation time data, that is, the second reference time T2 is measured, and the pseudo ignition discharge operation is executed. The pseudo-ignition discharge operation performs the same operation as the above-mentioned detonation operation (steps 9 to 11 in FIG. 6), but in this case, the energy storage capacitor 3 The discharge voltage of 4 is lower than the discharge voltage that can be detonated, and is configured so that it does not explode.

An external control signal source (not shown) is a signal controlled by a constant current immediately from the time when the second reference time is measured to the time when the pseudo ignition discharge is performed. The signal is transmitted and the pseudo-ignition is discharged. At this point, the voltage change that occurs between the input terminals (IN1, IN2) because the return reference level signal is bypassed to the ignition discharge circuit 45 (Fig. 3) (Descent) and confirm that there is no problem in the ignition discharge circuit 45.

If the control mode is the self-discharge mode (start signal bit pattern [0100]), program logic 114 is selected. Send discharge signal (SD 3) to output circuit 1 17. Upon receiving the discharge signal (SD 3), the selected output logic 117 outputs a self-discharge signal (SD) to the 〇UTB terminal.

In FIG. 3, the OUTB terminal is connected to the gate terminal of the SCR 1, and when the self-discharge signal (SD) is output, the OUTB terminal passes through the self-discharge circuit 44. Then, the charge of the energy storage capacitor 34 is self-discharged. The self-discharge mode is executed mainly to discharge the charge stored in the energy storage capacitor 34 when the second operation is completed, and the second operation, that is, the signal Used as the end mode of control processing operation.

The plurality of signal control operation modes are not completed except for the pseudo ignition discharge mode and the self-discharge mode, and after each operation mode is executed, the start signal is not reset. It returns to the state of waiting for [0] of the first bit, detects the first bit, synchronizes again with an external control signal source (not shown), and continues operation.

Until the second operation is completed after the first operation is specified, the determination of the charging voltage of the energy storage capacitor 34 is continued. The determination of the charging voltage of the energy storage capacitor 34 is as follows. The charge voltage determination logic 111 determines whether or not the potential of the VCMP 2 terminal of the timer IC 40 is equal to or lower than the second voltage.

After the second operation is specified, if it is determined that the charging voltage of the capacitor 34 is equal to or higher than the second voltage, the charging voltage determination port 1 1 1 Sends a reset signal (SR) to the RESET circuit 101. When receiving the reset signal (SR), the REST circuit 101 resets the operation of the circuit system 201.

When the circuit system 201 is reset, all operations are initialized, return to the initial state (step 2 in FIG. 5), and repeat the operation.

With reference to FIG. 7, an operation in which a plurality of operation modes included in the second operation are specified by a start signal that is received from the outside will be described.

Upon transition to the first operation, [0] at the start bit of the start signal is detected. It is in a standby state until [0] of the first bit is input. (Fig. 7—Step 101)

On the other hand, when the operation shifts to the second operation, the determination of the charging voltage of the energy storage capacitor 34 is continued until the second operation is completed. If it is determined that the charging voltage of the capacitor 34 is equal to or higher than the second voltage, all the operations are initialized and return to the initial state (FIG. 5—Step 2). Repeat the operation.

(Fig. 7 Step 1 102)

Therefore, if the electric energy signal for blasting is supplied in this state without inputting the first bi [0] of the start signal, the operation can be shifted to the first operation, that is, the detonation operation. . If [0] of the start bit of the start signal is detected, the start signal is determined. (Fig. 7-Step 103)

When the start signal is determined, a control operation corresponding to the start signal is performed. (Fig. 7-Step 104)

When the control operation corresponding to the start signal ends or when the start signal cannot be recognized, the start bit of the start signal is determined.

It returns to the [0] detection standby state (step 101 in FIG. 7). The id data program mode operation will be described with reference to FIG.

In the operation of discriminating the start signal (step 103 in FIG. 7), when the id data program mode start signal [01001] is recognized, A step status signal sequence [01] indicating that the start signal has been recognized is output on the reply reference level signal.

(Figure 8 — Step 1 1 1)

When the step state signal is output, an external control signal source (not shown) detects the step state signal and transmits the id program data string. To receive. (Fig. 8 Step 1 1 2)

When the reception of the id program data string is completed, a step status signal string indicating that the reception of the id program data string is terminated on the reply reference level signal. [0 1] is output.

(Figure 8 — Step 1 1 3)

Subsequently, writing of the id program data is executed by a write power signal supplied by an external control signal source (not shown). (Figure 8 — Step 1 1 4) When the writing operation of the id program data string is completed, a signal indicating that the writing of the id program data string has been completed on the reply reference level signal is completed. Outputs the step status signal sequence [01].

(Figure 8 — Step 1 1 5)

Then, the operation is terminated, and the operation returns to the detection standby state (step 101 in FIG. 7) for detecting [0] at the start bit of the start signal.

Referring to FIG. 9, the operation of the program mode in the detonation time will be described.

In the start signal discriminating operation (Step 103 in Fig. 7), when the ignition time data program mode start signal [0101] is recognized, a reply is returned. A step status signal sequence [01] indicating that the start signal has been recognized is output on the reference level signal.

(Fig. 9 — Step 1 2 1)

Next, the read of the programmed id data sequence is executed. (Fig. 9 Step 1 22)

When the step status signal is output, an external control signal source (not shown) detects the step status signal and receives an id confirmation data string transmitted therefrom. . (Fig. 9 Step 1 23)

When the reception of the id confirmation data string is completed, a step status signal string [01] indicating that the reception of the id data string is terminated is output on the reply reference level signal. You (Fig. 9 — Step 1 2 4)

Subsequently, the read id data string is compared with the received id data string. (Fig. 9 Step 1 25)

After the matching, the id data is put on the reply reference level signal and It outputs a step status signal string [0 1] to the effect.

(Figure 9 — Steps 1 2 6)

When the step state signal is output, an external control signal source (not shown) detects the step state signal and transmits the same. Receive the column.

(Figure 9 — Step 1 2 7)

When the reception of the program data sequence for the detonation time has been completed, a signal indicating that the reception of the program data sequence for the detonation time has been completed is put on the reply reference level signal. Outputs the step status signal sequence [01].

(Fig. 9 — Step 1 2 8)

Subsequently, the writing of the detonation time program data is executed by a writing power signal supplied from an external control signal source (not shown). (Fig. 9 — Step 1 2 9)

When the write operation of the detonation time program data sequence is completed, a signal indicating that the writing of the id program data sequence has been completed on the response reference level signal is completed. Outputs the step status signal sequence.

(Fig. 9 Step 1 330)

In the step (step 1 25 in FIG. 9) for comparing the read id data string with the received id data string, the id data string is If they do not match, reset each element that performs signal control processing, and wait for the time that continuous firing time data program mode operation should end. For example, the reset state is maintained for 150 ms. (Fig. 9 Step 1 13 1)

Then, the operation ends, and [0] of the first bit of the start signal is detected It returns to the standby state (Step 101 in Fig. 7). .

The operation of the id data check mode will be described with reference to FIG. .

When the id data program mode start signal [0110] is recognized in the start signal discrimination operation (Step 103 in Fig. 7), a reply is returned. A step status signal sequence [01] indicating that the start signal has been recognized is output on the reference level signal.

(Fig. 10 1 Step 1 4 1)

Subsequently, the read of the programmed id data sequence is executed. (Figure 10 — Step 1 4 2)

Subsequently, the id data string read out on the reply reference level signal is output as a reply. (Fig. 10 — Step 1 4 3)

When the reply of the id data string is completed, a step status signal string [01] indicating that the reply of the id program data string has been completed is put on the reply reference level signal. Output .

(Figure 10 — Step 1 4 4)

Subsequently, the operation is terminated, and the process returns to the detection standby state (step 101 in FIG. 7) for detecting [0] at the start bit of the start signal.

With reference to FIG. 11, the operation of the detonation time check mode will be described.

In the start signal discriminating operation (step 103 in FIG. 7), when the detonation time data program mode start signal [010110] is recognized, A step status signal sequence [01] indicating that the start signal has been recognized is output on the reply reference level signal. (Fig. 1 1 — Step 15 1)

Subsequently, the read-out of the programmed id data sequence is executed. (Fig. 1 1 — Step 15 2)

When the step state signal is output, an external control signal source (not shown) detects the step state signal and receives an id confirmation data sequence which is transmitted. To (Fig. 11 1 Step 1 5 3)

When the reception of the id confirmation data sequence is completed, a step status signal sequence indicating that the reception of the id program data sequence has been completed with the reply reference level signal is completed. 0 1] is output.

(Fig. 11 1 Step 1 5 4)

Subsequently, a comparison is made between the read id data sequence and the received id data sequence. (Fig. 11-Step 1 5 5)

If the data is matched, a step status signal sequence [01] indicating that the id data is matched is output on the reply reference level signal.

(Fig. 1 1 Step 1 56)

Subsequently, the programmed explosion time data is read out. (Fig. 1 1 — Step 1 5 7)

Subsequently, the explosion time data string read out on the reply reference level signal is output as a reply. (Figure 1 1 — Step 15 8)

When the response of the detonation time data string is completed, a step status signal string [0] indicating that the response of the detonation time program data string is terminated on the reply reference level signal 1] is output.

(Fig. 1 1 — Step 15 9)

The ratio of the read id data sequence to the received id data sequence In the step for performing the comparison (FIG. 1—Step 144), when the id data does not match, each element for executing the signal control processing is performed. The reset state is maintained, and the reset state is maintained for the duration that the data explosion time data pro- gram mode operation should end, for example, for 150 ms. You (Fig. 1 1 Step 160)

Then, the operation is terminated, and the process returns to the standby state for detection of [0] at the start bit of the start signal (FIG. 7—step 101).

The pseudo ignition discharge mode operation will be described with reference to FIG.

When the id data program mode start signal [0101] is recognized in the start signal discrimination operation (step 103 in Fig. 7), a reply is returned. A step status signal sequence [01] indicating that the start signal has been recognized is output on the reference level signal.

(Fig. 1 2 — Step 16 1)

Subsequently, the protected state of SCR 2 is released.

(Fig. 12 — Step 16 2)

Subsequently, the timing operation based on the detonation time, which should have been programmed, is started.

(Figure 1 2 — Step 16 3)

Subsequently, a timing operation based on the detonation time, which is supposed to be programmed, is programmed.

(Fig. 12 — Step 16 4)

When the explosion time counting operation, which should have been programmed, is completed, a pseudo ignition discharge is performed and the operation is terminated. (Fig. 1-1 step 1 65)

The self-discharge mode operation will be described with reference to FIG. In the start signal discriminating operation (step 103 in FIG. 7), when the id data program mode start signal [0100] is recognized, a reply reference is made. A step status signal sequence [01] indicating that the start signal has been recognized is output on the level signal.

(Figure 13 — Step 1 7 1)

Subsequently, self-discharge is performed, and the signal control processing operation ends. (Fig. 13 — Step 1 7 2)

The signal control processing operations shown in FIGS. 8 to 13 can be arbitrarily combined and executed. Potential for industrial use

According to the electronic delay detonator of the present invention, it is possible to distinguish the operation by detecting the level of the supplied voltage. Alternatively, it is possible to configure safety operations in various ways. This is particularly effective when the second operation for setting the detonation conditions, that is, when programming the detonation delay time.

(Hereinafter the margin)

Claims

Claims 1. A pair of input terminals (IN1, IN2) for receiving electric energy transmitted from a blaster, a rectifier circuit (32), and accumulating the electric energy. It is driven by the charging circuit (34) and the stored electric energy, emits an enable signal (SE) after a first reference time (T1), and can be set. Receiving an electronic timer (40) that emits a trigger signal (ST) after a second reference time (T2) and the enable signal (SE), the charging circuit (34) Detecting the charging voltage level of the battery, and if the charging voltage is equal to or higher than the first voltage, performs a first operation leading to detonation; and, if the charging voltage is lower than the first voltage, Operation determination means for controlling to perform a second operation for setting the detonation condition if the voltage is equal to or less than In a first operation, a triggering switch for receiving the trigger signal (ST) and discharging the electric energy stored in the charging circuit (34); An ignition device that is detonated by the ignition device; a control signal receiving unit that receives a control signal in the second operation; and an ignition condition setting unit that is controlled by the control signal. An electronic delay detonator characterized by having. 2. The electronic delay detonator according to claim 1, wherein a side current resistor is provided between the input terminals.

Claim 3. The electronic delay detonator according to claim 2, wherein the side-flow resistor has a resistance of 100 Ω or 100 Ω.

4. The control, wherein the control signal receiving means comprises a pulse train applied between the input terminals after the charging circuit is charged. The electronic delay detonator according to claim 1, wherein a signal is received, and the detonation condition setting means sets the detonation condition according to the control signal. Claim 5. The electronic delay detonator according to claim 1, further comprising means for inhibiting the first operation when the second operation is performed.

Claim 6. The electronic delay detonator of Claim 1, wherein the second voltage is a misfiring voltage that is not sufficient to detonate the igniter (12).

Claim 7. The charging operation is performed when the operation determining unit determines that the charging voltage is lower than the first voltage and higher than the second voltage. 2. The electronic delay detonator according to claim 1, further comprising a self-discharge means for self-discharging a voltage. Claim 8. When the control signal receiving means receives a control signal for inspection, an initiating condition set by the initiating condition setting means is output as a pulse train between input terminals. The electronic delay detonator according to claim 1, further comprising condition output means.

Claim 9. The explosion condition output means includes a side flow signal generating means (113 to 117) and a side flow circuit (31, 4) for flowing a current applied between signal input terminals. 6), the sidestream signal generating means outputs a sidestream signal (SO) consisting of a pulse train corresponding to the program condition, and the sidestream circuit receives the sidestream signal. Then, a constant-current controlled current received subsequent to the inspection control signal flows sideways to generate a voltage change between the input terminals, and the voltage change is output to the outside as a pulse train under an ignition condition. Claim 8 characterized by the following: Electronic delay detonator. Claim 10: After receiving an enable signal at the input terminals (IN1, IN2), after a predetermined period of time, the potential between the input terminals is detected, and the voltage is detected. 2. The method according to claim 1, further comprising a self-discharge means (44, 112, 117) for self-discharging the electric energy stored in the charging circuit if the voltage is equal to or higher than a third voltage. Electronic delay detonator.

Claim 1 1.

A pair of input terminals (IN1, IN2) for receiving electric energy transmitted from the blaster, a rectifier circuit (32), a charging circuit (34) for storing the electric energy, and the stored electric energy. And an enable signal generating means for generating an enable signal (SE) after a first reference time (T1); and receiving the enable signal (SE) after receiving the enable signal (SE). An operation determining means for continuously detecting a charging voltage level of the charging circuit (34), detecting that the charging voltage has reached a first voltage or more, and generating a reset signal; Receiving a reset signal, measuring a second reference time (T2), and then generating a trigger signal (ST); receiving the trigger signal (ST); A detonating switch for discharging electrical energy stored in the circuit (34); An electronic delay detonator characterized by having an ignition device detonated by electric energy.