[go: up one dir, main page]

WO1996007969A1 - Dispositif integre de correction d'erreurs - Google Patents

Dispositif integre de correction d'erreurs Download PDF

Info

Publication number
WO1996007969A1
WO1996007969A1 PCT/CA1995/000517 CA9500517W WO9607969A1 WO 1996007969 A1 WO1996007969 A1 WO 1996007969A1 CA 9500517 W CA9500517 W CA 9500517W WO 9607969 A1 WO9607969 A1 WO 9607969A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
computer
rsimc
parity
eca
Prior art date
Application number
PCT/CA1995/000517
Other languages
English (en)
Inventor
Bosco C. S. Lai
Original Assignee
Lai Bosco C S
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA 2131735 external-priority patent/CA2131735A1/fr
Application filed by Lai Bosco C S filed Critical Lai Bosco C S
Publication of WO1996007969A1 publication Critical patent/WO1996007969A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Definitions

  • the present invention is an on board errors correction methodology whereas an error correction apparatus (ECA) is a separate chip or device which utilizes the error detection and correction method in a memory system and memory sub-systems.
  • An algorithm detects and reports the kind of errors of the RSIMC (Memory chip that does not meet the manufacturers' original designed specifications). RSIMC with the same error pattern will then be grouped together along with the ECA for assemble into memory modules or memory cards .
  • ECA employs the redundant Error Correcting Algorithm which enables the rejected, fallout, audio grade, toy grade or any other kinds of reduced specification memory chips to become computer grade compatible, so that the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications.
  • the invention is an "on board" error correction methodology which employs the Redundant Error Correcting Algorithm to upgrade the RSIMC to become computer grade compatible.
  • ECA is mounted on the memory boards, memory cards, or SIMM modules along with the RSIMC's. It corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time. There is no limit on the number of errors corrected in total.
  • the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications and would only have a slight adverse effect on the computers' speed performance.
  • RSIMC refers to Reduced Specification Integrated Memory Chip which does not meet the manufacturers' original designed specifications. It includes but not limited to DRAM, ARAM, SRAM, VRAM, ROM, PROM, EPROM, FRESH Memory, and EEPROM.
  • On Board ECC means the ECC is done within the memory cards, memory modules, SIMM, or memory subsystems.
  • the invention is an "on board" error correction methodology which employs the Redundant Error Correcting Algorithm to upgrade the RSIMC to make the RSIMC board, RSIMC card or RSIMC module to become computer grade compatible.
  • An algorithm detects and reports the kind of errors of the RSIMC.
  • RSIMC with the same error pattern will then be grouped together along with the ECA for assembly into memory boards, memory cards or SIMM modules.
  • ECA is a redundant backup / switch method which corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time.
  • the corrected RSIMC memory board, memory cards or SIMM modules would function as normal memories for computer (or computer sub-systems) usages and applications. It will only have a slight adverse effect on the computers' speed performance.
  • the ECA includes the following components:
  • This part generates an extra 4 check bits Cl, C2, C3 and C4 for parity check.
  • the followings show an example of how the algorithm can be implemented.
  • This part generates the expecting check bits and compares the bits with Cl, C2, C3 and C4 using the same algorithm as in part 1.
  • the compared result will indicate the location of error if there are any errors occurred during the checking process.
  • the compared result will provide instructions to the correction circuit to correct the errors accordingly.
  • This part is the logic circuit to control the input / output timing for the ECA. It enables the output driver only after the output value is fixed and stabilized. It also ensures the , latch / input driver to be compatible with different speed devices. In other words, it improves the turn on/off lead time.
  • This part is to capture and to generate the parity mode (Odd / Even) of the system by using the "x 8 configuration”. It will then generate one of the following messages:
  • This part is to control input and output information of the memory chips, and to latch data. It isolates the memory chips and the data bus by acting as a I/O buffer to the memory chips. Therefore, instead of communicating to the data bus, the memory chips only "talk" to the ECA. Thus, it releases the I/O drivers' requirement for the memory chips.
  • the input latch also makes a clear input speed limit so that the ECA will not be affected by any unstable inputs.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne un algorithme qui détecte et identifie une erreur dans chaque adresse de mémoire de tout circuit à mémoire intégrée à caractéristiques réduites (RSIMC). Des RSMIC qui présentant les mêmes schémas d'erreurs peuvent alors être groupés avec un appareil de correction d'erreur (ECA) pour être montés dans des modules de mémoire. Un tel appareil de correction d'erreur recourt à l'algorithme de correction d'erreurs redondant ce qui permet à des circuits de mémoire rejetés, déclassés, de qualité audio ou jouet ou présentant d'autres caractéristiques réduites de devenir compatibles avec la qualité des ordinateurs, de façon que ces modules de mémoire RSIMC corrigés puissent fonctionner comme des modules de mémoire normaux destinés à des ordinateurs ou à leurs sous-systèmes et à leurs applications.
PCT/CA1995/000517 1994-09-09 1995-09-08 Dispositif integre de correction d'erreurs WO1996007969A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US30340094A 1994-09-09 1994-09-09
CA2,131,735 1994-09-09
CA 2131735 CA2131735A1 (fr) 1994-09-09 1994-09-09 Correcteur d'erreurs
US08/303,400 1994-09-09

Publications (1)

Publication Number Publication Date
WO1996007969A1 true WO1996007969A1 (fr) 1996-03-14

Family

ID=25677477

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA1995/000517 WO1996007969A1 (fr) 1994-09-09 1995-09-08 Dispositif integre de correction d'erreurs

Country Status (1)

Country Link
WO (1) WO1996007969A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0824237A3 (fr) * 1996-08-05 1999-10-06 Texas Instruments Inc. Audio RAM ayant une fonction de détection et correction d'erreur

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3814922A (en) * 1972-12-01 1974-06-04 Honeywell Inf Systems Availability and diagnostic apparatus for memory modules
US3897626A (en) * 1971-06-25 1975-08-05 Ibm Method of manufacturing a full capacity monolithic memory utilizing defective storage cells
US4612640A (en) * 1984-02-21 1986-09-16 Seeq Technology, Inc. Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
EP0520676A2 (fr) * 1991-06-28 1992-12-30 STMicroelectronics, Inc. Sous-système de mémoire à correction d'erreur
US5355377A (en) * 1993-11-23 1994-10-11 Tetra Assoc. Inc. Auto-selectable self-parity generator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897626A (en) * 1971-06-25 1975-08-05 Ibm Method of manufacturing a full capacity monolithic memory utilizing defective storage cells
US3814922A (en) * 1972-12-01 1974-06-04 Honeywell Inf Systems Availability and diagnostic apparatus for memory modules
US4612640A (en) * 1984-02-21 1986-09-16 Seeq Technology, Inc. Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
EP0520676A2 (fr) * 1991-06-28 1992-12-30 STMicroelectronics, Inc. Sous-système de mémoire à correction d'erreur
US5355377A (en) * 1993-11-23 1994-10-11 Tetra Assoc. Inc. Auto-selectable self-parity generator

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Swapping Failing Bits in 40-Pin Error Correcting SIMMS", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 37, no. 9, September 1994 (1994-09-01), NEW YORK US, pages 595 - 596 *
R. NASS: "MEMORY-EXPANSION SIMMS AND ERROR CORRECTION", ELECTRONIC DESIGN, vol. 42, no. 5, 7 March 1994 (1994-03-07), HASBROUCK HEIGHTS, NEW JERSEY, USA, pages 40, XP000441321 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0824237A3 (fr) * 1996-08-05 1999-10-06 Texas Instruments Inc. Audio RAM ayant une fonction de détection et correction d'erreur

Similar Documents

Publication Publication Date Title
US5452429A (en) Error correction code on add-on cards for writing portions of data words
US5488691A (en) Memory card, computer system and method of operation for differentiating the use of read-modify-write cycles in operating and initializaiton modes
US10169126B2 (en) Memory module, memory controller and systems responsive to memory chip read fail information and related methods of operation
US7487428B2 (en) Fully-buffered memory-module with error-correction code (ECC) controller in serializing advanced-memory buffer (AMB) that is transparent to motherboard memory controller
US5923682A (en) Error correction chip for memory applications
US5623506A (en) Method and structure for providing error correction code within a system having SIMMs
CA1290459C (fr) Memoire et dispositif connexe de detection et de correction d'erreurs
US5379304A (en) Method and structure for providing error correction code and parity for each byte on SIMM's
US7107493B2 (en) System and method for testing for memory errors in a computer system
US20140325315A1 (en) Memory module buffer data storage
WO2008115400A1 (fr) Implémentation ecc dans des composants non-ecc
US5465262A (en) Method and structure for providing error correction code and automatic parity sensing
CN1833289A (zh) 用于连接一个或多个存储器芯片的集线器模块
US20040237001A1 (en) Memory integrated circuit including an error detection mechanism for detecting errors in address and control signals
US6567950B1 (en) Dynamically replacing a failed chip
US5450422A (en) Method and structure for providing error correction code for each byte on SIMM'S
US20250060913A1 (en) Memory device, memory module including the memory device, and operating method of memory controller
US8219860B2 (en) Microprocessor system for controlling at least partly safety-critical processes
US20030182611A1 (en) Method for verifying error correction code function of a computer system
US5541941A (en) Method and structure for providing automatic parity sensing
US20040003165A1 (en) Memory subsystem including error correction
WO1996007969A1 (fr) Dispositif integre de correction d'erreurs
US20090037764A1 (en) Memory-module controller, memory controller and corresponding memory arrangement, and also method for error correction
US20100235680A1 (en) Microprocessor System for Controlling or Regulating at least partly Safety-Critical Processes
CA2131735A1 (fr) Correcteur d'erreurs

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase