WO1996007969A1 - On board error correction apparatus - Google Patents
On board error correction apparatus Download PDFInfo
- Publication number
- WO1996007969A1 WO1996007969A1 PCT/CA1995/000517 CA9500517W WO9607969A1 WO 1996007969 A1 WO1996007969 A1 WO 1996007969A1 CA 9500517 W CA9500517 W CA 9500517W WO 9607969 A1 WO9607969 A1 WO 9607969A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- computer
- rsimc
- parity
- eca
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
Definitions
- the present invention is an on board errors correction methodology whereas an error correction apparatus (ECA) is a separate chip or device which utilizes the error detection and correction method in a memory system and memory sub-systems.
- An algorithm detects and reports the kind of errors of the RSIMC (Memory chip that does not meet the manufacturers' original designed specifications). RSIMC with the same error pattern will then be grouped together along with the ECA for assemble into memory modules or memory cards .
- ECA employs the redundant Error Correcting Algorithm which enables the rejected, fallout, audio grade, toy grade or any other kinds of reduced specification memory chips to become computer grade compatible, so that the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications.
- the invention is an "on board" error correction methodology which employs the Redundant Error Correcting Algorithm to upgrade the RSIMC to become computer grade compatible.
- ECA is mounted on the memory boards, memory cards, or SIMM modules along with the RSIMC's. It corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time. There is no limit on the number of errors corrected in total.
- the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications and would only have a slight adverse effect on the computers' speed performance.
- RSIMC refers to Reduced Specification Integrated Memory Chip which does not meet the manufacturers' original designed specifications. It includes but not limited to DRAM, ARAM, SRAM, VRAM, ROM, PROM, EPROM, FRESH Memory, and EEPROM.
- On Board ECC means the ECC is done within the memory cards, memory modules, SIMM, or memory subsystems.
- the invention is an "on board" error correction methodology which employs the Redundant Error Correcting Algorithm to upgrade the RSIMC to make the RSIMC board, RSIMC card or RSIMC module to become computer grade compatible.
- An algorithm detects and reports the kind of errors of the RSIMC.
- RSIMC with the same error pattern will then be grouped together along with the ECA for assembly into memory boards, memory cards or SIMM modules.
- ECA is a redundant backup / switch method which corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time.
- the corrected RSIMC memory board, memory cards or SIMM modules would function as normal memories for computer (or computer sub-systems) usages and applications. It will only have a slight adverse effect on the computers' speed performance.
- the ECA includes the following components:
- This part generates an extra 4 check bits Cl, C2, C3 and C4 for parity check.
- the followings show an example of how the algorithm can be implemented.
- This part generates the expecting check bits and compares the bits with Cl, C2, C3 and C4 using the same algorithm as in part 1.
- the compared result will indicate the location of error if there are any errors occurred during the checking process.
- the compared result will provide instructions to the correction circuit to correct the errors accordingly.
- This part is the logic circuit to control the input / output timing for the ECA. It enables the output driver only after the output value is fixed and stabilized. It also ensures the , latch / input driver to be compatible with different speed devices. In other words, it improves the turn on/off lead time.
- This part is to capture and to generate the parity mode (Odd / Even) of the system by using the "x 8 configuration”. It will then generate one of the following messages:
- This part is to control input and output information of the memory chips, and to latch data. It isolates the memory chips and the data bus by acting as a I/O buffer to the memory chips. Therefore, instead of communicating to the data bus, the memory chips only "talk" to the ECA. Thus, it releases the I/O drivers' requirement for the memory chips.
- the input latch also makes a clear input speed limit so that the ECA will not be affected by any unstable inputs.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
This invention includes an algorithm, which detects and identifies the error in each memory address of the Reduced Specification Integrated Memory chips (RSIMC). RSIMC with the same error pattern will then be grouped together along with the Error Correction Apparatus (ECA) for assembly into memory modules. ECA employs the redundant Error Correcting Algorithm which enables the rejected, fallout, audio grade, toy grade and other reduced specification memory chips to become computer grade compatible, such that the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications.
Description
TITLE
ON BOARD ERROR CORRECTION APPARATUS
Background of the Invention
Field of the Invention:
The present invention is an on board errors correction methodology whereas an error correction apparatus (ECA) is a separate chip or device which utilizes the error detection and correction method in a memory system and memory sub-systems. An algorithm detects and reports the kind of errors of the RSIMC (Memory chip that does not meet the manufacturers' original designed specifications). RSIMC with the same error pattern will then be grouped together along with the ECA for assemble into memory modules or memory cards . ECA employs the redundant Error Correcting Algorithm which enables the rejected, fallout, audio grade, toy grade or any other kinds of reduced specification memory chips to become computer grade compatible, so that the corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications.
Description of the Prior Act.
The U.S. patent specification No. 5,127,014 discloses an error detection or correction method on the same chip as DRAM memory.
The invention of the Prior Act was an "On Chip ECC" to reduce the reject rate of the memory chips, not an "On Board ECC".
Summary of the Invention
It is an object of the invention to utilize the RSIMC in computer applications. The invention is an "on board" error correction methodology which employs the Redundant Error Correcting Algorithm to upgrade the RSIMC to become computer grade compatible. ECA is mounted on the memory boards, memory cards, or SIMM modules along with the RSIMC's. It corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time. There is no limit on the number of errors corrected in total.
The corrected RSIMC memory modules would function as normal memory modules for computer (or computer sub-systems) usages and applications and would only have a slight adverse effect on the computers' speed performance.
RSIMC refers to Reduced Specification Integrated Memory Chip which does not meet the manufacturers' original designed specifications. It includes but not limited to DRAM, ARAM, SRAM, VRAM, ROM, PROM, EPROM, FRESH Memory, and EEPROM.
"On Board" ECC means the ECC is done within the memory cards, memory modules, SIMM, or memory subsystems.
Detailed Description of the Invention
The invention is an "on board" error correction methodology which employs the Redundant Error Correcting Algorithm to upgrade the RSIMC to make the RSIMC board, RSIMC card or RSIMC module to become computer grade compatible.
An algorithm detects and reports the kind of errors of the RSIMC. RSIMC with the same error pattern will then be grouped together along with the ECA for assembly into memory boards, memory cards or SIMM modules.
ECA is a redundant backup / switch method which corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time. The corrected RSIMC memory board, memory cards or SIMM modules would function as normal memories for computer (or computer sub-systems) usages and applications. It will only have a slight adverse effect on the computers' speed performance.
The ECA includes the following components:
1. Check Bit generating circuit for encoding purpose in the memory write cycle:
This part generates an extra 4 check bits Cl, C2, C3 and C4 for parity check. The followings show an example of how the algorithm can be implemented.
C1 =DlEORD2EORD4EORD5EORD7
C2=DlEORD3EORD4EORD6EORD7
C3=D2EORD3EORD4EORD8
C4=D5EORD6EORD7EORD8
2. Check Bit generating circuit for decoding purpose in the memory read cycle:
This part generates the expecting check bits and compares the bits with Cl, C2, C3 and C4 using the same algorithm as in part 1. The compared result will indicate the location of error if there are any errors occurred during the checking process. The compared result will provide instructions to the correction circuit to correct the errors accordingly.
3. Timing control circuit
This part is the logic circuit to control the input / output timing for the ECA. It enables the output driver only after the output value is fixed and stabilized. It also ensures the , latch / input driver to be compatible with different speed devices. In other words, it improves the turn on/off lead time.
4. Parity capture / Generating circuit
This part is to capture and to generate the parity mode (Odd / Even) of the system by using the "x 8 configuration". It will then generate one of the following messages:
(a) Same parity message if there is no error or if there is only one correctable error detected;
(b) Different parity message if there is non-correctable error(s). In this case, it will generat parity error message to the computer system.
Since this "x 8 configuration" generates the parity mode itself, it is compatible with other systems using the parity feature.
5. I/O circuit for memory function
This part is to control input and output information of the memory chips, and to latch data. It isolates the memory chips and the data bus by acting as a I/O buffer to the memory chips. Therefore, instead of communicating to the data bus, the memory chips only "talk" to the ECA. Thus, it releases the I/O drivers' requirement for the memory chips.
The input latch also makes a clear input speed limit so that the ECA will not be affected by any unstable inputs.
Claims
1. An "on board" error correction methodology which employs the Redundant Error Correction Algorithm to upgrade the RSIMC's to make the RSIMC boards, RSIMC cards or RSIMC modules to become computer grade compatible. Such that the corrected RSIMC's could be applied on computer's main memory system or memory subsystem.
2. The methodology, as claimed in claim 1, includes an error detection algorithm which reports the kind of errors of the RSIMC.
3. RSIMC, as claimed in claim 1 and 2, includes all kinds of reduced specification integrated memory chips which do not meet the manufacturers' original designed specification. Names such as rejected chips, fallout chips, audio grade chips or toy grade chips are also considered as RSIMC.
4. Memories or Memory chips refer to the data width of the folio wings but not limited to:
(a) 30 pins, x8 or x9 configuration SIMM;
(b) 72 pins, x32, x36 or x40 configuration SIMM;
(c) 60 pins, xl6 or xl8 configuration SIMM;
(d) other x64, or xl28 configuration SIMM; and
(d) PCMCIA memory cards, DRAM, ARAM, SRAM, VRAM, ROM, PROM, EPROM, FRESH Memory, and EEPROM.
5. The methodology, as claimed in claim 1, includes an apparatus which employs the Redundant Error Correction Algorithm (ECA). It has the following components:
(a) Check Bit generating circuit for encoding purpose:
This part generates an extra 4 check bits Cl, C2, C3 and C4 for parity check. The followings show an example of how the algorithm can be implemented. Cl=DlEORD2EORD4EORD5EORD7
C2=DlEORD3EORD4EORD6EORD7
C3=D2EORD3EORD4EORD8
C4=D5EORD6EORD7EORD8
(b) Check Bit generating circuit for decoding purpose:
This part generates the expecting check bits and to compare the bits with Cl, C2, C3 and C4 using the same algorithm as in part (a). The compared result will indicate the location of errors if there are any errors occurred during the checking process. It will provide instructions to the correction circuit to correct the errors accordingly.
(c) Timing control circuit
This part is the logic circuit to control the input / output timing for the ECA. It enables the output driver only after the output value is fixed and stabilized. It also ensures the latch / input driver to be compatible with different speed devices. In other words, it improves the turn on off lead time.
(d) Parity capture / Generating circuit
This part is to capture and to generate the parity mode (Odd / Even) of the system by using the "x 8 configuration". It will then generate one of the following messages: (i) Same parity message if there is no error or if there is only one correctable error detected; (ii) Different parity message if there is non-correctable error(s). In this case, it will generate parity error message to the computer system.
Since this "x 8 configuration" generates the parity mode itself, it is compatible with other systems using the parity feature.
The ECC circuit detects and corrects all single error as it occurs. It also generates the parity check information according to the system's parity mode.
- 6 -
SUBSTTTUTE SHEET (RULE 26) (e) I/O circuit for memory function
This part is to control input and output information of the memory chips, and to latch data. It isolates the memory chips and the data bus by acting as a I/O buffer to the memory chips. Therefore, instead of communicating to the data bus, the memory chips only "talk" to the ECA. Thus, it releases the I/O drivers' requirement for the memory chips. The input latch also makes a clear input speed limit so that the ECA will not be affected by any unstable inputs.
6. The components, as claimed in claim 5, have the following features:
(a) added timing control to input and output driver to ensure its' compatibility with different speed devices.
(b) changed the data input level from TTL to CMOS to add noise margins.
(c) added learning circuit to the parity generating circuit to make sure its compatibility to both ODD and EVEN parity check.
(d) made 'CAS' before *RAS', Hidden' Refresh compatible.
(e) added input latch to make a clear input speed limit so that the ECA won't be affected by any unstable input signals.
(f) modified parity check circuit such that it generates parity error if the ECA failed.
(g) modified the internal control logic to improve its turn on/off lead time.
7. The methodology, as claimed in claim 1, whereas the RSIMC with the same error pattern will then be grouped together along with the ECA for assembly into memory boards, memory cards or SIMM modules.
8. The methodology, as claimed in claim 1, whereas the ECA is a redundant backup / switch method which corrects all kinds of RSIMC errors as long as there is only one single defect in the same memory address at a time.
9. The methodology, as claimed in claim 1, whereas the corrected RSIMC memory board, memory cards or SIMM modules would become computer grade compatible and would function as normal memories for computer (or computer sub-systems) usages and applications. It will only have a slight adverse effect on the computers' speed performance.
10. Computers), as claimed in claim 9, include(s) any device with a central processing unit, an input system, output system, memory system and a data bus connecting the central processing unit to the memory system.
11. Redundant Error Detection / Correction Algorithm, as claimed in claim 1, refers to any kinds of error correction method, procedure or algorithm. They include but not limited to HAMING CODE, OR MODIFY HAMING CODE.
12. The methodology, as claimed in claim 1, is the integration of any the ECC technology on computer's memory or memory sub-system for computers) with or without built in ECC capacity.
13. The methodology, as claimed in claim 1, is the integration of any the ECC technology on a computer's memory cards, memory boards, or SIMM modules such that the host computer will access the memory cards, memory boards, or SIMM modules as good quality memory chips. There is no limit on the address size of the memory chip/ card/ module or SIMM that it can correct.
14. On Board ECC as claimed in claim 1, means the ECC is done within the memory cards, memory modules, SIMM, or memory subsystems for the purpose of upgrading the reduced specification memory chips to become computer grade compatible such that the corrected memory cards, modules or SIMM can be used in a computer environment.
15. Built-in ECC, as mentioned in claim 12, refers to the computer with ECC capacity built inside the computer main-board for the purpose of increasing or enhancing the reliability of the memory access. To be more specific, built-in ECC is for fault-tolerance purpose.
16. The implementation of the methodology as in claim 1, will effectively replace the good quality memory card, memory board or SIMM modules with the Reduced Specification Memory Chips and the ECA such that the only effect on the computer is a slight adverse effect on the computer's speed performance but will not lower the fault-tolerance level of the computer system.
17. The purpose of the methodology, as claimed in claim 1, is to upgrade and to utilize the Reduced Specification Memory Chips in computer applications, not to increase the reliability of a computer system.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US30340094A | 1994-09-09 | 1994-09-09 | |
| CA2,131,735 | 1994-09-09 | ||
| CA 2131735 CA2131735A1 (en) | 1994-09-09 | 1994-09-09 | Board errors correction apparatus |
| US08/303,400 | 1994-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1996007969A1 true WO1996007969A1 (en) | 1996-03-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CA1995/000517 WO1996007969A1 (en) | 1994-09-09 | 1995-09-08 | On board error correction apparatus |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO1996007969A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0824237A3 (en) * | 1996-08-05 | 1999-10-06 | Texas Instruments Inc. | Audio RAM having error detection and correction function |
Citations (5)
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|---|---|---|---|---|
| US3814922A (en) * | 1972-12-01 | 1974-06-04 | Honeywell Inf Systems | Availability and diagnostic apparatus for memory modules |
| US3897626A (en) * | 1971-06-25 | 1975-08-05 | Ibm | Method of manufacturing a full capacity monolithic memory utilizing defective storage cells |
| US4612640A (en) * | 1984-02-21 | 1986-09-16 | Seeq Technology, Inc. | Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array |
| EP0520676A2 (en) * | 1991-06-28 | 1992-12-30 | STMicroelectronics, Inc. | Memory subsystem with error correction |
| US5355377A (en) * | 1993-11-23 | 1994-10-11 | Tetra Assoc. Inc. | Auto-selectable self-parity generator |
-
1995
- 1995-09-08 WO PCT/CA1995/000517 patent/WO1996007969A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3897626A (en) * | 1971-06-25 | 1975-08-05 | Ibm | Method of manufacturing a full capacity monolithic memory utilizing defective storage cells |
| US3814922A (en) * | 1972-12-01 | 1974-06-04 | Honeywell Inf Systems | Availability and diagnostic apparatus for memory modules |
| US4612640A (en) * | 1984-02-21 | 1986-09-16 | Seeq Technology, Inc. | Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array |
| EP0520676A2 (en) * | 1991-06-28 | 1992-12-30 | STMicroelectronics, Inc. | Memory subsystem with error correction |
| US5355377A (en) * | 1993-11-23 | 1994-10-11 | Tetra Assoc. Inc. | Auto-selectable self-parity generator |
Non-Patent Citations (2)
| Title |
|---|
| "Swapping Failing Bits in 40-Pin Error Correcting SIMMS", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 37, no. 9, September 1994 (1994-09-01), NEW YORK US, pages 595 - 596 * |
| R. NASS: "MEMORY-EXPANSION SIMMS AND ERROR CORRECTION", ELECTRONIC DESIGN, vol. 42, no. 5, 7 March 1994 (1994-03-07), HASBROUCK HEIGHTS, NEW JERSEY, USA, pages 40, XP000441321 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0824237A3 (en) * | 1996-08-05 | 1999-10-06 | Texas Instruments Inc. | Audio RAM having error detection and correction function |
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