[go: up one dir, main page]

WO1989002192A1 - Circuit de condensateur a commutation - Google Patents

Circuit de condensateur a commutation Download PDF

Info

Publication number
WO1989002192A1
WO1989002192A1 PCT/AU1988/000331 AU8800331W WO8902192A1 WO 1989002192 A1 WO1989002192 A1 WO 1989002192A1 AU 8800331 W AU8800331 W AU 8800331W WO 8902192 A1 WO8902192 A1 WO 8902192A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitors
capacitor
circuit
multiplexed
switched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/AU1988/000331
Other languages
English (en)
Inventor
Joseph Sylvester Chang
Yit Chow Tong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Melbourne
Original Assignee
University of Melbourne
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Melbourne filed Critical University of Melbourne
Publication of WO1989002192A1 publication Critical patent/WO1989002192A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00—Networks using time-varying elements, e.g. N-path filters
    • H03H19/004—Switched capacitor networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • G06G7/186—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop
    • G06G7/1865—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop with initial condition setting

Definitions

  • the present invention relates to electrical circuits incorporating shared capacitors and more particularly to Time-Multiplexed Switched Capacitor circuits/ such as filter banks, in which certain capacitors may be arranged to be shared.
  • the Switched Capacitor circuit of the present invention may be associated with developments disclosed in applicant's pending patent applications PI 6107 (Full Wave Rectifier) filed on 24 December 1987 and PI 8595 (Filter
  • SC circuits are relatively efficient in terms of chip area and power dissipation for implementing monolithic filters, many complex on-chip systems requiring a large number of high order filters employ SC design techniques.
  • An example of such a system is a spectrum analyzer for automatic speech recognition, vocoders, sensory aids for the deaf, and the like.
  • the spectrum analyzer may comprise a Bandpass filter bank, a bank of Full-Wave Rectifiers, and a Lowpass filter bank.
  • An object of the present invention is to address the chip area problem in prior art SC filters and filter banks, and to offer a capacitor sharing technique which may reduce
  • the present invention may be applicable to a Bandpass filter bank for a spectrum analyzer which may be compatible with micropower and Time-Multiplexed designs.
  • a second order filter is termed a biquadratic filter section (biquad) .
  • Synthesis of high order filters typically employ biquads as their workhorse where these filters are often realized as a cascade of biquads.
  • SC filters comprise operational amplifiers (op amps), capacitors, and switches controlled by clock signals.
  • a capacitor and its associated switches is termed a Capacitor Switch Network (CSN) .
  • CSN Capacitor Switch Network
  • the transfer function of a SC filter may be specified by clock frequency, capacitor ratios and circuit topology. All useful SC circuits preferably are parasitic insensitive or at least parasitic compensated. Clock signals used in implementing SC circuits depend on the realization method adopted. Most Time-Multiplexed SC filters and filter banks employ a single biphasic clock and a number of local clock periods.
  • the biphasic clock may comprise non-overlapping even (half) and odd (half) clock phases.
  • a global clock period (inverse of the sampling frequency) is divided into a number of non-overlapping local clock periods.
  • a different SC subcircuit usually one channel of a filter bank, may be serviced in a local clock period.
  • the odd (or even) phase of the biphasic clock may coincide with the first half of the local clock period, while the even (or odd) phase may coincide with the latter half of the local clock period.
  • each capacitor in a monolithic SC circuit may be (typically) 0.3 picofarad and is termed a unity (valued) capacitor.
  • each capacitor in a monolithic realization preferably is made up of a number of unity capacitors and an additional non-integer capacitor having a value between unity and two (unit capacitors) . For example, if a capacitor of 3.5 units is desired, 2 unity capacitors and a 1.5 non-integer capacitor are combined.
  • Integrating capacitors are capacitors that are connected across the output and inverting input terminals of an op amp. Integrating capacitors may be switched in during the entire local clock period in Time-Multiplexed circuits. All other capacitors are non-integrating capacitors which are charged and discharged by means of a biphasic clock signal- during a local clock period. Generally speaking integrating capacitors are required for individual biquads in Time-Multiplexed filters because they are used to retain the state of the filter. Thus, with some exceptions, integrating capacitors may not be shared between Time-Multiplexed biquads. Non-integrating capacitors, on the other hand, may be shared between all Time-Multiplexed biquads.
  • Synthesis of a SC filter may include dynamic range and capacitor scaling.
  • the former may involve scaling the closed-loop gains of each op amp such that the output of all op amps peak to a fixed predefined value; hence optimizing dynamic range.
  • the latter may involve scaling the values of a set of capacitors which have one of their terminals connected to the non-inverting input of an op amp. The smallest capacitor of that set may be assigned a unity value as previously described. In this manner, the total capacitance required may be optimized (to a minimum) .
  • Capacitors of a SC Bandpass filter bank generally are unequal for different channels due to the varied transfer function requirements of the different channels.
  • One prior art design method involves use of resistive strings to provide required voltage division such that capacitor values are made equal for all channels.
  • the present invention may provide an improved capacitor sharing arrangement by means of which the total capacitance or total number of unit capacitors required in a circuit may be significantly reduced.
  • the advantages of the present invention may be achieved without incurring significant overheads, such as, many additional clocking signals.
  • the present invention may provide in one form a switched capacitor circuit including a multiplicity of capacitors and switches.
  • the multiplicity of capacitors may include a first plurality of capacitors and a second plurality of capacitors.
  • a first common capacitor may be shared by the first and second plurality of capacitors and a second common capacitor may be shared by the said second plurality of capacitors.
  • the above arrangement may permit the total capacitance of the circuit to be significantly reduced thereby enabling corresponding savings in chip area in integrated circuits and component savings in discrete component circuits.
  • the total, capacitance in a given capacitor array may be
  • the present invention is particularly applicable to multiplexed circuits comprising an array of capacitors including first and second common capacitors and first and second pluralities of capacitors.
  • the capacitors may be switched into and out of different multiplexed time periods of the multiplexed circuits.
  • the first common capacitor may be switched into the circuit when any one of the first plurality of capacitors is involved in the operation of the multiplexed circuit thus reducing the size of that one 0 capacitor of the first plurality of capacitors.
  • the first and second common capacitors may be switched into the circuit when any one of the second plurality of capacitors is involved in the operation of the multiplexed circuit.
  • the capacitor sharing arrangement of the present invention may be advantageously applied to non-integrating capacitors in the circuit and in special cases, integrating capacitors.
  • the capacitor sharing arrangement of the present 0 invention may allow the number of non-integrating capacitors in a capacitor array to be substantially reduced.
  • the arrangement increases the extent of capacitor sharing and may result in simplified layout and possible improvement in noise performance of the circuit.
  • a Time-Multiplexed Switched Capacitor circuit having a multiplicity of capacitors, at least one of said capacitors being adapted to be switched into and out of said circuit during at least some local time periods of a global time period, said circuit including: an array comprising at least one capacitor; and a common capacitor adapted to be switched into said circuit during a plurality of local time periods fewer than the number of local time periods in said global time period; such that said common capacitor is shared by said at least one capacitor of said array during said plurality of local time periods.
  • a Switched Capacitor circuit having a multiplicity of capacitors and associated switches adapted to switch said capacitors into and out of said circuit, said multiplicity of capacitors including a first plurality of capacitors, a second plurality of capacitors, a first common capacitor adapted to be shared by at least one of said first and said second pluralities of capacitors and a second common capacitor adapted to be shared by said at least one of said second plurality of capacitors.
  • a Time-Multiplexed circuit comprising a multiplicity of elements adapted to be switched into and out of said circuit during at least some local time periods of a global time period, said circuit including a first array of elements, a second array of elements, a first common element adapted to be switched into said circuit during said global time period such that said first common element is shared by at least one element of said first and second arrays during said global time period and a second common element adapted to be switched into said circuit during a plurality of local time periods fewer than the number of local time periods in said global time period such that said second common element is shared by at least one element of said second array during said plurality of local time periods.
  • a Time-Multiplexed circuit comprising a multiplicity of elements and associated switches adapted to switch said elements into and out of
  • said circuit during at least some local time periods of a global time period, said multiplicity of elements including a first plurality of elements, a second plurality of elements, a first common element which .is adapted to be shared by at least one of said first and second pluralities of elements during said global time period and a second common element which is ' adapted to be shared by at least one of said second plurality of elements during a plurality of local time periods fewer than the number of local time periods in said global time period.
  • the present invention may provide a fourth order per channel 24-channel Bandpass filter bank.
  • the fourth order per channel 24-channel Bandpass filter bank may comprise a cascade of two Time-Multiplexed biquads.
  • Clocking signals may comprise 24 local clock periods wherein one filter channel is serviced in one local clock period; a biphasic clock comprising non-overlapping even and odd phases; and an additional clock period.
  • Each Time-Multiplexed biquad may comprise two op amps, 5 CSN arrays and 1 CSN.
  • Three CSN arrays may each comprise 24 capacitors and associated switches.
  • One CSN array may comprise 26 capacitors and associated switches.
  • the remaining CSN array may comprise 2 capacitors and associated switches.
  • SUBSTITUTE SHEET Figure 1(a) is a circuit diagram of an unmultiplexed biquad to which the present invention may be applied;
  • Figure 1(b) shows the biphasic clock used in the circuit of figure 1(a);
  • Figure 1(c) depicts the signal-flow-graph associated with the circuit of figure 1(a), its transfer function characteristics, and DC (frequency) transfer functions from the input of op amp 1 and op amp 2 to the output of the biquad;
  • Figure 2(a) is a schematic diagram of a 24-channel Time-Multiplexed biquad utilizing prior art techniques;
  • Figure 2(b) shows the clocking signal used in the filter bank realization of figure 2(a);
  • Figures 3(a,) and 3(a ) show schematic diagrams • - • ⁇ -° » of two CSN arrays of a Time-Multiplexed biquad embodying - the principles of the present invention.
  • Figure 3(b) shows the clocking signals used in the filter bank realization of figure .2(a) as modified by the
  • the biquad comprises op amps 1 and 2 and CSNs
  • the integrating capacitor of CSN *D* is connected across the inverting input and output terminals of op amp 1.
  • the non-integrating capacitor of CSN *A* has one terminal connected to the output of op amp 1 and the other terminal connected to the inverting input of op amp 2.
  • the non-integrating capacitor of CSN "J* has one terminal connected to the input of the biquad and the other terminal connected to the inverting input of op amp 2.
  • the integrating capacitor of CSN 'B* and non-integrating capacitor of CSN 'F' are connected across the inverting input and output of op amp 2.
  • the non-integrating capacitor of CSN 'TJ' has one terminal connected to the output of op amp 2 and the other terminal connected to the inverting input of op amp 1.
  • the output of op amp 2 (V out) is the output of the biquad.
  • the op amps of the biquad may be Time-Multiplexed to service different channels of a filter bank by simply connecting different capacitors pertaining to the relevant channels during the appropriate times.
  • This general approach would subsequently require 2 op amps and 6 CSN arrays.
  • the number of CSN arrays may be reduced so that overall hardware savings due to
  • Time-Multiplexing are op amps and capacitors. A practical implementation using prior art techniques is referred to for comparative purposes.
  • Non-integrating capacitors of CSNs 'A' and 'J' are discharged to virtual ground of an op amp and non-integrating capacitor of CSN 'U' is discharged to analog ground during the even phase of the biphasic clock, or equivalently, the latter half of the local clock period.
  • Non-integrating capacitors of CSN 'F' are discharged to analog ground during the odd phase.
  • the operation of this CSN array is as follows. During the first local clock period Pd 1 when channel 1 of the Bandpass filter bank is serviced, capacitor 'Al' is connected in parallel with common capacitor 'AO' so that
  • the capacitor of CSN 'U' is the smallest capacitor (unity valued) associated with the inverting input of op amp 1 in channels 1 to 14 of the Time-Multiplexed Bandpass biquad, after which the integrating capacitor of CSN 'D' becomes unity valued.
  • the value of capacitors of CSN 'U' does not remain invariant for all channels, unlike 'J', it may not be shared. Consequently, individual capacitors for CSN 'U' are required for each filter channel (as tabulated in Table 1) .
  • the DC (frequency) transfer function from the input of op amp 1 and op amp 2 to the output of the biquad are -1 and 0 respectively.
  • the DC offsets for this Time-Multiplexed Bandpass biquad are independent of capacitor ratios.
  • DC offsets between the different Time-Multiplexed Bandpass filter channels may be made small without the use of resistive strings. It is
  • a fourth order per channel 24-channel Bandpass filter bank may comprise a cascade of two Time-Multiplexed biquads shown in figure 2(a).
  • the capacitor sharing technique embodying the present invention will now be described with reference to CSN arrays 'A* and *U' .
  • CSN array 'A' first.
  • Capacitor sharing may be enhanced by connecting a second common capacitor 'AA' during periods Pd 9 to Pd 24 so that the residual required capacitors 'A9' to 'A24' are reduced by both the common capacitors 'AO' and 'AA* .
  • the modified CSN array 'A* is depicted in figure 3(a,).
  • capacitors 'AO' plus 'AA* plus *Ax' sums to the specified value capacitor for CSN 'A' of that channel.
  • the values of the mpdified 'A' CSN array is depicted in Table 2 below.
  • the second common capacitor *AA' is connected in circuit by means of an additional clock signal Pd 9-24 which goes high during Pd 9 and low at the end of Pd 24 (refer figure 3(b)).
  • Pd 9-24 which goes high during Pd 9 and low at the end of Pd 24
  • the second common capacitor 'AA' is shared between channels 9 to 24, the total number of unit capacitors required for CSN array 'A' is reduced by a notable 165 units. This represents a 23% reduction of the total number of capacitors for the biquad (or a 65% reduction of CSN array 'A').
  • the area reduction may be of the order of 15% for the Time-Multiplexed biquad.
  • the lower figure accounts for an area due to interconnections and the
  • Time-Multiplexed biquad embodying the principles of the present invention may be expected to be of the order of 20% in a monolithic implementation.
  • a fourth order per channel Bandpass filter bank may comprise a cascade of two Time-Multiplexed biquads each of which may comprise the Time-Multiplexed biquad depicted in figure 2(a) as modified by the CSN arrays shown in figure 3(a).
  • the capacitor sharing methodology of the present invention may provide for significant capacitor saving;, simplification of layout and interconnection, and improved noise performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

Dans un circuit de condensateur à commutation avec multiplexage temporel, certains condensateurs sont partagés pendant des périodes de temps local d'une période de temps global, pour permettre une réduction de la capacitance totale du circuit. On peut obtenir des économies correspondantes dans la superficie occupée par les puces dans l'implantation d'un circuit intégré et des économies de composants dans une implantation non intégrée. La présente invention s'applique en particulier à un circuit avec multiplexage comprenant un réseau de condensateurs constitué par des premier et second condensateurs communs et par des premier et second groupes de plusieurs condensateurs. Les condensateurs peuvent par commutation être inclus dans le circuit avec multiplexage et exclus de celui-ci pendant différentes périodes de temps local. Le premier condensateur commun peut par commutation être inclus dans le circuit, lorsque n'importe lequel des condensateurs du premier groupe participe au fonctionnement du circuit avec multiplexage, réduisant ainsi la grandeur de ce condensateur appartenant au premier groupe de condensateurs. De même, les premier et second condensateurs communs peuvent par commutation être inclus dans le circuit, lorsque n'importe lequel des condensateurs du second groupe participe au fonctionnement du circuit multiplexé.
PCT/AU1988/000331 1987-08-28 1988-08-26 Circuit de condensateur a commutation Ceased WO1989002192A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AUPI4081 1987-08-28
AU408187 1987-08-28

Publications (1)

Publication Number Publication Date
WO1989002192A1 true WO1989002192A1 (fr) 1989-03-09

Family

ID=3694540

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AU1988/000331 Ceased WO1989002192A1 (fr) 1987-08-28 1988-08-26 Circuit de condensateur a commutation

Country Status (1)

Country Link
WO (1) WO1989002192A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0511536A1 (fr) * 1991-04-30 1992-11-04 STMicroelectronics S.r.l. Circuit intégré comprenant un réseau de composants passifs ajustable
EP0599557A3 (en) * 1992-11-20 1995-09-20 Nec Corp Switched capacitor circuit.
EP0747849A1 (fr) * 1995-06-07 1996-12-11 Landis & Gyr Technology Innovation AG Intégrateur à capacités commutées et à polarité contrÔlable

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0047409A2 (fr) * 1980-09-08 1982-03-17 American Microsystems, Incorporated Compensation de tension de décalage pour intégrateurs à capacité commutée
GB2084835A (en) * 1980-10-01 1982-04-15 Asulab Sa Multiplexed electrical signal processor
GB2085684A (en) * 1980-10-20 1982-04-28 Philips Nv An arrangement for generating a sequence of values of an electrical quantity
EP0209948A1 (fr) * 1985-07-18 1987-01-28 Koninklijke Philips Electronics N.V. Circuit multiplicateur à condensateurs-commutés

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0047409A2 (fr) * 1980-09-08 1982-03-17 American Microsystems, Incorporated Compensation de tension de décalage pour intégrateurs à capacité commutée
GB2084835A (en) * 1980-10-01 1982-04-15 Asulab Sa Multiplexed electrical signal processor
GB2085684A (en) * 1980-10-20 1982-04-28 Philips Nv An arrangement for generating a sequence of values of an electrical quantity
EP0209948A1 (fr) * 1985-07-18 1987-01-28 Koninklijke Philips Electronics N.V. Circuit multiplicateur à condensateurs-commutés

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0511536A1 (fr) * 1991-04-30 1992-11-04 STMicroelectronics S.r.l. Circuit intégré comprenant un réseau de composants passifs ajustable
US6104235A (en) * 1991-04-30 2000-08-15 Stmicroelectronics S.R.L. Integrated circuit with trimmable passive components
EP0599557A3 (en) * 1992-11-20 1995-09-20 Nec Corp Switched capacitor circuit.
EP0747849A1 (fr) * 1995-06-07 1996-12-11 Landis & Gyr Technology Innovation AG Intégrateur à capacités commutées et à polarité contrÔlable
US5689206A (en) * 1995-06-07 1997-11-18 Landis & Gyr Technology Innovation Ag Sc-integrator with switchable polarity

Similar Documents

Publication Publication Date Title
US6765517B1 (en) Variable order sigma-delta modulator
da Franca Nonrecursive polyphase switched-capacitor decimators and interpolators
Lin et al. Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits
US6437720B1 (en) Code independent charge transfer scheme for switched-capacitor digital-to-analog converter
Young et al. MOS switched-capacitor analog sampled-data direct-form recursive filters
US5168461A (en) Switched capacitor differentiators and switched capacitor differentiator-based filters
Ansari et al. Efficient sampling rate alteration using recursive (IIR) digital filters
US5182521A (en) Time-multiplexed switched capacitor circuit having reduced capacitance
US6441762B2 (en) Circuit device for cancelling out spurious pulses in a switched capacitance low-pass filter, and a filter incorporating it
EP0015343B1 (fr) Filtre à capacités commutées et procédé pour sa fabrication
WO1989002192A1 (fr) Circuit de condensateur a commutation
DE60033300T2 (de) Verfahren und vorrichtung zur mehrkanaligen signalverarbeitung
JP3465951B2 (ja) 反転遅延回路
AU2323188A (en) Switched capacitor circuit
Allstot Simplified MOS switched capacitor ladder filter structures
US7047263B2 (en) Fast-settling digital filter and method for analog-to-digital converters
US6140951A (en) Double sampled switched capacitor low pass multirate filter for a ΣΔ D/A converter
US4763088A (en) Switching scheme for switched capacitor filters
US4745594A (en) Offset-compensated switched-capacitor filter for TDM multichannel analog signals
Pereira et al. Optimum design and implementation of IIR SC filters using small-order FIR cells
Jovanović-Doleček Design of multiplierless comb compensators with magnitude response synthesized as sinewave functions
WO1989006069A1 (fr) Circuits condensateurs commutes
Dolecek et al. Multiplierless two-stage comb structure with an improved magnitude characteristic
US5097155A (en) Switched-current differentiators and filters
US5453741A (en) Sampling frequency converter

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LU NL SE