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EP0747849A1 - Intégrateur à capacités commutées et à polarité contrÔlable - Google Patents

Intégrateur à capacités commutées et à polarité contrÔlable Download PDF

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Publication number
EP0747849A1
EP0747849A1 EP96103748A EP96103748A EP0747849A1 EP 0747849 A1 EP0747849 A1 EP 0747849A1 EP 96103748 A EP96103748 A EP 96103748A EP 96103748 A EP96103748 A EP 96103748A EP 0747849 A1 EP0747849 A1 EP 0747849A1
Authority
EP
European Patent Office
Prior art keywords
switch
capacitor
amplifier
connection
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96103748A
Other languages
German (de)
English (en)
Inventor
Michel Schaller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Landis and Gyr AG
Original Assignee
Landis and Gyr Technology Innovation AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Landis and Gyr Technology Innovation AG filed Critical Landis and Gyr Technology Innovation AG
Publication of EP0747849A1 publication Critical patent/EP0747849A1/fr
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • G06G7/186—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop

Definitions

  • the invention relates to a SC integrator polarity inversion according to the preamble of claim 1.
  • a SC integrator (S witched C apacity integrator) is known to be an integrator with switched capacitors.
  • Such an SC integrator is preferably used in sigma-delta modulators, e.g. B. are part of analog / digital converters that are used in electricity meters to analog measurement signals such. B. a mains voltage and an associated electrical current, or their product, such as. B. convert an electrical power belonging to the current in question into digital values.
  • the invention has for its object to improve the known SC integrator so that it, while maintaining its advantages, requires a storage capacitor, the capacitance value is significantly lower and thus space-saving and cheaper in an integrated circuit, for. B. can be produced by means of CMOS technology.
  • the known SC integrator shown in FIG. 1 and constructed by means of switched capacitances is provided with at least one switch arrangement 1 and one integration arrangement 2, which contains an amplifier 3, which is connected to at least one circuit network 4, through which a non-inverting output of the amplifier 3 is connected via an integration capacitor 5 to an inverting input of the amplifier 3 and in which a first connection of a storage capacitor 6 is connected to ground, the second connection of which is on the one hand via a first switch S1 to the non-inverting output of the amplifier 3 and on the other hand via a second Switch S2 is connected to the switch arrangement 1.
  • the latter in turn contains a switching capacitor 7, the first connection of which is connected to the ground or to the inverting input of the amplifier 3 by means of a third and fourth switch S3 and S4, while its second connection is connected to the input voltage Vin and by means of a fifth switch S5 of a sixth switch S6 is connected to a further voltage potential Vm, which is equal to the ground potential in the known SC integrator.
  • a connection in the switch arrangement 1 from the second connection of the switching capacitor 7 via a seventh switch S7 to a reference voltage Vref.
  • the capacitance value Cs of the storage capacitor 6 in the known integrator must be twice as large as the capacitance value Ci of the integration capacitor 5.
  • the amplifier 3 is preferably an operational amplifier, the non-inverting input of which is connected to ground. Its non-inverting output is connected to a non-inverting input of a comparator 8, the inverting input of which is connected to ground. Every time an output voltage Vo of the amplifier 3 exceeds a value zero, a logic value "1" appears at the output of the comparator 8, which inverts the polarity of the reference voltage Vref via a control circuit, not shown, so that the output voltage Vo decreases again and the Logic value "1" at the output of the comparator 8 disappears again as soon as the output voltage Vo falls below the value zero.
  • the integration of the algebraic sum Vin + Vref of the input voltage Vin and the reference voltage Vref is carried out in the SC integrator, both of which can be both positive and negative, so that a total of four combinations + / +, - / -, +/- and - / + are possible.
  • the input voltage + Vin or -Vin are integrated in succession during one sampling period of the integrator and the reference voltage + Vref or -Vref is integrated during another sampling period. If the two switches S5 and S4 are closed, the amplifier 3, which in this case is connected as an inverting amplifier, works as an inverting integrator and its output voltage Vo is then the integrated -Vin voltage when switches S1 and S2 are open.
  • the + Vin voltage is integrated in two phases.
  • the switching capacitor 7 is charged with the input voltage Vin via the closed switches S5 and S3 during a sampling period, which has no effect on the amplifier 3 since the switch S4 is not closed.
  • switches S6 and S7 are open during this phase.
  • the two switches S5 and S3 are open and the two switches S4 and S6 are closed, which has the consequence that on the one hand the polarity of the voltage Vin present via the switching capacitor 7 is inverted and on the other hand this inverted voltage in the amplifier operating as an inverting integrator 3 is inverted again so that a non-inverted integration voltage appears at the output of the latter.
  • the output voltage Vo of the amplifier 3 which is at the same time the voltage across the integration capacitor 5, charges the storage capacitor 6 with a charge Cs ⁇ Vo when the switch S2 is open via the closed switch S1, which charge is then reversed in the next phase
  • the switch S1 is open, the polarity is reloaded into the integration capacitor Ci via the closed switch S2, so that its charge is totally identical
  • the voltage present across the integration capacitor 5 has, as intended, changed its polarity and thus changed its value from + Vo to -Vo.
  • the first variant of the SC integrator according to the invention shown in FIG. 2 is constructed similarly to the known SC integrator shown in FIG. 1 with the difference that the second connection of the storage capacitor 6 is via the second Switch S2 is connected directly to the first connection of the circuit capacitor 7.
  • the first variant there is also the connection via the seventh switch S7 between the reference voltage Vref and the second connection of the switching capacitor 7 and the further voltage potential Vm is equal to the ground potential.
  • the sum Cf + Cs of a capacitance value Cf of the circuit capacitor 7 and a capacitance value Cs of the storage capacitor 6 is twice the capacitance value 2Ci of the integration capacitor 5.
  • each integration period consists of two time-graded partial integrations, the input voltage Vin being integrated in the first and the reference voltage Vref being integrated positively or negatively in the second.
  • the number of partial integrations per integration period can be reduced to one partial integration per integration period using the second or third variant described below. H. the input voltage Vin and the reference voltage Vref are integrated at the same time, so that the required speed of the amplifier 3 in these two variants is lower than that in the first variant.
  • the second variant of the SC integrator according to the invention shown in FIG. 3 is constructed similarly to the first variant.
  • the further voltage potential Vm is again the ground potential.
  • the switch arrangement 1 contains a further switch S8 and a further switching capacitor 9.
  • the first connections of the two switching capacitors 7 and 9 are connected to one another and a second connection of the further switching capacitor 9 is connected to the ground via the further switch S8.
  • the connection through the seventh This time, switch S7 is present between the reference voltage Vref and the second connection of the further switching capacitor 9.
  • the sum Cf + Cf1 + Cs of capacitance values Cf and Cf1 of the two circuit capacitors 7 and 9 and of the capacitance value Cs of the storage capacitor 6 is equal to twice the capacitance value 2Ci of the integration capacitor 5 in the second variant.
  • the capacitance values Cf and Cf1 of the two circuit capacitors 7 and 9 are preferably of the same size.
  • the three capacitors 6. 7 and 9 are connected in parallel when the switches S2, S6 and S8 are closed.
  • the third variant of the SC integrator according to the invention shown in FIG. 4 is constructed similarly to the first variant.
  • the connection via the seventh switch S7 between the reference voltage Vref and the second connection of the switching capacitor 7 is again present in the first switch arrangement 1.
  • the third variant differs as follows: This time, the further voltage potential Vm is the reference voltage -Vref provided with the reverse polarity.
  • the second connection of the switching capacitor 7 is additionally connected to the input voltage voltage -Vin provided with the reverse polarity by means of a further switch S9.
  • the amplifier 3 has a push-pull output and its non-inverting input is no longer connected to ground.
  • the amplifier 3 is also connected to a second circuit network 4a and a second switch arrangement 1a, both of which are connected to one another and to the amplifier 3 in a similar way to that the first two are connected to each other and to the amplifier 3 with the difference that the inverting input of the amplifier 3 is due to its non-inverting input and the non-inverting input Output of the amplifier 3 is replaced by its inverting output.
  • the two circuit networks 4 and 4a and the two switch arrangements 1 and 1a are each constructed identically.
  • the switches S1 to S7 and S9 are controlled in the two circuit networks 4 and 4a or in the two switch arrangements 1 and 1a in such a way that switches of the same name are switched simultaneously during operation.
  • the voltages Vin, -Vref, Vref and -Vin or -Vin, Vref, -Vref and Vin connected to the same names, ie identically numbered switches S5, S6, S7 and S9 are equal in the two switch arrangements 1 and 1a and of opposite polarity .
  • the inverting output of amplifier 3 is connected to the inverting input of comparator 8, which input is therefore no longer connected to ground.
  • the sum Cf + Cs of the capacitance values Cf and Cs of the circuit capacitor 7 of the first and second switch arrangement 1 and 1a and the storage capacitor 6 of the first and second circuit network 4 and 4a is in each case equal to twice the capacitance value 2Ci of the integration capacitor 5 of the relevant first or second circuit network 4 or 4a.
  • the second variant according to FIG. 3 can also be constructed as a differential solution.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Amplifiers (AREA)
EP96103748A 1995-06-07 1996-03-09 Intégrateur à capacités commutées et à polarité contrÔlable Ceased EP0747849A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH166295 1995-06-07
CH1662/95 1995-06-07

Publications (1)

Publication Number Publication Date
EP0747849A1 true EP0747849A1 (fr) 1996-12-11

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ID=4215698

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96103748A Ceased EP0747849A1 (fr) 1995-06-07 1996-03-09 Intégrateur à capacités commutées et à polarité contrÔlable

Country Status (2)

Country Link
US (1) US5689206A (fr)
EP (1) EP0747849A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923204A (en) * 1996-11-08 1999-07-13 Nokia Mobile Phones Limited Two phase low energy signal processing using charge transfer capacitance

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5936433A (en) * 1998-01-23 1999-08-10 National Semiconductor Corporation Comparator including a transconducting inverter biased to operate in subthreshold
US6064326A (en) * 1998-03-30 2000-05-16 Silicon Laboratories, Inc. Analog-to-digital conversion overload detection and suppression
US6061009A (en) * 1998-03-30 2000-05-09 Silicon Laboratories, Inc. Apparatus and method for resetting delta-sigma modulator state variables using feedback impedance
US6249240B1 (en) * 1998-08-28 2001-06-19 Texas Instruments Incorporated Switched-capacitor circuitry with reduced loading upon reference voltages
DE69917479T2 (de) * 1998-10-26 2005-06-02 Janez Pirs Ansteuerungsschema und elektronischer schaltkreis für ein elektooptisches lcd-schaltelement
JP2006303671A (ja) * 2005-04-18 2006-11-02 Digian Technology Inc 積分器およびそれを使用する巡回型ａｄ変換装置
US9231539B2 (en) 2013-03-06 2016-01-05 Analog Devices Global Amplifier, a residue amplifier, and an ADC including a residue amplifier
US10886940B1 (en) * 2020-06-03 2021-01-05 Qualcomm Incorporated Circuits and methods providing a switched capacitor integrator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989002192A1 (fr) * 1987-08-28 1989-03-09 The University Of Melbourne Circuit de condensateur a commutation
EP0607712A1 (fr) * 1993-01-20 1994-07-27 Schlumberger Industries S.A. Circuit intégrator modulé en fréquence

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4496858A (en) * 1981-12-24 1985-01-29 Motorola, Inc. Frequency to voltage converter
FI88562C (fi) * 1989-09-19 1993-05-25 Nokia Mobile Phones Ltd Integrerad, av driftsspaenning oberoende dynamisk amplitudbegraensare
US5331222A (en) * 1993-04-29 1994-07-19 University Of Maryland Cochlear filter bank with switched-capacitor circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989002192A1 (fr) * 1987-08-28 1989-03-09 The University Of Melbourne Circuit de condensateur a commutation
EP0607712A1 (fr) * 1993-01-20 1994-07-27 Schlumberger Industries S.A. Circuit intégrator modulé en fréquence

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHANG JOU I ET AL: "THE CHARACTERISTIC COMPARISON OF FULLY DIFFERENTIAL SWITCHED CAPACITOR BIQUADS", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, PORTLAND, MAY 8 - 11, 1989, vol. 3 OF 3, 8 May 1989 (1989-05-08), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 1712 - 1715, XP000131392 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923204A (en) * 1996-11-08 1999-07-13 Nokia Mobile Phones Limited Two phase low energy signal processing using charge transfer capacitance

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US5689206A (en) 1997-11-18

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