US9613961B2 - Field-effect transistor and semiconductor device - Google Patents
Field-effect transistor and semiconductor device Download PDFInfo
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- US9613961B2 US9613961B2 US15/066,880 US201615066880A US9613961B2 US 9613961 B2 US9613961 B2 US 9613961B2 US 201615066880 A US201615066880 A US 201615066880A US 9613961 B2 US9613961 B2 US 9613961B2
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- 230000005669 field effect Effects 0.000 title claims abstract description 41
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
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- H01L27/0924—
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- H01L21/845—
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- H01L27/1211—
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- H01L29/1604—
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- H01L29/165—
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- H01L29/2003—
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- H01L29/2006—
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- H01L29/205—
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- H01L29/225—
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- H01L29/786—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
- H10D62/402—Amorphous materials
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- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
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- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/826—Heterojunctions comprising only Group II-VI materials heterojunctions, e.g. CdTe/HgTe heterojunctions
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/011—Manufacture or treatment comprising FinFETs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
- H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
- H10D30/6218—Fin field-effect transistors [FinFET] of the accumulation type
Definitions
- a method for varying the material of a gate electrode from an n-type junctionless FET to a p-type junctionless FET and adjusting the work function of the gate electrode of each of the FETs there is a method for varying the material of a gate electrode from an n-type junctionless FET to a p-type junctionless FET and adjusting the work function of the gate electrode of each of the FETs.
- a field-effect transistor 1 of the present embodiment is provided above a semiconductor substrate 80 with an insulating film 81 therebetween.
- the semiconductor substrate 80 is a silicon (Si) substrate and the insulating film 81 is a film that is made of silicon oxide.
- a structure of the semiconductor substrate 80 and the silicon oxide film 81 on the semiconductor substrate will also be referred to as a substrate.
- the insulating film 81 made of silicon oxide film is not limited to SiO 2 formed by oxidizing the semiconductor substrate but may be a deposited film including boron (B) and phosphorus (P), such as a BSG film, a PSG film, a BPSG film, a TEOS film, or the like.
- the insulating film 81 may be a film generally used as an interlayer insulating film including nitrogen (N), carbon (C), fluorine (F) or the like.
- a cap layer 30 can be used between a gate insulating film 21 and a channel region (e.g., a polycrystalline germanium layer) 10 of the planar-structure junctionless type FET.
- the field-effect transistor 1 of the embodiment may be a double-gate-structure field-effect transistor.
- a polycrystalline germanium layer 10 on an insulating film 81 is divided by an insulating film 82 .
- a cap layer 30 is provided between the gate insulating film 21 and the channel region 100 . Accordingly, the threshold voltage (on-state voltage) of the FET 1 shifts to a value of a normally-off state from a value of a normally-on state in the case where no cap layer is provided between the channel region and the gate insulating film of the FET.
- the sample used for measurement of XPS is produced by forming a Si cap layer on the polycrystalline Ge layer and then forming a HfAlO film having a thickness of 2 nm on the cap layer by ALD.
- the n-type and p-type junctionless FETs including no cap layer is driven in normally-on operation.
- the gate electrode 75 of each of the FETs 7 is provided above the channel region in the well region 800 (semiconductor substrate 80 ) with a gate insulating film 71 therebetween.
- the FETs 7 are enhancement-type FETs.
- the FETs 7 include a source/drain region (diffusion region) 73 of a conductivity type different from that of the channel region in the well region 800 .
- a method for forming each film (layer) may include a well-known deposition method such as sputtering, vapor deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), pulse laser deposition (PLD) and the like.
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013-255383 | 2013-12-10 | ||
| JP2013255383A JP6235325B2 (ja) | 2013-12-10 | 2013-12-10 | 電界効果トランジスタ及びその製造方法、半導体デバイス及びその製造方法 |
| PCT/JP2014/082755 WO2015087935A1 (ja) | 2013-12-10 | 2014-12-10 | 電界効果トランジスタ及びその製造方法、半導体デバイス及びその製造方法 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2014/082755 Continuation WO2015087935A1 (ja) | 2013-12-10 | 2014-12-10 | 電界効果トランジスタ及びその製造方法、半導体デバイス及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20160197076A1 US20160197076A1 (en) | 2016-07-07 |
| US9613961B2 true US9613961B2 (en) | 2017-04-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US15/066,880 Active US9613961B2 (en) | 2013-12-10 | 2016-03-10 | Field-effect transistor and semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9613961B2 (ja) |
| JP (1) | JP6235325B2 (ja) |
| WO (1) | WO2015087935A1 (ja) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160300857A1 (en) * | 2015-04-07 | 2016-10-13 | Stmicroelectronics, Inc. | Junctionless finfet device and method for manufacture |
| JP6839939B2 (ja) * | 2016-07-26 | 2021-03-10 | 株式会社Ｓｃｒｅｅｎホールディングス | 熱処理方法 |
| JP6839940B2 (ja) | 2016-07-26 | 2021-03-10 | 株式会社Ｓｃｒｅｅｎホールディングス | 熱処理方法 |
| JP6645940B2 (ja) * | 2016-09-20 | 2020-02-14 | キオクシア株式会社 | 不揮発性半導体記憶装置 |
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| US20160197076A1 (en) | 2016-07-07 |
| JP2015115415A (ja) | 2015-06-22 |
| WO2015087935A1 (ja) | 2015-06-18 |
| JP6235325B2 (ja) | 2017-11-22 |
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