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US6173347B1 - Process and arrangement for transmitting system-specific data in a synchronous microprocessor system - Google Patents

Process and arrangement for transmitting system-specific data in a synchronous microprocessor system Download PDF

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US6173347B1
US6173347B1 US09/142,672 US14267298A US6173347B1 US 6173347 B1 US6173347 B1 US 6173347B1 US 14267298 A US14267298 A US 14267298A US 6173347 B1 US6173347 B1 US 6173347B1
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incompatible
data
microprocessor
compatible
arrangement
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Norbert Emmerich
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Definitions

  • the invention relates to a method for transmitting system-specific data in a synchronous microprocessor system, and an arrangement for transmitting the system-specific data in the synchronous microprocessor system.
  • a microprocessor system is the functional unit consisting of a microprocessor, a memory, and a control unit for peripheral equipment, said system being respectively built into a multiplicity of technical apparatuses.
  • the microprocessor is thereby a universally applicable and freely programmable functional unit designated the central unit (Central Processing Unit CPU), and which contains the complete control and computing unit of the microprocessor system and is housed on or more integrated circuits (chip).
  • the term peripheral equipment refers to such devices as can be connected to the microprocessor.
  • the peripheral apparatuses of the microprocessor are divided, according to their function, into peripheral memory equipment, input/output peripheral equipment, and peripheral control equipment.
  • the peripheral memory equipment thereby includes devices provided for the storage of extensive databases, e.g. magnetic layer storage units and magnetic bubble memories.
  • the input/output peripheral equipment includes functional units for the input and output of data, e.g. printer, monitor, etc.
  • the peripheral control equipment includes apparatuses that supply peripheral input/output equipment with control signals (apparatus management).
  • microprocessor system indicated above is used for example in telecommunication terminal equipment of wireless telecommunication systems.
  • Wireless telecommunication systems of the type designated above are message systems with a remote data transmission path between a message source and a message sink for message processing and message transmission, in which
  • the message processing and message transmission can take place in a preferred direction of transmission (Simplex operation) or in both directions of transmission (duplex operation),
  • the message transmission via the remote data transmission path is wireless—e.g. according to various radio standards such as DECT, GSM, WACS or PACS, IS-54, PHS, PDC, etc. (cf. IEEE Communications Magazine, January 1995, pages 50-57; D. D. Falconer et al: “Time Division Multiple Access Methods for Wireless Personal Communications”).
  • Message is a higher-order term that stands both for the meaning content (information) and also for the physical representation (signal).
  • Signals can thereby represent e.g.
  • FIG. 1 shows, as a representative of the large number of wireless telecommunication systems, a DECT/GAP system in which, according to the DECT/GAP standard (Digital European Cordless Telecommunication; cf. (1): barker Elektronik 42 (1992) January/February no. 1, Berlin, DE; U. Pilger “Struktur des DECT-Standards,” pp. 23 to 29 in connection with ETSI publication ETS 300175-1 . . . , Oct. 9, 1992; (2): Telcom Report 16 (1993), no. 1, J. H.
  • DECT/GAP standard Digital European Cordless Telecommunication
  • ETSI Publication prETS 300444, April 1995, Final Draft, ETSI, FR at a DECT/GAP base station BS, via a DECT/GAP air interface designed for the frequency range between 1.88 and 1.90 Ghz, a maximum of twelve connections according to the TDMA/FDMA/TDD method (Time Division Multiple Access/Frequency Division Multiple Access/Time Division Duplex) are set up parallel to DECT/GAP mobile parts MT1 . . . MT12.
  • the connections can thereby be internal and/or external.
  • two mobile parts registered at the base station BS can communicate with one another.
  • the base station BS is connected with a telecommunication network TKN, e.g. in line-bound form via a telecommunication terminal unit TAE, or, respectively, a private branch exchange NStA, with a line-bound telecommunication network, or, according to WO 95/05040, in wireless form as a repeater station with a higher-order telecommunication network.
  • a mobile part e.g.
  • the base station BS has only one terminal to the telecommunication terminal unit TAE or, respectively, to the private branch exchange NStA, then only one external connection can be set up.
  • the Gigaset 952 Siemens cordless telephone, cf. Telcom Report 16, 1993, no.
  • the base station BS has two terminals to the telecommunication network TKN, then in addition to the external connection with the mobile part MT1 a further external connection from a wire-bound telecommunication terminal apparatus TKE connected to the base station BS is possible.
  • a second mobile part e.g. the mobile part MT12, instead of the telecommunication terminal apparatus TKE, uses the second terminal for an external connection.
  • the mobile parts MT1 . . . MT12 are operated in manual operation (normal operation) with a battery or an accumulator, and in hands-free operation are operated in connection with a charge station connected to a voltage network SPN.
  • the base station fashioned as a wireless small switching installation, is connected to the voltage network SPN via a network terminal apparatus NAG.
  • FIG. 2 shows, on the basis of the reference Components 31 (1993), no. 6, pages 215-218; S. Althammer, D. Br ⁇ umlaut over (u) ⁇ ckmann: “Hochoptimiert IC's f ⁇ umlaut over (u) ⁇ r DECT-Schnurlostelefone,” the circuit design of the base station BS and of the mobile part MT.
  • the base station BS and the mobile part comprise, according to the reference, a radio part FKT with an antenna ANT allocated for the transmission and reception of radio signals, a signal processing means SVE, and a central control unit ZST, connected with one another in the manner shown.
  • the radio part FKT essentially the known means, such as transmitter SE, receiver EM, and synthesizer SYN, are contained.
  • a coding/decoding means CODEC is contained in the signal processing means SVE.
  • the central control unit ZST comprises, both for the base station BS and also for the mobile part MT, a microprocessor ⁇ P, having a program module PGM constructed according to the OSI/ISO layer model, a signal control part SST, and a digital signal processor DSP, connected with one another in the manner shown.
  • a microprocessor ⁇ P having a program module PGM constructed according to the OSI/ISO layer model
  • a signal control part SST and a digital signal processor DSP, connected with one another in the manner shown.
  • the signal control part SST is fashioned in the base station BS as a time switch controller TSC and in the mobile part MT as a burst mode controller BMC.
  • the essential difference between the two signal control parts TSC, BMC is that the base-station-specific signal control part TSC takes over additional switching functions in relation to the mobile-part-specific signal control part BMC.
  • the microprocessor ⁇ P is, according to the definition indicated above, a component of a microprocessor system.
  • the specified circuit design according to FIG. 2 is supplemented in the base station BS and the mobile part MT by additional functional units according to their function in the DECT/GAP system according to FIG. 1 .
  • the base station BS is connected with the telecommunication network TKN via the signal processing means SVE and the telecommunication terminal unit TAE or, respectively, the private branch exchange NStA.
  • the base station BS can also comprise a user interface (functional units drawn in with dotted lines in FIG. 2 ), consisting for example of an input means EE fashioned as a keyboard, a display means AE fashioned as a display, a speech/hearing means SHE fashioned as a handset with microphone MIF and earpiece HK, as well as a tone call bell TRK.
  • the mobile part MT comprises the user interface, possible as an option in the base station BS, with the above-described operating elements belonging to this user interface.
  • FIG. 3 shows a synchronous microprocessor system ⁇ PS, in which for example the microprocessor ⁇ P according to FIG. 2 is connected with external peripheral equipment via a synchronous system bus SB syn for data transmission.
  • the external apparatuses are for example a memory SP fashioned as a E 2 PROM and a digital-analog circuit DAC. The known functioning of these external apparatuses in connection with the microprocessor ⁇ P is not discussed in more detail.
  • the transmission of the data (addressing and useful data) between the microprocessor ⁇ P and the external apparatuses SP, DAC on the synchronous system bus SB syn takes place in chronologically synchronized fashion or, respectively, according to a predetermined data transmission pulse.
  • the system bus SB syn comprises two lines, a clock signal line TSL and a data line DL.
  • the data are thereby transmitted according to an agreed-upon system-specific protocol, which is in principle freely selectable. In the present case, this protocol is, according to the reference Funk-Technik 39 (1984), No. 4, pages 162 through 166; Schmidt, W. P.: “Bussysteme-Veritatienweg Mon Art, etc.
  • the microprocessor ⁇ P comprises a control means STE (controller), which correspondingly supports the data transmission on the synchronous system bus SB syn fashioned as an I 2 C bus as a result of the agreed-upon protocol.
  • Microprocessor ⁇ external apparatuses can be regarded as a master-slave configuration, in which the microprocessor ⁇ P can be designated the master apparatus ME and the memory SP can be designated the first slave apparatus SLE1 with a first slave address SLA1 for the addressing, and the digital-analog circuit DAC can be designated as the second slave apparatus SLE2 with a second slave address SLA2 for the addressing.
  • the master-slave configuration defined in this way, there are no compatibility problems between “master” and “slave/slaves,” so that the two slave apparatuses SLE1, SLE2 are compatible with the master apparatus ME, i.e., are system-compatible.
  • FIG. 4 shows the signal curves that occur according to the I 2 C specification on the clock signal line TSL and on the data line DL.
  • the slave address SLA1, SLA2 is sent. This is recognized by the memory SP and the digital-analog circuit DAC as their own, so that, in accordance with sequence, the subsequently transmitted data are interpreted/received by the memory SP and the digital-analog circuit DAC.
  • a further external (peripheral) apparatus e.g. a display means AE fashioned as a display
  • a display means AE fashioned as a display
  • this incompatible display means AE with the microprocessor ⁇ P via separate additional lines ZL between the microprocessor ⁇ P and the display means AE and program-supported driver means TRM.
  • the underlying object of the invention is that, in a synchronous microprocessor system, an apparatus that is system-incompatible in relation to the system-specific data transmission can be supplied with apparatus-specific data in a simple manner without an additional hardware outlay at the microprocessor.
  • the present invention is a method for transmitting system-specific data in a synchronous microprocessor system. Addressing data and useful data are transmitted between a microprocessor and at least one system-compatible system-specific apparatus, as well as at least one system-incompatible system-specific apparatus, on a first line. Clock signals are transmitted on a second line, the first and second lines forming a system bus. First addressing data and first useful data destined for the system-compatible apparatus are transmitted on the first line. Second addressing data and second useful data destined for the system-incompatible apparatus are transmitted on the first line. Third addressing data, likewise destined for the system-incompatible apparatus, is transmitted on a control line between the microprocessor and the system-incompatible apparatus. Free addresses are respectively assigned to the system-compatible apparatus and to the system-incompatible apparatus.
  • the first addressing data, the second addressing data, the first useful data and the second useful data are transmitted on a I 2 C bus according to an I 2 C protocol.
  • the third addressing data contains chip select information.
  • the system-compatible apparatus is an E 2 PROM.
  • the system-incompatible apparatus is an optical display device.
  • the method is utilized in a wireless hand apparatus of a wireless telecommunication system that operates according to a DECT/GAP standard.
  • the method is utilized in a wireless base station of a wireless telecommunication system that operates according to a DECT/GAP standard.
  • the method is utilized in a mobile radiotelephone hand apparatus of a mobile radiotelephone telecommunication system that operates according to a GSM standard.
  • the method is utilized in a mobile radiotelephone base station of a mobile radiotelephone telecommunication system that operates according to a GSM standard.
  • the present invention is also an arrangement for the transmission of system-specific data in a synchronous microprocessor system.
  • the arrangement has the following components:
  • microprocessor and at least one system-compatible system-specific apparatus as well as at least one system-incompatible system-specific apparatus, between which addressing data and useful data are transmitted;
  • a system bus between the microprocessor and the system-compatible apparatus as well as the system-incompatible apparatus, on which first addressing data and first useful data destined for the system-compatible apparatus and second addressing data and second useful data destined for the system-incompatible apparatus are transmitted on a first line, and clock signals are respectively transmitted on a second line;
  • the underlying idea of the invention is that, on the basis of the microprocessor system indicated in the introduction to the specification and the technical application thereof, in particular in wireless telecommunication systems, given data accesses of a microprocessor of the microprocessor system to peripheral apparatuses of the microprocessor (e.g. a memory, a digital-analog circuit, a display means) that are system-compatible and system-incompatible with respect to data transmission protocols (e.g. I 2 C protocol), data (addressing and useful data) are transmitted via a synchronous system bus in target-directed and thereby collision-free manner, in that
  • data transmission protocols e.g. I 2 C protocol
  • a control signal fashioned e.g. as a chip select signal, is transmitted for the selection of the system-compatible and system-incompatible external (peripheral) apparatuses of the microprocessor, and
  • FIG. 1 depicts a prior art DECT/GAP system
  • FIG. 2 is a block diagram of a prior art base station and mobile part
  • FIG. 3 depicts a prior art synchronous microprocessor system
  • FIG. 4 shows signal curves in the FIG. 3 system
  • FIG. 5 shows, on the basis of the known microprocessor system according to FIG. 3, a modified microprocessor system
  • FIG. 6 shows the signal curves that occur according to the I 2 C specification on the clock signal line and the data line according to FIG. 5 for the data transmission between the microprocessor and the display means
  • FIG. 7 shows the signal curves that occur according to the I 2 C specification on the clock signal line and the data line according to FIG. 5 for the data transmission between the microprocessor and the memory or, respectively, digital-analog circuit.
  • FIG. 5 shows a modified microprocessor system ⁇ PS m , in which the system-incompatible display means AE according to FIG. 3, like the system-compatible memory SP and the system-compatible digital-analog circuit DAC according to FIG. 3, is connected with the microprocessor ⁇ P via the synchronous system bus SB syn and, in addition, via a single control line SL.
  • the program-supported driver means TRM in the microprocessor ⁇ P required in the known microprocessor system ⁇ PS according to FIG. 3, can be omitted, and the additional lines ZL can be replaced by the single control line SL.
  • the microprocessor ⁇ P of the control means STE contains allocated control means STM, fashioned in such a way that a data transmission is possible that is target-directed and thereby collision-free with respect to the accesses. This takes place in that
  • a control signal SS fashioned as a chip select signal, is transmitted for the selection of the system-compatible and system-incompatible external (peripheral) means of the microprocessor ⁇ P, and
  • a free virtual slave address or addresses SLA v is/are assigned to the system-incompatible apparatus(es), which address or addresses has/have not yet been allocated to the other apparatuses.
  • control means STM require no additional terminal contacts (pins) at the microprocessor ⁇ P (simplification of layout in the chip design of the microprocessor).
  • existing control means STE can be used (optimal exploitation of the existing processor performance).
  • FIG. 6 shows the signal curves that occur according to the I 2 C specification on the clock signal line TSL and the data line DL according to FIG. 5 for the data transmission between the microprocessor ⁇ P and the display means AE.
  • the virtual slave address SLA v is sent. This is not recognized by the memory SP and the digital-analog circuit DAC as their own, so that consequently the subsequently transmitted data are not interpreted/received by the memory SP and the digital-analog circuit DAC.
  • control signal SS is sent after the transmission of the virtual slave address SLA v and before the data transmission on the control line SL (setting of the chip select signal to HIGH potential)
  • the system-incompatible display means AE is thereby activated for the reception of the data subsequently transmitted on the system bus SB syn .
  • FIG. 7 shows the signal curves occurring according to the I 2 C specification on the clock signal line TSL and the data line DL according to FIG. 5 for the data transmission between the microprocessor ⁇ P and the memory SP or, respectively, the digital-analog circuit DAC.
  • the response of the system-compatible memory SP or, respectively, of the system-compatible digital-analog circuit DAC takes place as in FIG. 4 .
  • the control signal SS is not sent on the control line SL (chip select signal at LOW potential)
  • the system-incompatible display means AE is not activated.
  • the subsequently transmitted data on the clock signal line TSL and the data line DL are thus not interpreted or, respectively, received by the display means AE.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
US09/142,672 1996-03-13 1997-03-12 Process and arrangement for transmitting system-specific data in a synchronous microprocessor system Expired - Fee Related US6173347B1 (en)

Applications Claiming Priority (3)

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DE19609883 1996-03-13
DE19609883A DE19609883C1 (de) 1996-03-13 1996-03-13 Verfahren und Anordnung zum Übertragen von systemspezifischen Daten in einem synchronen Mikroprozessorsystem
PCT/DE1997/000491 WO1997034238A1 (fr) 1996-03-13 1997-03-12 Procede et dispositif pour transmettre des donnees specifiques du systeme dans un systeme synchrone a microprocesseur

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EP (1) EP0886828B1 (fr)
DE (2) DE19609883C1 (fr)
ES (1) ES2143303T3 (fr)
TW (1) TW362179B (fr)
WO (1) WO1997034238A1 (fr)

Cited By (4)

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Publication number Priority date Publication date Assignee Title
CN100362502C (zh) * 2005-05-26 2008-01-16 海信集团有限公司 I2c总线数据的无线传输系统
US20150370735A1 (en) * 2014-06-18 2015-12-24 Qualcomm Incorporated Dynamically adjustable multi-line bus shared by multi-protocol devices
US10241955B2 (en) * 2014-06-18 2019-03-26 Qualcomm Incorporated Dynamically adjustable multi-line bus shared by multi-protocol devices
US20210358510A1 (en) * 2020-05-12 2021-11-18 Yealink (Xiamen) Network Technology Co., Ltd. Dect base station, mobile terminal and system for transmitting data frame

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10036643B4 (de) * 2000-07-26 2005-12-22 Robert Bosch Gmbh Verfahren und Vorrichtung zur Auswahl von Peripherieelementen
WO2019070361A1 (fr) * 2017-10-03 2019-04-11 Qualcomm Incorporated Bus multilignes à réglage dynamique partagés par des dispositifs multiprotocoles

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US4958277A (en) 1987-07-24 1990-09-18 Motorola, Inc. Queued serial peripheral interface for use in a data processing system
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US5873033A (en) * 1995-02-06 1999-02-16 Telia Ab Method and arrangement for transfer between a cordless telecommunication system and a cellular mobile telecommunication system

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US5376928A (en) * 1992-09-18 1994-12-27 Thomson Consumer Electronics, Inc. Exchanging data and clock lines on multiple format data buses
WO1995005040A1 (fr) 1993-08-06 1995-02-16 Siemens Aktiengesellschaft Systeme de telecommunications mobile universel
EP0693729A1 (fr) 1994-07-15 1996-01-24 Thomson Consumer Electronics, Inc. Système de bus de données de plusieurs protocoles
US5873033A (en) * 1995-02-06 1999-02-16 Telia Ab Method and arrangement for transfer between a cordless telecommunication system and a cellular mobile telecommunication system

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ETSI-Publication, Oct. 1992, ETS 300175 1 . . . 9, Part 1: Overview, pp. 1-30; Part 2: Physical layer, pp. 1-39; Part 3: Medium access control layer, pp. 1-197; Part 4: Data link control layer, pp. 1-128; Part 5: Network layer, pp. 1-241; Part 6: Identities and addressing, pp. 1-41; Part 7: Security features, pp. 1-104; Part 8: Speech coding and transmission, pp. 1-39; Part 9: Public access profile, pp. 1-71.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100362502C (zh) * 2005-05-26 2008-01-16 海信集团有限公司 I2c总线数据的无线传输系统
US20150370735A1 (en) * 2014-06-18 2015-12-24 Qualcomm Incorporated Dynamically adjustable multi-line bus shared by multi-protocol devices
JP2017520053A (ja) * 2014-06-18 2017-07-20 クアルコム，インコーポレイテッド マルチプロトコルデバイスによって共有される動的調整可能なマルチラインバス
US10007628B2 (en) * 2014-06-18 2018-06-26 Qualcomm Incorporated Dynamically adjustable multi-line bus shared by multi-protocol devices
US10241955B2 (en) * 2014-06-18 2019-03-26 Qualcomm Incorporated Dynamically adjustable multi-line bus shared by multi-protocol devices
US20210358510A1 (en) * 2020-05-12 2021-11-18 Yealink (Xiamen) Network Technology Co., Ltd. Dect base station, mobile terminal and system for transmitting data frame
US11640828B2 (en) * 2020-05-12 2023-05-02 Yealink (Xiamen) Network Technology Co., Ltd. DECT base station, mobile terminal and system for transmitting data frame

Also Published As

Publication number Publication date
DE59701068D1 (de) 2000-03-02
WO1997034238A1 (fr) 1997-09-18
EP0886828B1 (fr) 2000-01-26
EP0886828A1 (fr) 1998-12-30
ES2143303T3 (es) 2000-05-01
TW362179B (en) 1999-06-21
DE19609883C1 (de) 1997-10-09

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